JPH1032266A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a process where a silicon nitride film is formed on an silicon oxide film to serve also as a thermal treatment where the lower silicon oxide film is enhanced in density by a method wherein the forming temperature of the silicon nitride film is optimized. SOLUTION: A silicon oxide film 22 is formed on the gate electrode 16 of a transistor provided onto a semiconductor substrate 10. Then, a silicon nitride film 24 is formed on the silicon oxide film 22, whereby the silicon oxide film 22 is enhanced in density. A contact hole 26 is provided to the silicon nitride film 24 and the silicon oxide film 22 facing to the surface of the semiconductor substrate 10. Then, a semiconductor layer 28 serving as a resistor load device layer is formed on the silicon nitride film 24 so as to penetrate into the contact hole 26. That is, when the silicon nitride film 24 is formed on the silicon oxide film 22, the forming temperature of the silicon nitride film 24 is optimized. By this setup, a process where the silicon nitride film 24 is formed is made to serve also as a thermal treatment by which the lower silicon oxide film 22 is enhanced in density.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MIS transistor (MO) such as a high resistance load type SRAM.
More specifically, the present invention relates to a method for manufacturing a semiconductor device having an S transistor (including an S transistor) and a resistive load element. The present invention relates to a method for manufacturing a semiconductor device which can reduce a heat treatment step for densifying a silicon oxide film.

[0002]

2. Description of the Related Art The demand for 0.35 μm SRAMs is overwhelmingly higher in high-speed operation types than in low-power consumption types. Therefore, it is not necessary to use a TFT as a load element, and the function as a resistance element is sufficient.
Conventional high resistance loads are re-emerging in the limelight to reduce costs.

[0003] Compatibility between the development of a MOS transistor suitable for such a high-speed operation and cost reduction by reducing the number of steps is very important in order to make the high resistance load type SRAM more competitive. The high-speed SRAM uses a MOS transistor having a high current driving capability for speeding up. Therefore, as a result of aggressive efforts to reduce the gate length and lower the threshold voltage, the short channel effect has become remarkable. To suppress the short channel effect, see FIG.
As shown in (1), it is very effective to reduce the total amount of heat applied to the MOS transistor.

In FIG. 13, the horizontal axis represents the gate length of the MOS transistor, the vertical axis represents the threshold voltage Vth of the MOS transistor, and the smaller the total heat treatment in the manufacturing process, the more effective the MOS transistor becomes. The gate length becomes longer, and the resistance to the short channel effect becomes stronger.

In a high resistance load type SRAM, a MOS transistor having a source / drain region on a silicon substrate, such as a driving transistor, a selection transistor, a MOS transistor of a peripheral circuit, etc., constituting a memory cell is generally formed. A semiconductor layer serving as a high resistance load element is formed thereon.

Since this semiconductor layer is made of polysilicon formed by CVD so as to cover a contact region directly connected to the semiconductor substrate, as a pretreatment before CVD,
Light etching for removing a natural oxide film formed on a semiconductor substrate is required.

[0007]

However, in order to suppress the etching of the interlayer insulating film by light etching,
As shown in FIG. 14A, after forming an interlayer insulating film 5 on a polysilicon layer 4 serving as a gate electrode, a heat treatment at about 850 ° C. is necessary as annealing for densifying the interlayer insulating film 5. It is known that

If light etching is performed without annealing, as shown in FIG. 14B, the interlayer insulating film 5a in the contact hole region 2 is etched, and a breakdown voltage failure with the underlying polysilicon layer 4 occurs. There is a possibility that. FIG. 14A shows a case where the contact hole region 2 is formed after the interlayer insulating film 5 is densified.
The breakdown voltage with the lower polysilicon layer 4 is sufficient.

A high resistance load type SRAM is disclosed in Japanese Patent Application Laid-Open No. 63-1 (1988) in order to suppress the fluctuation of the resistance value.
As disclosed in Japanese Patent No. 28733, a technique for leaving an Al wiring at a chip end on a scribe is required. In particular, a silicon nitride film is also formed on the high-resistance load element to suppress the intrusion of hydrogen, moisture, and mobile ions into the high-resistance load element, thereby suppressing the fluctuation of the resistance value.

[0010] Forming a silicon nitride film also under the high resistance load element is very effective for suppressing the fluctuation of the resistance value of the high resistance element. The present invention has been made in view of such a situation, and reduces a heat treatment step for densification of a lower silicon oxide film by optimizing a formation temperature of a silicon nitride film formed below a high resistance load element. It is an object of the present invention to provide a method of manufacturing a semiconductor device which can be manufactured and has a sufficient breakdown voltage with respect to a lower gate electrode which should not be connected in a contact hole.

[0011]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises forming a silicon oxide film on a gate electrode of a transistor formed on a semiconductor substrate. Forming a silicon nitride film on the silicon oxide film to densify the silicon oxide film, and forming a contact hole facing the surface of the semiconductor substrate in the silicon nitride film and the silicon oxide film. Forming a semiconductor layer to be a resistance load element layer on the silicon nitride film so as to enter the contact hole.

The temperature for forming the silicon nitride film is 700 °
C or higher, preferably 730 to 800 ° C. If this temperature is less than 700 ° C,
Density of the lower silicon oxide film tends to be insufficient, while heat treatment at a temperature higher than 800 ° C. is not practical because it is difficult to control the CVD film thickness of the nitride film.

Preferably, light etching is performed to remove the silicon oxide thin film formed on the surface of the semiconductor substrate exposed at the bottom of the contact hole. The light etching is performed using, for example, a solution containing hydrofluoric acid. In forming the contact hole,
In order to obtain a shared contact, a contact hole may be formed so that a part of the gate electrode is also exposed.

Further, a method called buried contact may be used in which a contact hole is also opened in the wiring layer constituting the gate electrode and the gate electrode and the resistance element are directly connected. The transistors formed on the semiconductor substrate are, for example, an SRAM driving transistor and a selection transistor, and the semiconductor layer serving as the resistance load element layer is a load resistance of the SRAM.

In the method for manufacturing a semiconductor device according to the present invention,
By forming a silicon nitride film over the silicon oxide film and optimizing the formation temperature of the silicon nitride film, heat treatment for densification of the lower silicon oxide film can be performed. Therefore, it is not necessary to separately perform a heat treatment step for densification of the silicon oxide film. As a result, while contributing to the reduction of the manufacturing process,
The total amount of heat treatment at the time of manufacturing becomes smaller, the effective gate length of the MOS transistor becomes longer, and the resistance to the short channel effect becomes stronger.

According to the present invention, since the silicon oxide film is densified, the silicon oxide film has a sufficient withstand voltage with respect to the lower gate electrode which should not be connected in the contact hole. Further, in the present invention, by forming the silicon nitride film below the high-resistance load element, it is very effective in suppressing the fluctuation of the resistance value of the high-resistance load element.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described in detail based on an embodiment shown in the drawings. First, an equivalent circuit diagram of a memory cell of a high resistance load type SRAM is shown in FIG.

As shown in FIG. 10, the memory cell of the SRAM, the flip-flop circuit constituted by a pair of drive transistors T _3, T _4, the driving transistor T _3, T
It has a pair of load resistance elements R ₁ and R ₂ electrically connected to the _four storage node units N ₁ and N ₂ , respectively. The storage node units N ₁ and N ₂ are connected to a bit line b and an inverted bit line b ′ via selection transistors T ₁ and T ₂ , respectively.

The gate electrodes of the select transistors T ₁ and T ₂ also serve as the word line W. In such an SRAM memory cell, in the storage node portions N ₁ and N ₂ , the high-resistance load elements R ₁ and R ₂ , the source / drain regions of the transistors T _{1 to} T ₄ , and the transistors T ₁ and T ₂ Since it is necessary to connect to a gate electrode, a shared contact as described later is employed in a process of manufacturing a semiconductor device.

Next, a method of manufacturing an SRAM as a semiconductor device according to an embodiment of the present invention will be described. In the following description, only the main part (peripheral part of the shared contact) of the SRAM memory cell will be illustrated, and the manufacturing process thereof will be described.

As shown in FIG. 1, first, a semiconductor substrate 10
An element isolation region 12 having a thickness of, for example, 350 nm is formed thereon.
Is formed using a LOCOS method using a silicon nitride film. As the semiconductor substrate 10, for example, a silicon single crystal wafer is used. Next, as shown in FIG. 2, a P well region 13 which is a P type impurity region is formed by boron ion implantation. After that, a gate insulating film 14 is formed on the surface of the semiconductor substrate 10 located between the element isolation regions 12. The gate insulating film 14 is made of, for example, a silicon oxide film and is formed by a thermal oxidation method or the like. The thickness of the gate insulating film 14 is not particularly limited.
It is about.

Next, a polysilicon layer to be the gate electrode 16 of the MOS transistor is formed on the gate insulating film 14. In the present embodiment, the gate electrode 16 is a polycide layer (laminated structure of a polysilicon layer and a silicide layer), and is formed by sequentially laminating a polysilicon layer 120 nm and a tungsten silicide layer 120 nm.

In this embodiment, since an example of an SRAM will be described, the driving transistors T ₃ and T ₄ and the selection transistors T ₁ and T _{1 of} the SRAM memory cell shown in FIG.
And T _2, the gate electrode of the MOS transistor of the peripheral circuit (not shown) formed in the polycide layer above. Next, after the gate electrode 16 is etched in a predetermined pattern, an N-type impurity such as arsenic is ion-implanted into a portion serving as a source / drain region to form an LDD region (low-concentration diffusion layer) 18.

Next, as shown in FIG. 3, an interlayer insulating film made of a silicon oxide film is formed to a thickness of, for example, 300 nm, and a side wall 19 is formed on the side of the gate electrode 16 by anisotropic etching such as RIE. Form. afterwards,
N-type impurities such as arsenic are ion-implanted to form source / drain regions 20 (high-concentration diffusion layers). The conditions for this ion implantation are not particularly limited. For example, the implantation energy is about 20 keV and the dose is 2 × 10
¹⁵ / cm ² .

Next, as shown in FIG. 4, a silicon oxide film 22 is formed with a thickness of about 100 nm. Here,
Conventionally, annealing at about 850 ° C. for 15 minutes was required to densify the silicon oxide film 22. But,
In the present embodiment, this annealing step is omitted, and the silicon nitride (Si ₃ N ₄ ) film 2 is formed on the silicon oxide film 22.
4 is formed by low pressure CVD. The Si ₃ N ₄ film 24 is
It is effective as a stopper for moisture, hydrogen and mobile ions, and is also important in guaranteeing the interlayer breakdown voltage of the underlying silicon oxide film.

In the present embodiment, the silicon nitride film 24 is
Low pressure (LP) -CVD for 2-5 hours
The film is formed with a thickness of about 5 to 30 nm by applying heat of 0 ° C. or more. By forming the silicon nitride film 24 by applying such heat, densification of the lower silicon oxide film 22 is achieved.

Next, as shown in FIG. 5, the silicon nitride film 22 and the silicon oxide film 22 are directed toward the source / drain regions 20 to be the storage nodes N ₁ and N ₂ shown in FIG.
Is etched in a predetermined pattern to form contact holes 26.
To form In the present embodiment, the contact hole 2
Reference numeral 6 denotes a contact hole formed in the storage nodes N ₁ and N ₂ shown in FIG. 10, which must be connected to the gate electrodes of the selection transistors T ₃ and T ₄ , and are shared contacts. is there. In addition,
Contact hole and wire for source / drain 20
Alternatively, contact holes for the lead lines may be formed at the same time, and these may be connected.

Next, light etching is performed to remove the inside of the contact hole 26, particularly, the natural oxide film on the semiconductor substrate 10. If the heat treatment for densification of the underlying silicon oxide film 22 is not sufficient during this light etching, the silicon oxide film below the silicon nitride film 24 is side-etched as shown in FIG. There is a risk of causing an interlayer breakdown voltage failure.
For example, as shown in FIG. 11, the heat treatment temperature (horizontal axis) of the silicon oxide film 22 and the buffered hydrofluoric acid (HF: NH
The etching rate (vertical axis) of the silicon oxide film 22 when the ratio with ₄ F is 1: 400) has a fixed relationship, and when the annealing time is constant (the annealing time in FIG. 11 is 10 minutes). The higher the heat treatment temperature, the lower the etching rate. This is considered because the quality of the silicon oxide film is increased. Therefore, the silicon oxide film 2
If the silicon oxide film 2 is not sufficiently heat-treated, the silicon oxide film under the silicon nitride film 24 is side-etched as shown in FIG. . A solution that can be used in the light etching is, for example, a solution containing hydrofluoric acid, and its concentration is HF: H ₂ O = 1: 100 to 1:20.
It may be about 0 and is not limited.

On the other hand, performing both the heat treatment step for densification of the silicon oxide film 22 and the formation step of the silicon nitride film 24 separately for the purpose of securing the resistance value fluctuation and the breakdown voltage of the resistance load is performed separately. As shown in FIG. 13, the total amount of heat treatment increases, which is extremely disadvantageous for the short channel effect. On the other hand, it is not a good idea from the viewpoint of cost reduction.

In the present embodiment, the silicon nitride film 24 is formed on the silicon oxide film 22, and at this time, the formation temperature of the silicon nitride film 24 is optimized to reduce the density of the lower silicon oxide film 22. Heat treatment for the purpose. Therefore, the silicon oxide film 2
It is not necessary to perform a heat treatment step for densification of Step 2. As a result, at the same time as contributing to a reduction in the number of manufacturing steps, the total heat treatment amount during manufacturing is reduced, the effective gate length of the MOS transistor is increased, and the MOS transistor is more resistant to the short channel effect.

In this embodiment, the silicon oxide film 2
2 is densified, so that the result is not as shown in FIG.
, And has a sufficient breakdown voltage with respect to the lower gate electrode 16a which should not be connected in the contact hole 26. Further, in the present invention, by forming the silicon nitride film below the high-resistance load element, it is very effective in suppressing the fluctuation of the resistance value of the high-resistance load element.

Next, in this embodiment, as shown in FIG. 6, a polysilicon layer 28 as a semiconductor layer which becomes a high resistance load element after light etching is formed, for example, by 50 nm.
The thickness is formed by CVD. Next, As for determining the resistance value of the high resistance load element is ion-implanted on the entire surface of the polysilicon layer 28. Thereafter, as shown in FIG. 7, the polysilicon layer 28 is patterned by RIE,
A pattern is formed to selectively apply As to the polysilicon layer 28.
To form a power supply line Vcc (see FIG. 10).

As shown in FIG. 8, a silicon oxide film 30 is formed as an interlayer insulating film, and a silicon nitride film serving as a stopper for moisture, hydrogen, and mobile ions is deposited thereon for about 5 minutes.
It is formed with a thickness of about 30 nm by CVD or the like. Thereafter, as shown in FIG. 9, the BPSG layer 34 is
After forming with a thickness of about 0 nm, flattening by reflow, a metal wiring layer 36 is formed after forming a contact region of a metal wiring layer (not shown). The metal wiring layer 36 is made of, for example, a barrier metal layer and Al containing Cu.
The wiring layer is formed. This metal wiring layer 36 becomes a bit line or the like.

Next, after forming the interlayer insulating film 38, although not shown, after forming a second Al wiring layer, a silicon nitride film (SiN film) to be an overcoat film is formed by plasma CVD.
Film). In the present embodiment, as described above, both the heat treatment step for densification of the silicon oxide film and the formation step of the silicon nitride film for securing the resistance value variation of the resistance load and the withstand voltage are separately performed. Since it is not performed, it is very advantageous for the short channel effect (short channel effect). On the other hand, it is very advantageous from the viewpoint of cost reduction. Therefore, the turnaround time (TA
T) can also be shortened.

It should be noted that the present invention is not limited to the above-described embodiment, but can be variously modified within the scope of the present invention. For example, in the above-described embodiment, the example in which the resistance load is a high resistance load has been described, but a thin film transistor (TFT) may be used as the resistance element. Also, SR
Although described as a method of manufacturing an AM, in addition to the SRAM,
It can be widely applied as a technique for manufacturing a semiconductor device having a MIS transistor (including a MOS transistor) and a resistance load element. In addition, the conductivity types and manufacturing conditions of the semiconductor impurities in the above-described embodiments are merely examples, and can be variously modified in the present invention.

[0036]

As described above, according to the method of manufacturing a semiconductor device according to the present invention, a silicon nitride film is formed on a silicon oxide film, and at this time, the temperature for forming the silicon nitride film is optimized. This makes it possible to also serve as a heat treatment for densifying the lower silicon oxide film. Therefore, it is not necessary to separately perform a heat treatment step for densification of the silicon oxide film. As a result, at the same time as contributing to a reduction in the number of manufacturing steps, the total heat treatment amount during manufacturing is reduced, the effective gate length of the MOS transistor is increased, and the MOS transistor is more resistant to the short channel effect.

In the present invention, since the silicon oxide film is densified, it has a sufficient withstand voltage with respect to the lower gate electrode which should not be connected in the contact hole. Further, in the present invention, by forming the silicon nitride film below the high-resistance load element, it is very effective in suppressing the fluctuation of the resistance value of the high-resistance load element.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view showing a manufacturing process of an SRAM according to an embodiment of the present invention;

FIG. 2 is an essential part cross sectional view showing a step that follows the step shown in FIG. 1;

FIG. 3 is an essential part cross sectional view showing a step that follows the step shown in FIG. 2;

FIG. 4 is a fragmentary cross-sectional view showing a step that follows the step shown in FIG. 3;

FIG. 5 is an essential part cross sectional view showing a step continued from FIG. 4;

FIG. 6 is an essential part cross sectional view showing a step that follows the step shown in FIG. 5;

FIG. 7 is an essential part cross sectional view showing a step that follows the step shown in FIG. 6;

FIG. 8 is an essential part cross sectional view showing a step that follows the step shown in FIG. 7;

FIG. 9 is an essential part cross sectional view showing a step that follows the step shown in FIG. 8;

FIG. 10 is an equivalent circuit diagram of an SRAM memory cell.

FIG. 11 is a graph showing the relationship between annealing heat treatment and the etching rate of a silicon oxide film.

FIG. 12 is a cross-sectional view of a principal part when the densification of the silicon oxide film is insufficient.

FIG. 13 is a graph showing the relationship between the total heat treatment, the gate length of the MOS transistor, and Vth.

14 (A) and (B) are SRA according to a conventional example.
It is principal part sectional drawing which shows the manufacturing process of M.

[Explanation of symbols]

10 semiconductor substrate 12 element isolation region 16
Gate electrode, 20 ... source / drain region, 22 ...
Silicon oxide film, 24 silicon nitride film, 26 contact hole, 28 polysilicon layer (semiconductor layer).

Claims (7)

[Claims] A step of forming a silicon oxide film over a gate electrode of a transistor formed over a semiconductor substrate; and forming a silicon nitride film over the silicon oxide film to form a dense silicon oxide film. Forming a contact hole facing the surface of a semiconductor substrate in the silicon nitride film and the silicon oxide film; and forming a resistive load element layer on the silicon nitride film so as to enter the contact hole. Forming a semiconductor layer to be a semiconductor device. 2. The method according to claim 1, wherein the forming temperature of the silicon nitride film is 700.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the temperature is not lower than ° C. 3. After the contact hole forming step and before forming a resistance load element layer, light etching is performed to remove a silicon oxide thin film formed on the surface of the semiconductor substrate exposed at the bottom of the contact hole. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of: 4. The method according to claim 3, wherein the light etching is performed using a solution containing hydrofluoric acid. 5. When forming the contact hole,
2. The method according to claim 1, wherein a contact hole is formed such that a part of the gate electrode is also exposed in order to obtain a shared contact. 6. The method according to claim 1, further comprising the step of forming a contact hole in the surface of the semiconductor substrate and forming a contact hole in the surface of the wiring layer forming the gate electrode.
The manufacturing method of the semiconductor device described in the above. 7. A transistor formed on the semiconductor substrate is a drive transistor and a selection transistor of an SRAM, and the semiconductor layer serving as the resistance load element layer is
2. The method for manufacturing a semiconductor device according to claim 1, wherein the method is a load resistance of an SRAM.