JPH08340052A - Semiconductor memory device and its manufacture - Google Patents

Abstract

PURPOSE: To reduce the number of masks required for manufacturing an SRAM device. CONSTITUTION: An N-type polycrystalline silicon layer 40 which is simultaneously connected to both the gate electrode (polycide layer 27) of an N-type MOS transistor 14 and the diffusion area (N<-> -type impurity area 29 and N<+> -type impurity area 36) of an N-type MOS transistor 13 is newly provided. As a result, N-N contacts are formed between the layer 40 and the gate electrode of the transistor 14 and between the layer 40 and diffusion area of the transistor 13. On the other hand, the gate electrode (polycrystalline silicon layer 47) of a TFT 15 is formed in P-type and is only brought into contact with the polysilicon layer 40 at the bottom section of an opening 46 for contact. Since the gate electrode does not come into direct contact with the N-type diffusion area, such a case that a P-type impurity is diffused in the N-type diffusion area and increases the contact resistance of the diffusion area does not occur even when the gate electrode is formed in the P-type. While a P-N contact is formed between the gate electrode and the layer 40, the operation of the gate electrode is not hindered because the electrode is connected with the layer 40 in the forward direction. Therefore, the polycrystalline silicon layer 47 can be formed in a single conductivity (P type) and the manufacturing process of a semiconductor memory can be simplified by reducing the number of necessary masks.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to SRAMs having so-called shared contacts (static random
Access memory device and a method of manufacturing the same.

[0002]

2. Description of the Related Art For example, "1994 Symposium on VLSI Tec
As described in "Hinology Digest of Technical Papers pp99-100", most of the conventional SRAMs form a contact portion at the same time on the gate electrode of the driver transistor of the memory cell and the diffusion layer of the access transistor. A shared contact for making contact with the gate electrode of (thin film transistor) is used. SRA with such shared contacts
In M, the conductive layer serving as the gate electrode of the TFT is drawn out to the peripheral circuit as a power supply line and connected to the metal wiring layer via the impurity diffusion layer at the power supply line contact portion.

FIG. 19 shows a cross section of a main part of an SRAM device having such a conventional shared contact. As shown in this figure, this SRAM device includes a memory cell formation region 11 and a peripheral circuit portion 12. In the memory cell formation region 11, the NMOS transistor 13 which is one of the pair of access transistors and the NMOS transistor 1 which is one of the pair of driver transistors in the memory cell circuit shown in FIG.
4 and a P-type TFT (thin film transistor) 15 ', which is one of a pair of load transistors. Specifically, it has the following structure.

In the memory cell formation region 11, a P-type well region 23 is formed in the upper layer region of the silicon substrate 21, and on the silicon substrate 21 of the P-type well region 23, silicon as an element isolation region is selectively formed. The oxide film 22 is formed. A so-called LDD (Lightly DoD) is formed on the P-type well region 23 partitioned by the silicon oxide film 22.
An NMOS transistor 13 having a ped drain structure is formed. That is, the polycide layer 27 is formed and patterned through the silicon oxide film 24 (gate insulating film) formed on the P-type well region 23. NM
An N ⁻ -type impurity region 29, which is a low-concentration impurity diffusion region, is formed near the surface of the P-type well region 23 adjacent to the polycide layer 27 serving as the gate electrode of the OS transistor 13. A silicon oxide film side wall 35 is formed on the side surface of the polycide layer 27 serving as the gate electrode of the NMOS transistor 13, and the P type well region 2 is self-aligned with the side wall 35.
A high concentration impurity diffusion region (N ⁺ type impurity region 36) as a source / drain region of the NMOS transistor 13 is formed near the surface of the NMOS transistor 13. NMOS transistor 1
A polycide layer 43 as a ground line (Vss) is provided on the polycide layer 27 in the region where 4 is formed via a silicon oxide film 138 as an interlayer insulating film,
Further, a silicon oxide film 45 as a flattening insulating film is formed so as to cover this. And the silicon oxide film 4
A shared contact opening 146 is formed through the holes 5, 138. N on the silicon oxide film 45
Type polycrystalline silicon layer 47 is formed, of which FIG.
At the bottom of the shared contact opening 146, the polycrystalline silicon layer 47 serving as the gate electrode of the TFT 15 in the above-mentioned TFT 15 has a gate electrode layer (polycide layer 27) of the NMOS transistor 14 and the NMOS transistor 13.
Of the source / drain regions (N ⁺ type impurity region 36 and N ⁻ type impurity region 29) are simultaneously connected and are in electrical contact. A silicon oxide film 52 having an opening 53 in a part thereof is formed on the polycrystalline silicon layer 47, and a channel region of the TFT 15 'is further formed thereon.
A polycrystalline silicon layer 56 is formed as a source / drain region and a power supply line (Vdd), and is connected to the polycrystalline silicon layer 47 in the opening 53. Then, a silicon oxide film 57 as a planarization insulating film is formed so as to cover the above element structure.

On the other hand, in the peripheral circuit section 12, a P ⁺ -type impurity region 37 as a power (Vdd) line contact region is formed near the surface of the silicon substrate 21 partitioned by the silicon oxide film 22 which is an element isolation film. Has been formed. Silicon oxide films 138 and 45 are formed on the P ⁺ type impurity region 37. Then, a power line contact opening 48 is formed through these silicon oxide films 45, 138. This opening is covered with a P-type polycrystalline silicon layer 47, and a silicon oxide film 52 having an opening 50 in part is formed thereon. A P-type polycrystalline silicon layer 56 is formed on the silicon oxide film 52, and is connected to the polycrystalline silicon layer 47 in the opening 50. As a result, the polycrystalline silicon layer 56 has the P ⁺ -type impurity region 37 at the bottom of the power line contact opening 48 via the polycrystalline silicon layer 47.
Is electrically connected to. A silicon oxide film 57 is formed on the polycrystalline silicon layer 56. Contact holes are formed in the silicon oxide films 57, 52, 45, 138 to reach the P ⁺ type impurity regions 37, and the titanium / titanium nitride layer 61 and the tungsten layer 62 are formed.
Buried by and. And the tungsten layer 6
2 is a titanium / titanium nitride layer 63, an aluminum layer 64
And a titanium nitride layer 65, which is connected to the first-layer laminated aluminum wiring 17 of a predetermined pattern.

[0006]

As described above, the polycrystalline silicon layer 47 serves as a power supply line in the peripheral circuit section 12, but in this area, it makes good contact with the P ⁺ -type impurity area 37. It is formed as a P type. On the other hand, in the memory cell formation region 11, the gate electrode of the TFT 15 is formed, but in this portion, it is formed as N type. This is because the diffusion region (N ⁺ type impurity region 36, N ⁻ type impurity region 29) in contact with the polycrystalline silicon layer 47 in the shared contact opening 146 of the memory cell formation region 11 is N type. , Polycrystalline silicon layer 47
This is because when P is made P-type, the P-type impurity propagates and diffuses into the N-type diffusion region to increase the contact resistance.
Therefore, although the polycrystalline silicon layer 47 is formed in the same step, in the subsequent ion implantation step, N-type ions are generated in the memory cell formation region 11 in the peripheral circuit portion 12.
Then, it is necessary to implant P-type ions. In order to implant ions of different conductivity types depending on the region, it is necessary to cover the other region with a mask (resist) when performing ion implantation on one region. Had to be done twice. Here, since one ion implantation process is performed in three steps of mask formation, ion implantation, and mask removal, six steps are eventually required, which is a cause of complication of the manufacturing process.

The present invention has been made in view of the above problems, and its object is to provide a gate electrode layer of a load thin film transistor, a diffusion layer of an access transistor, and a driver.
In a semiconductor memory device having a shared contact in which the gate electrode layer of a transistor is in contact at the same time,
It is an object of the present invention to provide a semiconductor memory device capable of reducing the number of masks required for forming a gate electrode layer of a load thin film transistor and simplifying the manufacturing process, and a manufacturing method thereof.

[0008]

A semiconductor memory device according to claim 1, wherein a pair of first conductivity type driver MOS transistors, a pair of first conductivity type access MOS transistors, and a pair of second conductivity types are provided. Memory device including a load type thin film transistor for load, wherein at least a partial region on the first conductivity type gate electrode layer of the driver MOS transistor is used as a source / drain region of the access MOS transistor. The first conductivity type impurity diffusion layer is extended to the first conductivity type impurity diffusion layer, and its end portion is terminated on the first conductivity type impurity diffusion layer. A first conductive type conductive layer that is in electrical contact with both of them at the same time, and an insulating layer formed so as to cover the first conductive type conductive layer and each of the transistors. A gate and a contact opening formed so as to penetrate the interlayer insulating film on the first conductive type conductive layer and reach the first conductive type conductive layer; and a gate of the load transistor. An electrode layer having a second conductivity type is formed to cover the contact opening, and
It is configured to be electrically connected to the conductive type conductive layer.

According to another aspect of the method of manufacturing a semiconductor memory device of the present invention, a pair of first conductivity type driver MOS transistors, a pair of first conductivity type access MOS transistors, and a pair of second conductivity type loads. A method of manufacturing a semiconductor memory device having a memory cell including a thin film transistor for use in a semiconductor device, the method comprising: forming a driver MOS transistor and an access MOS transistor on a semiconductor substrate;
MOS transistor for driver and MOS for access
Forming a first interlayer insulating film on the transistor, and forming a first conductive type gate electrode layer of the driver MOS transistor and an access MO on the first interlayer insulating film.
A step of forming a first opening for forming a common contact for the first-conductivity-type impurity diffusion layer as the source / driver region of the S transistor, and a first-conductivity-type so as to cover the first opening. Forming a conductive layer, etching the first conductive type conductive layer so that it terminates on the first conductive type impurity diffusion layer, and forming a second conductive layer on the first conductive type conductive layer. A step of forming an interlayer insulating film, a step of forming a second opening in the second interlayer insulating film that reaches the first conductive type conductive layer, and a load so as to cover the second opening. Forming a second conductivity type gate electrode layer of the transistor for use in the application.

[0010]

In the semiconductor memory device and the method of manufacturing the same according to the present invention, both the first conductivity type gate electrode layer of the driver MOS transistor and the first conductivity type impurity diffusion layer as the source / drain region of the access MOS transistor are formed. A first-conductivity-type conductive layer that is in electrical contact with the gate electrode layer at the same time is newly provided, and is electrically connected to the gate electrode layer of the load transistor at the bottom of the contact opening. Therefore, the gate electrode layer of the load transistor is not directly connected to the first conductivity type impurity diffusion layer, and even if the gate electrode layer of the load transistor is formed as the second conductivity type, this gate electrode layer Second
There is no possibility that the conductivity type impurities will propagate or diffuse into the first conductivity type impurity diffusion layer. Therefore, it becomes possible to form the gate electrode layer of the load transistor as the second conductivity type.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows a sectional structure of an SRAM device as a semiconductor memory device according to an embodiment of the present invention, FIG. 2 shows a circuit structure of one memory cell of this SRAM device, and FIG. 3 shows this SRAM device. 2 is a plan view showing the configuration of the main part of FIG. The left side portion (memory cell formation region 11) in FIG. 1 corresponds to the BB ′ cross section in FIG. 3. In FIG. 2, reference numeral WL indicates a word line, reference numerals BL and / BL indicate bit lines, bit bar lines, reference numeral Vdd indicates a power supply line, and Vss indicates a ground line.

As shown in FIG. 1, this SRAM device is
It includes a memory cell formation region 11 formed using a silicon substrate 21 as a substrate and a peripheral circuit portion 12. In the memory cell formation region 11, an NMOS transistor 13 (13 ') which is an access MOS transistor and a gate
N is a diffusion region self-aligned driver transistor
A MOS transistor 14 (14 ') and a P-type TFT 15' (15) as a load transistor are formed,
The peripheral circuit section 12 has a P as a power supply line (Vdd).
Power source line contact 19 for connecting the p-type polycrystalline silicon layer 56 to the p ⁺ -type impurity region 37 via the p-type polycrystalline silicon layer 47 as the gate electrode layer of the TFT 15,
A contact electrode 16 serving as a plug region for the P ⁺ type impurity region 37 and a laminated aluminum wiring layer 17 connected to the contact electrode 16 are formed.

Silicon substrate 2 in memory cell forming region 11
A P-type well region 23 is formed in the upper layer region of 1
A silicon oxide film 22 as an element isolation region is selectively formed on the mold well region 23 and the silicon substrate 21 of the peripheral circuit portion 12. This silicon oxide film 22
An LDD structure NMOS transistor 13 is formed on the P-type well region 23 of the memory cell formation region 11 partitioned by. That is, the P-type well region 23
An N-type polycide layer 27 as a gate electrode is formed via a silicon oxide film 24 (gate insulating film) formed above, and near the surface of the P-type well region 23 adjacent to the patterned gate electrode, An N ⁻ type impurity region 29, which is a low concentration impurity diffusion region, is formed. NM
The gate electrode of the OS transistor 13 (the word line W in FIG. 2)
A silicon oxide film side wall 35 is formed on the side surface of the polycide layer 27 as L), and a high concentration impurity diffusion region (source / drain region) of the NMOS transistor 13 (in the vicinity of the surface of the P-type well region 23 in a self-aligned manner). An N ⁺ type impurity region 36) is formed.

From a partial region on the N-type polycide layer 27 serving as the gate electrode layer of the NMOS transistor 14, N ⁻
Over the type impurity region 29 and N ⁺ -type impurity region 36, N-type polycrystalline silicon layer 40 as a conductive layer, which is one of the features of the present invention is formed, both the polycide layer 27 and the N ⁺ -type impurity region 36 Are simultaneously in electrical contact with. This polycrystalline silicon layer 40 is terminated at its end on the N ⁺ type impurity region 36, and serves as a polycide layer 27 as a gate electrode layer of the NMOS transistor 13.
, And a sufficient space is secured to secure the breakdown voltage with the polycide layer 27.

A silicon oxide film 3 as an interlayer insulating film is formed on the polycide layer 27 and the polycrystalline silicon layer 40.
A polycide layer 43 serving as a ground line (Vss) is provided via the electrodes 8 and 44, and a silicon oxide film 45 serving as a flattening insulating film is formed to cover the polycide layer 43. Then, a contact opening 46 is formed through these silicon oxide films 45, 44.

A P-type polycrystalline silicon layer 47 is formed on the silicon oxide film 45 and is patterned as shown in FIG. 3 to form the gate electrodes of the TFTs 15 and 15 '. Of these, the P-type polycrystalline silicon layer 47 that becomes the gate electrode of the TFT 15 has the N-type polycrystalline silicon layer 4 at the bottom of the contact opening 46 as shown in FIG.
Connected to 0.

A silicon oxide film 52 having an opening 53 in a part thereof is formed on the polycrystalline silicon layer 47, and a polysilicon film as a channel region, a source / drain region and a power supply line (Vdd) of the TFT 15 is further formed thereon. A crystalline silicon layer 56 is formed and connected to the polycrystalline silicon layer 47 at the opening 53.

Then, a silicon oxide film 57 as a flattening insulating film is formed so as to cover the above element structure.

On the other hand, the peripheral circuit section 12 is a conventional example (see FIG. 1).
It has the same structure as 9). That is, a P ⁺ -type impurity region 37 as a power supply line contact region is formed near the surface of the silicon substrate 21 partitioned by the silicon oxide film 22 which is an element isolation region, and silicon is formed on the P ⁺ -type impurity region 37. Oxide films 38, 44 and 45 are formed. And these silicon oxide films 3
A power line contact opening 48 is formed through 8, 44 and 45, and this is a P-type polycrystalline silicon layer 47.
Covered with. Further, a silicon oxide film 52 having an opening 50 in a part thereof is formed thereon, and the opening 50 is formed.
Thus, the P-type polycrystalline silicon layer 56 formed thereon is connected to the lower P-type polycrystalline silicon layer 47. As a result, the polycrystalline silicon layer 56 is provided with the power line contact opening 48 through the polycrystalline silicon layer 47.
Is electrically connected to the P ⁺ -type impurity region 37 at the bottom of the. Therefore, in the power supply line contact region, all P-type conductive layers are in contact with each other.

A silicon oxide film 57 as a flattening insulating film is formed on the polycrystalline silicon layer 56. Then, contact holes are formed in the silicon oxide films 57, 52, 45, 44, and 38 to reach the P ⁺ -type impurity regions 37 and are filled with the titanium / titanium nitride layer 61 and the tungsten layer 62. Thus, the contact electrode 16 is formed. Then, the tungsten layer 62
Are connected to the first-layer laminated aluminum wiring 17 of a predetermined pattern formed of the titanium / titanium nitride layer 63, the aluminum layer 64, and the titanium nitride layer 65.

FIG. 4 is an enlarged cross-sectional view of the shared contact portion in the memory cell formation region 11 of FIG. As shown in this figure, the N-type polycrystalline silicon layer 40 has a gate electrode (polycide layer 27) of the driver MOS transistor 14 and a source / drain region (N ⁻ type) of the access MOS transistor 13 which are both N-type. Both the impurity region 29 and the N ⁺ type impurity region 36) are simultaneously connected. Therefore, in this portion, the N-type conductive layers are in contact with each other. On the other hand, the gate electrode (polycrystalline silicon layer 47) of the P-type TFT 15 contacts only the N-type polycrystalline silicon layer 40,
There is no direct contact with the type diffusion region (N ⁺ type impurity region 36 and N ⁻ type impurity region 29). For this reason,
Even if the gate electrode of the TFT 15 is P-type, there are disadvantages as in the conventional case (that is, P-type impurities diffuse into the N-type diffusion region to increase contact resistance).
There is no. Moreover, here, the contact is made between the P-type conductive layer and the N-type conductive layer, but since it is a forward connection, there is no problem in operation. Therefore, the polycrystalline silicon layer 47
The conductivity type can be formed as P type in both the region of the memory cell forming region 11 as the gate electrode of the TFT 15 and the power supply line contact region of the peripheral circuit portion 12. Therefore, as will be described later, the manufacturing process can be simplified.

The polycrystalline silicon layer 40 is in contact with the polycide layer 27 with a sufficient horizontal distance d _3, and is sufficiently horizontal with the impurity diffusion regions (N ⁺ type impurity regions 36 and N ⁻ type impurity regions 29). Since they are in contact with each other at the distance d ₄ , the contact area with each is sufficiently secured. Therefore, the contact resistance in this portion is suppressed low. The horizontal contact distance between the gate electrode (polycrystalline silicon layer 47) of the TFT 15 and the polycrystalline silicon layer 40 is equal to the size d of the contact opening 46. Therefore, the size d of the contact opening 46 is
The contact resistance does not increase even if the value is smaller than the conventional value. Since the size of the contact opening 46 can be reduced, the horizontal distance t ₁ between the polycide layer 43 and the contact opening 46 and the distance t ₂ between the polycide layer 27 and the contact opening 46 should be increased. You can Therefore, a sufficient breakdown voltage can be secured between the gate electrode (polycrystalline silicon layer 47) of the TFT 15 'and the Vss line (polycide layer 43) and the gate electrode (polycide layer 27) of the NMOS transistor 13 which is a word line. it can.

Next, a method of manufacturing the SRAM device having the above structure will be described.

First, as shown in FIG. 5, so-called LOC.
A silicon oxide film 22 having a thickness of about 400 nm is selectively formed on the surface of the N-type silicon substrate 21 by an OS (Local Oxidation of Silicon) method. As a result, a partition is formed between the element isolation region in which the silicon oxide film 22 is formed and the element active region surrounded by the silicon oxide film 22.

Next, as shown in FIG. 6, boron (B) is selectively ion-implanted into the silicon substrate 21 of the memory cell forming region 11 to form the P-type well region 23, and then as a gate insulating film. A silicon oxide film 24 is formed on the surface of the element active region. And CVD (Chemical Vapor D
The polycide layer 27 is formed by sequentially depositing a polycrystalline silicon layer 25 having a film thickness of about 70 to 150 nm and a silicide layer such as a tungsten silicon layer 26 by an eposition) method or a sputtering method. The layer 27 is patterned to form the gate electrodes of the NMOS transistors 13 and 14. Peripheral circuit section 12
The polycide layer 27 of is removed. Then, in the memory cell formation region 11, the N ⁻ type impurity region 29 is formed in self-alignment with the gate electrode. That is, a portion of the memory cell formation region 11 other than the source / drain formation region 28 is covered with a resist (not shown), and arsenic (A _S ) which is an N-type impurity is ion-implanted using this resist as a mask to reduce the concentration. The N ⁻ -type impurity region 29 is formed. Similarly, in the power line contact portion region 31 of the peripheral circuit portion 12, P
Boron (B), which is a type impurity, is ion-implanted to form a low concentration P ⁻ type impurity region 32.

Next, as shown in FIG. 7, after a silicon oxide film is deposited on the entire surface by the CVD method, the silicon oxide film side wall 35 is formed on the side surface of the polycide layer 27 as a gate electrode by anisotropic etching. At the same time as the formation, the silicon oxide film 24 is removed, and further, an N ⁺ -type impurity region 36 which is a high-concentration impurity diffusion region is formed in self-alignment with the silicon oxide film side wall 35. That is, the memory cell formation region 1
A portion other than the source / drain formation region of 1 is again covered with a resist (not shown), and a high concentration of arsenic is ion-implanted using this resist and the side wall 35 of the silicon oxide film as a mask to form an N ⁺ -type impurity region 36. To do. Thus, LD
D-structured NMOS transistors 13 and 14 are formed. Similarly, high-concentration boron is ion-implanted into the power supply line contact region 31 of the peripheral circuit portion 12 to generate P ^+.
A type impurity region 37 is formed. The NMOS transistor 14 has source / drain regions formed in a direction perpendicular to the plane of the drawing.

Next, as shown in FIG. 8, a silicon oxide film 38 is formed as an interlayer insulating film on the entire surface.

Next, as shown in FIG. 9, in the memory cell forming region 11, with respect to the N ⁺ type impurity region 36 as the source region of the NMOS transistor 13 and the polycide layer 27 as the gate electrode of the NMOS transistor 14. At the same time, a shared contact opening 39 for making contact is formed.

Subsequently, as shown in FIG. 10, after a polycrystalline silicon layer 40 is formed on the entire surface to a film thickness of about 50 nm,
Arsenic (or phosphorus), which is an N-type impurity, is ion-implanted on the entire surface.

Next, as shown in FIG. 11, a polycrystalline silicon layer 40 is formed by RIE (reactive ion etching).
Is selectively removed so that the connection portion with the N ⁺ type impurity region 36, the N ⁻ type impurity region 29 and the polycide layer 27 remains. As a result, the polycrystalline silicon layer 40 as the N-type conductive layer is simultaneously connected to the N-type N ⁺ -type impurity region 36 and the polycide layer 27 with a sufficient contact area. At this time, in the N ⁺ -type impurity region 36 in the portion where the shared contact opening 39 is formed, a minute region adjacent to the end of the polycrystalline silicon layer 40 is etched, so that N as shown in the figure. A groove 71 having a depth of about 50 nm is formed in the ⁺ -type impurity region 36.
However, the polycrystalline silicon layer 40 serves as the polycide layer 27 as the gate electrode of the NMOS transistor 13.
Since they do not overlap with each other, a sufficient breakdown voltage between them is secured.

Next, as shown in FIG. 12, a silicon oxide film 44 as an interlayer insulating film is formed on the entire surface with a film thickness of about 150 nm, and then the CVD method or the sputtering method is used.
A polycrystalline silicon layer 41 having a thickness of about 30 to 100 nm and a silicide layer such as a tungsten silicon layer 42 are sequentially deposited to form a polycide layer 43, and the polycide layer 43 is patterned to form a memory cell. A ground line (Vss) layer in the region 11 is formed.

Next, as shown in FIG. 13, BPSG (boron phosphorus silicate glass) is used as a flattening insulating film.
A silicon oxide film 45 is formed on the entire surface with a film thickness of about 200 to 500 nm, annealed at a temperature of 850 to 900 ° C., and flattened by reflow.

Next, as shown in FIG. 14, a contact opening 46 for making contact with the polycrystalline silicon layer 40 is formed through the silicon oxide films 45 and 44 in the memory cell formation region 11, and The P ⁺ -type impurity region 37 is penetrated through the silicon oxide films 45 and 44 of the peripheral circuit portion 12.
Power contact opening 48 for making contact with
To form. At this time, unlike the conventional shared contact, the contact opening 46 need only be connected to the polycrystalline silicon layer 40 and need not be directly connected to the N ⁺ -type impurity region 36. The size of about 4 μm is sufficient, and the size can be made smaller than the conventional one. Therefore, the polycide layer 43 that is the Vss line is
It is possible to increase the distance between the two, and it is possible to ensure a sufficient breakdown voltage between the two.

Next, as shown in FIG. 15, the TFT 15 '
The polycrystalline silicon layer 47 to be the gate electrode of
After being formed with a film thickness of about nm, boron, which is a P-type impurity, is ion-implanted into the entire surface (memory cell formation region 11 and peripheral circuit portion 12). Then, the polycrystalline silicon layer 47 is patterned as shown in FIG. As described above, in the present embodiment, the memory cell formation region 1
Since it is not necessary to separately implant impurities of different conductivity types in 1 and the peripheral circuit section 12, the manufacturing process is greatly simplified. At this point, the TFT 1 is formed in the contact opening 46.
P-type polycrystalline silicon layer 47 as 5'gate electrode
Is the gate electrode (polycide layer 27) of the NMOS transistor 14 and the source region (N ⁺ -type impurity region 36, N ⁻ -type impurity region) of the NMOS transistor 14 which are both N-type via the N-type polycrystalline silicon layer 40. The electrical connection with 29) is completed. In the power contact opening 48 of the peripheral circuit portion 12, the electrical connection between the P type polycrystalline silicon layer 47 and the P ⁺ type impurity region 37 is completed.

Next, as shown in FIG. 16, a silicon oxide film 52 is formed on the entire surface by CVD to a film thickness of about 20 to 50 nm.

Next, as shown in FIG. 17, the TFT 1 is formed on a part of the silicon oxide film 52 in the memory cell formation region 11.
A contact opening 53 for making contact with the polycrystalline silicon layer 47 serving as the 5'gate electrode layer is formed, and a portion of the silicon oxide film 52 of the peripheral circuit portion 12 is provided with polycrystalline silicon serving as a power supply line. A contact opening 54 for making contact with the layer 47 is formed.

Next, as shown in FIG. 18, a polycrystalline silicon layer 56 to be the channel region and the source / drain regions of the TFT 15 is formed by CVD or the like, and this is formed in FIG.
Pattern as shown in FIG. And TFT1
Boron is ion-implanted into the polycrystalline silicon layer 56 of the source / drain region 5'and the polycrystalline silicon layer 56 of the power supply line contact portion of the peripheral circuit portion 12 to form a P-type high concentration impurity region. As a result, the formation of the channel region of the TFT 15 'and the power supply line is completed. In addition,
By providing an offset region formed by separating the drain region from the gate and forming a low-concentration P-type region on the drain side, the drain electric field can be relaxed, and the on-current can be reduced without turning off. The current can be reduced. In this way, the P-type polycrystalline silicon layer 56 forms the gate electrode of the TFT 15 in the contact opening 53 of the memory cell formation region 11.
Connected to the polycrystalline silicon layer 47 of the mold. In this case, PN matching is formed, but as described above, there is no operational problem because it is a forward connection. The polycrystalline silicon layer 56 is used as a power supply line in the memory cell formation region 11 and is drawn out to the peripheral circuit section 12 as a P-type conductive layer, and the P-type polycrystalline silicon layer 47 is formed in the contact opening 54. Connected to. Therefore, in the peripheral circuit section 12, the P-type polycrystalline silicon layer 56 is formed.
Are connected to the P ⁺ -type impurity region 37 through the P-type polycrystalline silicon layer 47, and all have the same conductivity type.

Next, as shown in FIG. 1, a reflow film 57 of BPSG or the like is formed on the entire surface as an interlayer insulating film, which is heat-treated and flattened by reflow, and then selectively formed on the peripheral circuit portion 12. The contact hole 58 is formed. And
After filling the contact hole 58 with a plug composed of a titanium / titanium nitride (Ti / TiN) layer 61 and the like as a barrier metal layer and an adhesion layer and a tungsten layer 62, a titanium / titanium nitride layer 63 as a barrier metal layer and the like. And C
After forming an aluminum layer 64 containing u and further forming a titanium nitride layer 65 as an antireflection layer or the like, these are patterned to form a first layer of laminated aluminum wiring. In this way, the SRAM device shown in FIG. 1 is completed. After that, although not shown, an interlayer insulating film and a second-layer laminated aluminum wiring are formed, and a silicon nitride (SiN) layer as an overcoat film is further formed by a plasma CVD method to complete the whole manufacturing process. To finish.

[0040]

As described above, according to the semiconductor memory device and the method of manufacturing the same of the present invention, the driver MO is provided.
A first conductivity type conductive layer is newly provided to be in electrical contact with both the first conductivity type gate electrode layer of the S transistor and the first conductivity type impurity diffusion layer as the source / drain regions of the access MOS transistor at the same time. At the same time, since it is connected to the gate electrode layer of the load transistor at the bottom of the contact opening, the gate electrode layer of the load transistor is not directly connected to the first conductivity type impurity diffusion layer, Even if the gate electrode layer of the load transistor is formed as the second conductivity type,
There is no possibility that the second conductivity type impurity of the gate electrode layer will propagate or diffuse into the first conductivity type impurity diffusion layer. Therefore, the gate electrode layer of the load transistor can be formed as the second conductivity type. Therefore, when the gate electrode layer of the load transistor is drawn out to the peripheral circuit and is used as the power supply line of the second conductivity type, the conductivity type can be shared between the memory cell region and the peripheral circuit region. For this reason, it is not necessary to perform ion implantation of different conductivity types depending on regions during manufacturing, an ion implantation mask is not required, a mask removing step is not required, and the ion implantation step is only required once. Therefore, there is an effect that the manufacturing process can be greatly simplified as compared with the conventional case.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts showing an SRAM device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a circuit configuration of a memory cell of this SRAM device.

FIG. 3 is a plan view showing a main part of a memory cell of this SRAM device.

FIG. 4 is an enlarged cross-sectional view showing a main part of the SRAM device of FIG.

5 is a cross-sectional view of a main part for explaining the first step of the method for manufacturing the SRAM device in FIG.

FIG. 6 is a cross-sectional view for explaining a step following the step of FIG.

FIG. 7 is a cross-sectional view illustrating a step following the step of FIG.

FIG. 8 is a cross-sectional view for explaining a process following the process in FIG.

FIG. 9 is a cross-sectional view for explaining a step following the step of FIG.

FIG. 10 is a cross-sectional view illustrating a step following the step of FIG.

FIG. 11 is a cross-sectional view for explaining a step following FIG.

FIG. 12 is a cross-sectional view for explaining a step following FIG.

FIG. 13 is a cross-sectional view for explaining a step following FIG.

FIG. 14 is a cross-sectional view for explaining a step following the step of FIG.

FIG. 15 is a cross-sectional view for explaining a process following the process in FIG.

16 is a cross-sectional view for explaining a step following FIG.

FIG. 17 is a cross-sectional view illustrating a step following the step of FIG.

FIG. 18 is a cross-sectional view illustrating a step following the step of FIG.

FIG. 19 is a cross-sectional view showing a main part of a conventional SRAM device.

[Explanation of symbols]

11 memory cell formation region 12 peripheral circuit section 13, 13 'NMOS transistor (access MO
S transistor) 14,14 'NMOS transistor (MO for driver
S transistor) 15,15 'TFT (load element: thin film transistor for load) 17 laminated aluminum wiring layer 21 silicon substrate 22 silicon oxide film (element isolation film) 23 P-type well region 24 silicon oxide film (gate insulating film) 27 polycide Layer (gate electrode layer) 29 N ⁻ type impurity region 35 Silicon oxide film side wall 36 N ⁺ type impurity region (source / drain region) 37 P ⁺ type impurity region 38 Silicon oxide film (first interlayer insulating film) 39 Shared Opening for contact (first opening) 40 Polycrystalline silicon layer (conductive layer) 43 Polycide layer (Vss line) 44 Silicon oxide film (second interlayer insulating film) 45, 57 Silicon oxide film 46 Opening for contact (Second opening) 47 Polycrystalline silicon layer (TFT gate electrode layer) 48 Power supply controller Tact opening 50,53 Opening 52 Silicon oxide film (TFT gate oxide film) 56 Polycrystalline silicon layer

Claims (2)

[Claims] 1. A semiconductor comprising a memory cell including a pair of first conductivity type driver MOS transistors, a pair of first conductivity type access MOS transistors, and a pair of second conductivity type load thin film transistors. A memory device, which extends from at least a partial region on a first conductivity type gate electrode layer of a driver MOS transistor to a first conductivity type impurity diffusion layer as a source / drain region of an access MOS transistor. At the same time, the end portion of the first conductivity type impurity diffusion layer is terminated, and the first conductivity type impurity diffusion layer is in electrical contact with both the first conductivity type gate electrode layer and the first conductivity type impurity diffusion layer at the same time. A conductive layer, an interlayer insulating film formed so as to cover the first conductive type conductive layer and the transistors, and an interlayer insulating film on the first conductive type conductive layer. A contact opening formed so as to reach the first conductive type conductive layer through, and a gate electrode layer of the load transistor is formed as a second conductive type so as to cover the contact opening. ,
A semiconductor memory device electrically connected to the first conductive type conductive layer. 2. A semiconductor provided with a memory cell including a pair of first conductivity type driver MOS transistors, a pair of first conductivity type access MOS transistors, and a pair of second conductivity type load thin film transistors. A method of manufacturing a memory device, which comprises a step of forming a driver MOS transistor and an access MOS transistor on a semiconductor substrate, and a driver MOS transistor and an access MOS.
A step of forming a first interlayer insulating film on the transistor, and a step of forming a first conductive type gate electrode layer of the driver MOS transistor and a source / driver region of the access MOS transistor on the first interlayer insulating film. Forming a first opening for forming a common contact for the first conductivity type impurity diffusion layer; forming a first conductivity type conductive layer so as to cover the first opening; Etching the first conductive type conductive layer so that it terminates on the first conductive type impurity diffusion layer; and forming a second interlayer insulating film on the first conductive type conductive layer, A step of forming a second opening reaching the first conductive type conductive layer in the second interlayer insulating film; and a second conductive type gate electrode layer of the load transistor so as to cover the second opening. Shape The method of manufacturing a semiconductor memory device which comprises a step of.