JPH10321806A - Semiconductor device protection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a protection circuit capable of providing sufficient withstand voltage characteristic and ensuring the high-speed operation of a semiconductor device, without complicating the element structure and with stable element characteristics maintained in the semiconductor device having a silicide layer formed by a selfaligned silicide method. SOLUTION: This protection circuit 1 is provided between an electrode pad 2 and an internal circuit 3 and is provided with an MOS transistor 11. The MOS transistor 11 has a drain (first diffused layer electrode) 11a connected to the electrode pad 2 and the internal circuit 3, and a source (second diffused layer electrode) 11b connected to a reference potential VSS. In this case, a resistive element 14, consisting of a silicide layer 14a connected to the electrode pad 2 and a polycrystalline silicon 14b connected to an internal circuit 33, is provided between the electrode pad 2 and the drain 11a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a protection circuit for a semiconductor device, and more particularly, to a protection circuit for protecting an internal circuit having a silicide layer obtained by a self-aligned silicide method on a diffusion layer surface.

[0002]

2. Description of the Related Art FIG. 13 is an equivalent circuit diagram for explaining a protection circuit in a semiconductor device. The protection circuit 9 shown in this figure is provided between the electrode pad 2 and the internal circuit 3 and includes an insulated gate field effect transistor 11, a resistor 12, a diode 13, and a resistor 90. Hereinafter, an insulated gate field effect transistor will be referred to as a MOS (Metal Ox
ide Semiconductor) transistor. M above
The OS transistor (insulated gate type field effect transistor) 11 is an N-channel type. The drain 11a is connected to the internal circuit 3 and the electrode pad 2, and the source 11b is connected to the reference potential Vss of the semiconductor device. Further, the resistance element 12 is arranged between the gate of the MOS transistor 11 and the reference potential Vss. Further, the diode 13 has an N-type region connected to the internal circuit 3 and the electrode pad 2, and a P-type region connected to the reference potential Vss. In particular, the resistor 90 is made of a diffusion layer or polycrystalline silicon.
It is arranged between the OS transistor 11 and the drain 11a.

In the protection circuit 9 having the above configuration, the electrode pad 2
Is applied with a negative overvoltage, the diode 13 conducts and the electric charge is discharged to the reference potential Vss. The resistance element 12
, When a positive overvoltage is applied to the electrode pad 2, the gate 1 of the MOS transistor 11
1c, the MOS transistor 11 is temporarily turned on by the coupling between the source 11a and the drain 11b,
The conduction between the source 11a and the drain 11b of the transistor 11 causes the electric charge to be discharged to the reference potential Vss. On the other hand, when a normal operating voltage is applied to the electrode pad 2,
The gate 11c of the transistor 11 is held at the level of the reference potential Vss, and the off state of the MOS transistor 11 is held. Therefore, when an operating voltage is applied from the electrode pad 2 to the internal circuit 3, generation of a leak current is prevented. Further, by providing the resistor 90, M
The OS transistor 11 itself is prevented from being destroyed by application of an overvoltage.

[0004]

However, in the semiconductor device having the protection circuit having the above configuration, the signal waveform applied to the electrode pad when the semiconductor device is operated normally is
Due to the influence of the capacitance of the impedance of the drain resistance present in the drain of the resistor and the MOS transistor, the waveform becomes dull due to the RC time constant and is output from the protection circuit to the internal circuit side. For this reason, in the semiconductor device having the protection circuit with the above configuration, the presence of the resistor adversely affects the high-speed operation of the semiconductor device.

Therefore, in the semiconductor input protection device described in Japanese Patent No. 2557980, the MOS transistor has a structure in which the drain is extended and a diffusion resistor formed integrally with the drain is provided in the protection circuit as the resistor. By doing so, high-speed propagation of signals is enabled.

However, in a highly integrated semiconductor device, a low-resistance silicide layer is provided on the surface layer of the source / drain in order to reduce the sheet resistance of the source / drain of the MOS transistor. This silicide layer is formed in a self-aligned manner on the surface layer of the diffusion layer by a self-aligned silicide method. For this reason, when the resistor is a diffusion resistor integrated with the drain of the MOS transistor, a silicide layer is also formed on the surface layer of the resistor to prevent electrostatic breakdown of the MOS transistor due to application of overvoltage. Can not be done.

In order to improve the electrostatic resistance of a semiconductor device formed by applying the self-aligned silicide method, International Electron Devices M.
eeting (1996) (US) p. 889-892 proposes a configuration in which the element structure is comb-shaped. Furthermore, In
ternational Electron Devices Meeting (1996)
(US) p. 895-896 proposes to increase the junction depth of the source and the drain with respect to the thickness of the silicide layer. However, in these semiconductor devices, there are problems that the element structure becomes complicated and high integration of the semiconductor device is hindered, and if the controllability of the thickness of the silicide layer varies, stable element characteristics cannot be obtained.

As described above, a semiconductor device in which a silicide layer is formed on the surface of a diffusion layer constituting an internal circuit by a self-aligned silicide method has stable element characteristics without complicating the element structure. In this state, a protection circuit having sufficient withstand voltage characteristics and capable of ensuring high-speed operation of the semiconductor device could not be obtained.

[0009]

A protection circuit for a semiconductor device for solving the above-mentioned problems is a protection circuit provided between an electrode pad and an internal circuit, wherein a first diffusion layer electrode is connected to the electrode pad. A MOS transistor connected to the internal circuit has a second diffusion layer electrode connected to a reference potential. The protection circuit according to a first aspect of the present invention includes a silicide layer connected to the electrode pad and polycrystalline silicon connected to the internal circuit between the electrode pad and the first diffusion layer electrode. It is characterized in that a resistance element is provided.

In the protection circuit according to the first invention, the overvoltage applied to the electrode pad is applied from the resistance element to the MOS transistor. The resistance element includes a silicide layer on the electrode pad side and polycrystalline silicon on the MOS transistor side. For this reason, an overvoltage is applied to the MOS transistor via the polycrystalline silicon having a high resistance to prevent the electrostatic breakdown of the MOS transistor, and an overvoltage is applied to the resistance element from a silicide layer having a low resistance. As a result, the capacity of the resistance impedance existing in the resistance element is reduced, and the influence of the RC time constant on the internal circuit is suppressed to a low level.

The protection circuit according to a second aspect of the present invention is the protection circuit, wherein an input terminal is connected to the electrode pad and an output terminal is connected to the internal circuit between the electrode pad and the first diffusion layer electrode. It is characterized in that a resistive element composed of a withstand voltage CMOS transistor is provided, and a silicide layer is provided at a connection portion on the input end side of the resistive element.

In the protection circuit according to the second aspect of the present invention, the overvoltage applied to the electrode pad is applied to the MOS transistor from a resistance element composed of a high-withstand-voltage CMOS transistor. Further, a silicide layer is provided at a connection portion forming an input terminal of the resistance element. For this reason,
An overvoltage is applied to the MOS transistor via the high-withstand-voltage CMOS transistor to prevent electrostatic breakdown of the MOS transistor, and an overvoltage is applied to the CMOS transistor from a silicide layer having a low resistance value to cause the MOS transistor to be present in the resistance element. Therefore, the effect of the RC time constant on the internal circuit is reduced.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a protection circuit for a semiconductor device according to the present invention will be described below with reference to the drawings.
It should be noted that each embodiment described below is shown only as an example. For this reason, the negative power supply voltage (Vss) is used as the reference potential, but a positive power supply voltage VDD may be used. In this case, the conductivity types of the elements constituting each protection circuit are reversed. And In addition, the same components as those of the conventional protection circuit described with reference to FIG. 13 are denoted by the same reference numerals, and redundant description will be omitted.

(First Embodiment) FIG. 1 is a sectional view of a main part of a protection circuit according to a first embodiment, FIG. 2 is an equivalent circuit diagram of the protection circuit according to the first embodiment, and FIG. FIG. 3 is a layout diagram of a protection circuit according to an embodiment. FIG. 1 is a sectional view taken along the line AA ′ of FIG. As shown in these figures, the protection circuit 1
Is provided between the electrode pad 2 and the internal circuit 3, and the MO
It comprises an S transistor (including MIS type) 11, a first resistance element 12, a diode 13, and a second resistance element (resistance element in the claims).

The MOS transistor 11 is an N-channel type, and a drain (first diffusion layer electrode in the claims) 11a is connected to the internal circuit 3 and the electrode pad 2.
A source (a second diffusion layer electrode in the claims) 11b is connected to a reference potential (here, Vss) of the semiconductor device. The first resistance element 12 is arranged between the gate 11c of the MOS transistor 11 and the reference potential Vss. The diode 13 has an N-type region connected to the internal circuit 3 and the electrode pad 2, and a P-type region connected to the reference potential Vss. Here, for example, the P-type region is a semiconductor substrate, and the N-type region is a MOS substrate.
The drain 11a of the transistor 11 is shared. Further, the second resistance element 14 is connected to the electrode pad 2 and the MO.
It is arranged between the S transistor 11 and the drain 11a.

Then, in the protection circuit 1 of the first embodiment,
The second resistor element 14 is characterized by comprising a silicide layer 14a and polycrystalline silicon 14b joined to the silicide layer 14a (see FIG. 1). The silicide layer 14a is provided at a connection portion between the second resistance element 14 and the wiring 15 on the electrode pad 2 side, and the polycrystalline silicon 14b is provided on the second resistance element 1 side on the internal circuit 3 side.
It is provided at the connection between the wiring 4 and the wiring 15.

Further, the silicide layer 14a is obtained by silicidizing a part of the surface layer of the polycrystalline silicon 14b.
It is formed in the same step as the gate electrode 11c of the OS transistor 11. In addition, the silicide layer 14a
Source 11b and drain 11 of MOS transistor 11
a and the surface layer of the gate electrode 11c are silicided by a self-aligned silicide method, and are obtained by silicidizing the surface layer of the polycrystalline silicon 14b.

In the protection circuit 1 having the above configuration, the electrode pad 2
The positive or negative overvoltage applied to the second resistance element 14
Through the MOS transistor 11 or the diode 13
From above to the reference potential Vss. here,
The second resistance element 14 includes a silicide layer 14a on the electrode pad 2 side and a polycrystalline silicon 14b on the MOS transistor 11 side. Therefore, the MOS transistor 11 is connected via the polycrystalline silicon 14b having a high resistance value.
Is applied to the MOS transistor 11
Is prevented from being electrostatically damaged. Further, by applying an overvoltage to the second resistance element 14 from the silicide layer 14a having a low resistance value, the capacity of the resistance impedance existing in the second resistance element 14 is reduced. Therefore, the second
The effect of the RC time constant on the internal circuit 3 to which the operating voltage from the electrode pad 2 is applied via the resistive element 14 is suppressed.

As described above, in the protection circuit 1, in the semiconductor device in which the silicide layer is formed on the surface of the diffusion layer constituting the internal circuit 3 or the surface of the diffusion layer of the MOS transistor 11 by the self-aligned silicide method, Without complicating the structure and maintaining stable element characteristics, electrostatic breakdown of the protection circuit itself due to application of overvoltage can be prevented and high-speed operation of the semiconductor device can be ensured.
In addition, in the protection circuit 1, since the second resistance element does not use a diffusion layer, when the second resistance element is formed of a diffusion layer, there is a concern about a short circuit occurring at a connection portion with the diffusion layer. do not have to.

FIG. 4 shows the first type described with reference to FIG.
5 shows a modification of the protection circuit of the embodiment. The protection circuit 1 'shown in FIG. 4 and the protection circuit (1) described with reference to FIG.
The difference from the above is the configuration of the second resistance element. That is, the second resistance element 14 ′ is composed of a polycrystalline layer formed on the semiconductor substrate 10 in a state where the silicide layer 14 a ′ is formed on a part of the surface layer of the semiconductor substrate 10 and overlapped on a part of the silicide layer 14 a ′. And silicon 14b. This silicide layer 14a 'is obtained by silicidizing the surface layer of the semiconductor substrate 10 in a step of silicifying the surface layer of the source 11b, the drain 11a and the gate electrode 11c of the MOS transistor 11 by a self-aligned silicide method. Also, the polycrystalline silicon 14b is used to form a second circuit constituting an internal circuit (not shown).
Of the polycrystalline silicon layer.

Even in the protection circuit 1 'having such a structure, the second resistance element 14' is composed of the silicide layer 14a 'and the polycrystalline silicon 14b, and the silicide layer 14a'
Is connected to the electrode pad (2) side and the polysilicon 14b
Is connected to the internal circuit (3) side, the same effect as that of the protection circuit (1) described with reference to FIG. 1 can be obtained.

FIGS. 5A to 5C are cross-sectional process views showing an example of the process of forming the protection circuit described with reference to FIG. The procedure for forming the protection circuit during the process of forming the internal circuit will be described below with reference to these drawings. First, as shown in FIG. 5A, an element isolation region 502 is formed on the front side of the semiconductor substrate 10. Thereafter, the gate electrode 11c of the MOS transistor forming the protection circuit and the gate electrode of the MOS transistor forming the internal circuit (not shown) not shown here are formed of polycrystalline silicon. Here, a pattern of polycrystalline silicon 14b constituting the second resistance element is simultaneously formed on the element isolation region 502. It is assumed that impurities are introduced into the gate electrode 11c and the polycrystalline silicon 14b. These impurities may be introduced by ion implantation before patterning the polycrystalline silicon film constituting them, or may be introduced in advance into the polycrystalline silicon film at the time of forming the polycrystalline silicon film.

Next, after performing ion implantation for forming the LDD diffusion layer 503, an oxide film pattern 504 is formed on a portion on the polycrystalline silicon 14b. here,
The oxide film pattern 504 is formed by patterning a silicon oxide film formed on the entire surface of the semiconductor substrate 10.
Get.

An example of the conditions for forming the silicon oxide film is shown below. Deposition gas and flow rate: TEOS (tetraethoxys
ilane) gas = 300 sccm, gas pressure in film formation atmosphere:
93 Pa, film formation temperature: 700 ° C., film thickness: 150 n
m. An example of the etching conditions at the time of the above patterning is shown below. Etching gas and flow rate: C ₄ F ₈ (cyclobutane octafluoride) = 50 sccm, RF power: 120
0 W, gas pressure in etching atmosphere: 2 Pa.

Next, a side wall 505 made of silicon oxide is formed on the side wall of the gate electrode 11c. Here, the silicon oxide film formed on the entire surface of the semiconductor substrate 10 is etched back to form the side wall 5.
05 is obtained. Therefore, not only the side wall of the gate electrode 11c but also the oxide film pattern 504 and the polysilicon 14b
Side walls 505 are also formed on the side walls of. The conditions for forming the silicon oxide film and the etching conditions for the etch back in this step are, for example, the above-described oxide film pattern 5.
04.

Thereafter, ion implantation for forming the source 11b and the drain 11a of the MOS transistor (including the MOS transistor forming the internal circuit) is performed.
At this time, first, a 10-nm-thick silicon oxide film (not shown) is formed on the entire surface of the semiconductor substrate 10. Here, a silicon oxide film is obtained by performing heat treatment at 800 ° C. for 10 minutes in an O ₂ (oxygen gas) atmosphere supplied at a flow rate of 4 slm.

Next, as a P-type impurity, for example, BF
₂ (boron difluoride) ions are implanted at about 3 × 10 ¹⁵ ions / cm ² at an implantation energy of 40 keV. At this time, B
F (fluorine) of F ₂ is taken into the silicon oxide film, and only B (boron) is introduced into the semiconductor substrate 10. Next, after the silicon oxide film obtained by the above heat treatment is removed by etching using a hydrofluoric acid solution,
As a type impurity, for example, As (arsenic) ion is 50 ke
About 3 × 10 ¹⁵ / cm ² are implanted at an implantation energy of V.

Thereafter, the semiconductor substrate 1 is
0, heat treatment for activating impurities introduced into the gate electrode 11c and the polycrystalline silicon 14b is performed. Here, heat treatment is performed at 1000 ° C. for 10 seconds in a nitrogen atmosphere,
The source 11b and the drain 11a having the LDD diffusion layer 503 are formed, and the conductivity of the polysilicon 14b and the gate electrode 11c is obtained.

Next, as shown in FIG. 5B, a silicide layer 14a is formed on the exposed surface layer of the source 11b, the drain 11a, the gate electrode 11c and the polycrystalline silicon 14b by a self-aligned silicide method. Here, first, the semiconductor substrate 10 and the gate electrode 11 are treated with a hydrofluoric acid solution.
After removing the native oxide film on the surface of the polysilicon 14b and the polycrystalline silicon 14b, a metal film is formed on the entire surface of the semiconductor substrate 10.
As the metal film, Ti (titanium), Co (cobalt), Ni (nickel), Zr (zirconium), Ru
(Ruthenium), Pd (palladium), Hf (hafnium), W (tungsten), Pt (platinum), Co /
Ti, Ti / Co, TiN / Co, or the like is used.

An example of the conditions for forming the metal film made of Co will be described below. Sputtering gas and flow rate: Ar
(Argon) = 100 sccm, gas pressure in the film formation atmosphere: 0.47 Pa, film formation temperature: 150 ° C., film thickness: 3
0 nm, power: 1 kW.

Thereafter, a first heat treatment is performed to selectively grow a silicide layer 14a made of CoSi _{2 on} the single crystal and polycrystal silicon surfaces. As an example of the heat treatment, nitrogen (N) supplied at a flow rate of 5000 cm ³ / min.
₂ ) RTA (Rapi) at 550 ° C for 30 seconds in an atmosphere
d Thermal Annealing). Next, an unreacted metal film (Co) is selectively removed by etching using sulfuric acid and hydrogen peroxide as an etching solution.

Thereafter, a second heat treatment is performed to transfer the silicide layer 14a to a more stable phase. An example of the heat treatment at this time is as follows: an N ₂ atmosphere supplied at a flow rate of 5000 cm ³ / min.
Perform TA.

Next, as shown in FIG. 5C, an interlayer insulating film 506 having a laminated structure of a silicon oxide film or a silicon nitride film and a BPSG (boron-phosphorus silicate glass) film is formed on the entire surface of the semiconductor substrate 10. Is formed. less than,
An example of the conditions for forming the interlayer insulating film will be described. The conditions for forming the silicon oxide film are as follows: film forming gas and flow rate: SiH
₄ (silane) / O ₂ = 0.03 slm / 0.54 sl
m, gas pressure in the film formation atmosphere: 10.2 Pa, film formation temperature:
400 ° C., film thickness: 100 nm. The conditions for forming the silicon nitride film are as follows: film forming gas and flow rate: SiH ₂ Cl
₂ (dichlorosilane) / NH ₃ (ammonia) / N ₂ =
0.05 slm / 0.2 slm / 0.2 slm, gas pressure in the film formation atmosphere: 70 Pa, film formation temperature: 760 ° C., film thickness: 50 nm.

The conditions for forming the BPSG film are as follows: film forming gas and flow rate: TEOS = 50 sccm, gas pressure in the film forming atmosphere: 40 Pa, film forming temperature: 720 ° C., film forming film thickness: 50
0 nm. After the BPSG film is formed, CMP (Chemical Mechanical Polishing) for planarization may be performed.

Next, a connection hole 507 is formed in the interlayer insulating film 506 and the oxide film pattern 504 by etching using a resist pattern (not shown) as a mask.
To form An example of the etching condition of the interlayer insulating film at this time is shown. Etching gas and flow rate: C ₄ F ₈ / 50s
ccm, RF power: 1200 W, gas pressure in the etching atmosphere: 2 Pa.

After the above steps, contact ion implantation is performed to cope with the mask displacement of the connection hole 507. At this time, as an example of the introduction condition of the P-type impurity, BF ₂ ions are implanted at a dose of 3 × 10 ¹⁵ / c at an energy of 50 keV.
m ² about to introduce. As an example of the conditions for introducing the N-type impurity, As ions are implanted at about 3 × 10 ¹⁵ ions / cm ² at an implantation energy of 50 keV.

Thereafter, activation heat treatment is performed at 850 ° C. for 30 seconds in an N ₂ atmosphere.

Next, as shown in FIG.
07, a plug 508 is formed. At this time, first, the natural oxide film on the bottom surface of the connection hole 507 is removed by immersion in an aqueous solution of sulfuric acid and dry etching with Ar ions.
Subsequent to the dry etching, a film of an adhesion layer (not shown) is formed. The adhesion layer is formed by stacking a TiN (titanium nitride) film on a Ti (titanium) film, for example. The conditions for forming the Ti film are as follows: sputtering gas and flow rate: Ar = 100 scc
m, gas pressure in the film formation atmosphere: 0.47 Pa, film formation temperature:
150 ° C., film thickness: 10 nm, power: 8 kW. Ti
The conditions for forming the N film are as follows: sputtering gas and flow rate: Ar / N ₂ = 40 sccm / 20 sccm, gas pressure in the film formation atmosphere: 0.47 Pa, film thickness: 70 nm,
Power: 5 kW.

Next, a blanket W film is formed on the adhesion layer. An example of the film forming conditions is shown below. Deposition gas and flow rate: Ar / N ₂ / H ₂ (hydrogen gas) / WF ₆ (tungsten hexafluoride) = 2200 sccm / 300 sccm
/ 500 sccm / 75 sccm, gas pressure in the film formation atmosphere: 10640 Pa, film formation temperature: 450 ° C., film thickness:
400 nm.

Next, the W film is etched back so that the W film remains only in the connection hole 507, and a plug 508 made of the W film is formed. An example of the etching conditions for etching back the W film is shown below. Etching gas and flow rate: SF ₆ (sulfur hexafluoride) = 50 sccm, RF power: 150 W, gas pressure in etching atmosphere: 1.33
Pa.

Next, the interlayer insulating film 506 and the plug 508
The wiring 15 is formed thereon. Here, as an example, a wiring 15 is obtained by forming a wiring material film formed by stacking an Al (aluminum) film on a Ti film and then patterning the wiring material film. The following is an example of the film forming conditions for the wiring material film and the etching conditions for patterning the wiring material film.

The conditions for forming the Ti film are as follows: sputtering gas and flow rate: Ar = 100 sccm, gas pressure in the film formation atmosphere: 0.47 Pa, film formation temperature: 150 ° C., film thickness: 30 nm, power: 4 kW. The conditions for forming the Al film are as follows: sputtering gas and flow rate: Ar = 50 scc
m, gas pressure in the film formation atmosphere: 0.47 Pa, film formation temperature:
150 ° C., film thickness: 0.5 μm, power: 22.5 k
W. As etching conditions, etching gas and flow rate: BCl ₃ (boron trichloride) / Cl ₂ (chlorine gas) =
60 sccm / 90 sccm, microwave power: 10
00 W, RF power: 50 W, gas pressure in the etching atmosphere: 0.016 Pa.

As described above, the protection circuit 1 described with reference to FIGS. 1 to 3 is formed without increasing the number of steps in the process of forming the internal circuit and without complicating the element structure.

The heat treatment sequence of the RTA in the above formation process is 100 ° C./sec until the temperature rises to 500 ° C.
c. The temperature is increased by about 10 ° C./sec. Perform processing. In addition, 100
-10 ° C / sec. From 0 ° C to 500 ° C. At -100 ° C / sec. Implement a rapid cooling down to a degree. This increases the throughput and prevents the occurrence of crystal defects due to thermal stress.

(Second Embodiment) FIG. 6 is a sectional view of a main part of a protection circuit according to a second embodiment, FIG. 7 is an equivalent circuit diagram of the protection circuit according to the second embodiment, and FIG. FIG. 3 is a layout diagram of a protection circuit according to an embodiment. FIG. 6 is a sectional view taken along the line AA ′ of FIG. Hereinafter, the protection circuit of the second embodiment will be described with reference to these drawings. Note that the same components as those of the protection circuit of the first embodiment are denoted by the same reference numerals, and redundant description will be omitted.

The protection circuit 6 shown in FIGS.
The second resistance element of the protection circuit described in the embodiment is replaced with a second resistance element 61 formed of a high-withstand-voltage CMOS transistor (hereinafter, referred to as CMOS). The other components, that is, the MOS transistor 11, the first resistance element 12, and the diode 13 are the same as those in the first embodiment.

The second resistive element 61 having the above CMOS structure
Is provided with the source 61a and the gate electrode 61b connected to the electrode pad 2 as input terminals and the drain 61c connected to the internal circuit 3 as output terminals.
In particular, a silicide layer 61d is provided on the surface layer of the gate electrode 61b and the source 61a (see FIG. 6), and these silicide layers 61d are connected to the wiring 15 on the electrode pad 2 side. The second resistance element 61
, L in the channel length direction of the source 61a
High withstand voltage characteristics are obtained by increasing the length of the DD diffusion layer.

In the protection circuit 6 having the above configuration, the electrode pad 2
The positive or negative overvoltage applied to the second resistance element 61
To the MOS transistor 11 and the diode 13, and the overvoltage is discharged from the MOS transistor 11 or the diode 13 to the reference potential Vss. Here, the second resistance element 61 is formed of a high withstand voltage CMOS. Therefore, the high withstand voltage second resistance element 6
1, the overvoltage is applied to the MOS transistor 11 to prevent the MOS transistor 11 from being electrostatically damaged. Further, by applying an overvoltage to the second resistance element from the silicide layer 61d having a low resistance value, the capacity of the resistance impedance existing in the second resistance element is reduced. Therefore, the effect of the RC time constant on the internal circuit 3 to which the operating voltage from the electrode pad 2 is applied via the second resistance element is suppressed low.

As described above, in the protection circuit 6 provided with the second resistive element 61, the silicide layer is formed on the surface of the diffusion layer constituting the internal circuit and the surface of the diffusion layer of the MOS transistor 11 by the self-aligned silicide method. In such a semiconductor device, it is possible to prevent the protection circuit itself from being electrostatically damaged by applying an overvoltage and to ensure a high-speed operation of the semiconductor device without complicating the element structure and having stable element characteristics.

FIGS. 9 (1) to 9 (5) are cross-sectional process diagrams showing an example of the process of forming the protection circuit described with reference to FIGS. 6, 7 and 8. FIG. The formation of the protection circuit will be described based on FIG. FIG. 9 is a sectional view taken along line AA ′ of FIG.
It has a cross section. First, as shown in FIG. 9A, an element isolation region 502 is formed on the front side of the semiconductor substrate 10. After that, the gate electrode of the MOS transistor and the gate electrode 61b of the CMOS constituting the protection circuit and the gate electrode of the MOS transistor constituting the internal circuit (not shown) not shown here are formed of polycrystalline silicon. It is assumed that an impurity has been introduced into the gate electrode 61b. These impurities may be introduced by ion implantation before patterning the polycrystalline silicon film constituting them, or may be introduced in advance into the polycrystalline silicon film at the time of forming the polycrystalline silicon film.

Next, after ion implantation for forming the LDD diffusion layer 503 is performed, a sidewall 505 made of silicon oxide is formed on the side wall of the gate electrode 61b.

Next, as shown in FIG. 9B, an oxide film pattern 901 having a thickness of 200 nm is formed on a portion of the gate electrode 61b and on the semiconductor substrate 10. The oxide film pattern 901 is formed in the same manner as the oxide film pattern (504) described with reference to FIG. 5A in the first embodiment.

Thereafter, in the step shown in FIG. 9 (3), in the same manner as described in the first embodiment with reference to FIG. Source 61 (including transistor)
a and the drain 61c.

Next, in the step shown in FIG. 9D, the source 61a, the drain 61c and the gate electrode 61b are formed by a self-aligned silicide method similar to that described in the first embodiment with reference to FIG. A silicide layer 61d is formed on the exposed surface layer.

Thereafter, in the step shown in FIG. 9 (5), the interlayer insulating film 506 and the connection are formed in the same manner as described in the first embodiment with reference to FIGS. 5 (3) and 5 (4). Hole 50
7, the plug 508 and the wiring 15 are formed.

As described above, the protection circuit 6 described with reference to FIGS. 6 to 8 is formed without increasing the number of steps in the process of forming the internal circuit and without complicating the element structure.

FIG. 10 is a sectional view of a principal part showing a modification of the protection circuit of the second embodiment described with reference to FIGS. 6 to 8, and FIG. 11 is a layout diagram of this protection circuit.
FIG. 10 is a sectional view taken along line AA ′ of FIG. The difference between the protection circuit 6 'shown in these figures and the protection circuit (6) described with reference to FIGS. 6 to 8 lies in the layout of the CMOS constituting the second resistance element. That is, the CMOS constituting the second resistance element 61 'is LOCOS
A high withstand voltage characteristic is obtained by providing a structure in which the gate electrode 61b and the LDD diffusion layer 503 are provided so as to overlap the oxide film layer 502a formed in the same step as the element isolation region 502 made of (Local Oxidation of Silicon).

FIGS. 12 (1) to 12 (4) correspond to FIG.
FIG. 12 is a sectional process view illustrating an example of a process of forming the protection circuit described with reference to FIG. In addition, FIG.
A 'section.

First, as shown in FIG. 12A, the element isolation region 502 and the oxide film layer 5 are formed on the front side of the semiconductor substrate 10.
02a is formed. Then, the CMO that constitutes the protection circuit
The same impurity as that of the source / drain of S is introduced into the CMOS formation region under the oxide film layer 502a by ion implantation.

Next, the gate electrode of the MOS transistor and the gate electrode 61b of the CMOS constituting the protection circuit are described.
Alternatively, a gate electrode of a MOS transistor constituting an internal circuit (not shown) not shown is formed of polycrystalline silicon. At this time, the CMOS gate electrode 6 is used.
1b is the semiconductor substrate 1 from above a part of the oxide film layer 502a.
0 is provided. Also, the gate electrode 61b
Has impurities introduced therein. These impurities may be introduced by ion implantation before patterning the polycrystalline silicon film constituting them, or may be introduced in advance into the polycrystalline silicon film at the time of forming the polycrystalline silicon film. After that, ion implantation for forming the LDD diffusion layer 503 is performed.

Next, in the step shown in FIG. 12B, the side wall 505 made of silicon oxide is formed on the side wall of the gate electrode 61b in the same manner as described with reference to FIG. 9A in the first embodiment. And a source 61a and a drain 61c of a CMOS (including a MOS transistor of a protection circuit and a MOS transistor of an internal circuit).
To form

Next, in the step shown in FIG. 12C, the source 61a, the drain 61c and the gate electrode are formed by the self-aligned silicide method similar to that described in the first embodiment with reference to FIG. A silicide layer 61d is formed on the exposed surface layer 61b.

After the above, in the step shown in FIG.
As described with reference to FIGS. 5 (3) and 5 (4) in the first embodiment, the interlayer insulating film 506 and the connection hole 50 are formed.
7, the plug 508 and the wiring 15 are formed.

As described above, the protection circuit 6 'for protecting the internal circuit is formed without increasing the number of steps in the process of forming the internal circuit and without complicating the element structure.

[0065]

As described above, according to the first aspect of the present invention,
According to the protection circuit of the semiconductor device of the present invention, the connection portion on the input end side is provided between the electrode pad and the diffusion layer electrode of the MOS transistor (insulated gate type field effect transistor) connected to the internal circuit. By providing a high-resistance resistance element having a silicide layer, an overvoltage applied to the MOS transistor can be reduced, and the resistance impedance existing in the resistance element can be reduced to reduce the RC impedance to the internal circuit. The effect of the constant can be kept low. Therefore, in a semiconductor device in which a silicide layer is formed by a self-aligned silicide method on a surface of a diffusion layer constituting an internal circuit or a surface of a diffusion layer of the MOS transistor, stable device characteristics are obtained without complicating the device structure. In this state, it is possible to obtain a protection circuit having sufficient withstand voltage characteristics and capable of ensuring high-speed operation of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a protection circuit according to a first embodiment.

FIG. 2 is an equivalent circuit diagram illustrating a protection circuit according to the first embodiment.

FIG. 3 is a layout diagram of a protection circuit according to the first embodiment.

FIG. 4 is an essential part cross-sectional view showing a modification of the protection circuit of the first embodiment.

FIG. 5 is a cross-sectional process diagram illustrating an example of a process of forming the protection circuit according to the first embodiment.

FIG. 6 is a sectional view of a main part of a protection circuit according to a second embodiment.

FIG. 7 is an equivalent circuit diagram illustrating a protection circuit according to a second embodiment.

FIG. 8 is a layout diagram of a protection circuit according to a second embodiment.

FIG. 9 is a cross-sectional process diagram illustrating an example of a process of forming the protection circuit according to the second embodiment.

FIG. 10 is an essential part cross sectional view showing a modification of the protection circuit of the second embodiment.

FIG. 11 is a layout diagram showing a modification of the protection circuit of the second embodiment.

FIG. 12 is a sectional process view showing an example of a forming process of a modification of the second embodiment.

FIG. 13 is an equivalent circuit diagram illustrating a conventional protection circuit.

[Explanation of symbols]

1,1 ', 6,6' protection circuit 2 electrode pad
3 Internal circuit 11 MOS transistor (insulated gate field effect transistor) 11a Drain (first diffusion layer electrode) 11b Source (second diffusion layer electrode) 14, 14 ', 61, 61' Second resistance element (resistance) Element) 14a, 61d Silicide layer 14b Polycrystalline silicon layer 61a Source (input end) 61b Gate electrode (input end) 61c Drain (output end)

Claims (2)

[Claims] An insulated gate provided between an electrode pad and an internal circuit, wherein a first diffusion layer electrode is connected to the electrode pad and the internal circuit, and a second diffusion layer electrode is connected to a reference potential. In a protection circuit for a semiconductor device having a field effect transistor, a silicide layer connected to the electrode pad and a polycrystalline silicon connected to the internal circuit are provided between the electrode pad and the first diffusion layer electrode. A protection circuit for a semiconductor device, comprising: a resistance element comprising: 2. An insulated gate provided between an electrode pad and an internal circuit, wherein a first diffusion layer electrode is connected to the electrode pad and the internal circuit, and a second diffusion layer electrode is connected to a reference potential. In a protection circuit for a semiconductor device having a field-effect transistor, between the electrode pad and the first diffusion layer electrode, an input terminal is connected to the electrode pad and an output terminal is connected to the internal circuit. A resistance element including a withstand voltage n-channel insulated gate field effect transistor and a high withstand voltage p-channel insulated gate field effect transistor is provided, and a silicide layer is provided at a connection portion on the input end side of the resistance element. A protection circuit for a semiconductor device, characterized in that: