JPH1022461A - Electrostatic discharge protection transistor and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: The present invention provides an ESD protection transistor and a method of manufacturing the same, in which a drain structure is changed so that a drain region can effectively act as a ballast resistor and a process step can be simplified. I do. SOLUTION: The electrical protection transistor according to the present invention includes a first conductive type semiconductor substrate; a gate formed on the substrate; a second conductive type well formed on the substrate on one side of the gate; An isolation film formed in the well and separated from the gate; a second conductivity type source formed on the substrate on the other side of the gate; formed in the well and formed in the well region; A second conductivity type drain region including a first impurity region formed between a gate and one side of the device isolation film and a second impurity region formed on the other side of the device isolation film; both sides of the gate And a metal layer formed on the gate and the source / drain regions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to an electrostatic discharge.
The present invention relates to a transistor for protecting an organic discharge and a method for manufacturing the same.

[0002]

2. Description of the Related Art Electrostatic discharge (Electro Stat)
The ic Discharge (hereinafter, referred to as ESD) is one of the factors that affect the reliability of a semiconductor chip and is generated when the semiconductor chip is used or when the semiconductor chip is mounted on a system and causes damage to the chip. Therefore, in order to protect such ESD, E
A circuit for protecting SD is incorporated.

Conventional ESD built into a semiconductor chip
The protection circuit is shown in FIG.

[0004] Between the input pad 10 and the pre-buffer 30, E
An SD protection circuit 20 is provided.

The ESD protection circuit 20 includes a PMOS transistor (PM) and an NMOS transistor (NM) connected in series to respective power supply voltages (VDD, VSS). The gate and source of the PMOS transistor (PM) are connected and the power supply voltage VDD is applied, and the gate and source of the NMOS transistor (NM) are connected and the power supply voltage VSS is applied. PMOS transistor (P
M) and the drain of the NMOS transistor (NM) are connected through a node A to the input pad 10 and the prebuffer 30 composed of a CMOS inverter.

[0006] The ESD protection circuit 20 has a voltage E equal to or higher than VDD.
When SD is applied through input pad 10, PMO
S is turned on to prevent EDS from being applied by the pre-buffer 30, and when ESD equal to or lower than VSS is applied, N is applied.
This prevents a high voltage from being applied to the pre-buffer 30 by turning on the MOS.

Next, a method for manufacturing a conventional ESD protection transistor will be described with reference to FIG.

As shown in FIG. 4, a LOCOS (LOCal Oxidation) is formed on a semiconductor substrate 1.
f Silicon) field oxide film 2
Is formed, and a gate oxide film 3 and a gate 4
Is formed. High concentration impurity ions are implanted in the substrate 1 using the gate 4 as a mask to form source / drain regions 5a and 5b.

Thereafter, sidewall spacers 6 are formed on both sides of the gate by a known method, and a metal having a resistance to oxidation, such as
The gate 4 and the source / drain regions 5a and 5b are formed by selective deposition using titanium, tungsten, or the like.
A metal silicide layer 7 is formed thereon. An interlayer insulating film 8 is formed on the substrate 1, contact portions of the source / drain regions 5a and 5b are exposed by photolithography and a stamping process, and metal wiring layers 9a and 9b for interconnection are formed in the contact portions. It is formed.

[0010]

In order to reduce the parasitic resistance of a highly integrated semiconductor device, silicide is selectively formed in the gate and source / drain regions as described above. Silicide is ESD
Deteriorates the characteristics of the protection transistor. That is, the silicide layer having a low sheet resistance formed on the surface of the source / drain region suppresses the function of the drain region as a velast resistance, thereby lowering the ESD characteristics.

Therefore, conventionally, a silicide structure has been
When the present invention is applied to a protection transistor, a separate process is added to prevent silicide from being formed in a drain region, so that not only the manufacturing cost increases but also the yield decreases.

It is an object of the present invention to provide an E
An ESD protection transistor and a method of manufacturing the same, in which a drain structure is changed and a silicide structure is applied to an NMOS transistor of an SD prevention circuit so that a drain region can effectively function as a ballast resistor and a process step can be simplified. I will provide a.

[0013]

In order to achieve the object of the present invention, an electrostatic discharge protection transistor according to the present invention comprises a first transistor.
A conductive type semiconductor substrate; a gate formed on the substrate; a second conductive type well formed on one side of the gate on the substrate; an element isolation film formed in the well and separated from the gate; A second conductivity type source region formed on the other side of the gate in the substrate; a second source region formed in the well and formed between the gate and one side of the device isolation film in the well region; A second conductivity type drain region including one impurity region and a second impurity region formed on the other side of the device isolation film; sidewall spacers formed on both sides of the gate; and the gate and the source / drain A metal layer formed on the region; an interlayer insulating film formed on the substrate; contacts formed on the interlayer insulating film on the second impurity region of the source region and the drain region, respectively. Lumpur; and characterized in that it comprises a metal wiring layer formed respectively on the contact hole on the interlayer insulating film.

According to another embodiment of the present invention, there is provided an electrostatic discharge protection transistor comprising: a first conductive type semiconductor substrate; a gate formed on the substrate; a second conductive type second gate formed on one side of the gate on the substrate. A second well of a second conductivity type formed on the other side of the gate in the substrate; a first isolation film formed in the first well and separated from one side of the gate; A second element isolation film formed in the second well and separated from the other side of the gate; formed in the first well;
A first impurity region formed between the gate and one side of the first device isolation film in a well and a second impurity region formed on the other side of the first device isolation film in the first well; A source region formed in the second well; a first impurity region formed between the gate and the side of the second element isolation film in the second well; and a first element formed in the second well. A drain region comprising a second impurity region formed on the other side of the isolation film; sidewall spacers formed on both sides of the gate; and a metal layer formed on the gate and source / drain regions. .

According to an embodiment of the present invention, there is provided a method of manufacturing an electrostatic discharge protection transistor, comprising: forming an element isolation film on a first conductive type semiconductor substrate; Forming a second conductivity type well in the semiconductor substrate; forming a gate separated from the device isolation layer on the substrate; forming a source region on a side of the gate on the substrate; Forming a drain region including first and second impurity regions formed in the well on the other side and separated by the device isolation layer and electrically connected through the well; sidewalls on both sides of the gate Forming a spacer; and forming a metal layer on the gate and the source / drain regions.

According to another embodiment of the present invention, there is provided a method of fabricating an electrostatic discharge protection transistor, comprising forming first and second isolation layers separated from each other on a semiconductor substrate of a first conductivity type; Forming first and second wells of a second conductivity type on the semiconductor substrate including the second device isolation film; forming a gate on the substrate between the first and second device isolation films; A source region including first and second impurity regions formed in the first well and electrically connected through the first well and separated by the second device isolation layer. And a drain region electrically connected through the second well and formed of the first and second impurity regions formed in the second well is connected to the first and second wells, respectively. Step for forming; step formed on both sides on the sidewall spacers of the gate; and characterized in that it comprises a step of forming a metal layer on the gate and the source / drain regions.

The metal silicide layer formed on the drain region is cut off by the element isolation oxide film, and the drain region performs a function of a verast resistance between the gate and the contact of the second metal wiring layer by the well, thereby preventing the ESD. The characteristics of the transistor for use are improved.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS.

First, E according to a preferred embodiment of the present invention
The method of manufacturing the transistor for preventing SD will be described in detail with reference to FIGS.

As shown in FIG. 1, the semiconductor substrate 20
First and second element isolation films 21a and 21b separated by a predetermined distance by the LOCOS method are formed thereon, and first and second well regions 22a and 22b of a predetermined conductivity type, for example, n-type or p-type are formed. It is formed on the substrate 20 while including the element isolation films 21a and 21b. At this time, the first
And the substrate 20 between the second well regions 22a and 22b becomes a channel region of the MOS transistor.

As shown in FIG. 2, the first and second
A gate oxide film 23 and a polysilicon gate 24 are formed on the substrate 20 between the well regions 22a and 22b by a known method. Then, high-concentration impurity ions are implanted into the surface of the substrate 20 using the gate 24 as a mask to form source / drain regions 25 and 26. The source region 25 includes first and second impurity regions 25a and 25b formed in the first well region 22a. The first and second impurity regions 25a and 25b are separated from each other by the first element isolation film 21a. It is electrically connected through the first well region 22a. The drain region 26 includes first and second impurity regions 26a and 26b formed in the second well region 22b, and the first and second impurity regions 26a and 26b are formed in the second element isolation film 21b.
And the second well region 22b
Are electrically connected to each other.

As shown in FIG. 3, sidewall spacers 27 are formed on both side walls of the gate 24 by a known method, and are selected from transition metals such as Ti, Cr, Pt, and Ni on the substrate 20. One metal is deposited. Then
The silicon and the deposited metal react by a heat treatment process at a temperature of 500 to 800 ° C., and a metal silicide layer 28 is formed on the gate 24 and the source / drain regions 25 and 26. Then, NH ₄ OH / H ₂ O ₂ / H
_The unreacted metal was selectively wet-etched by a mixed solution of ₂ O or a mixed solution of H ₂ O ₄ / H ₂ O ₂ .

At this time, a metal layer may be selectively formed instead of the metal silicide layer 28, but such a metal layer is formed after the formation of the side wall spacer 27 and a mixed gas of WF ₆ / H ₂ or WF. _The gate 24 and the source / drain regions 2 containing silicon using a mixed gas of ₆ / SiH ₄
It is formed by being deposited only on 5, 26.
Accordingly, since the tungsten film is deposited only on the selected region, a process of removing unreacted metal that has been performed during the formation of the metal silicide is not required.

Thereafter, an interlayer insulating film 29 is formed on the substrate 20. Element isolation film 21 in source / drain regions 25 and 26 by photolithography and etching processes
The contact portions of the respective second impurity regions 25b and 26b separated from the gate 24 by the a and 21b are exposed, and the metal wiring layers 30a and 30b are formed in the contact portions.
Is formed.

According to the above-described embodiment, the metal silicide layer 28 formed at the contact portion of the source / drain regions 25 and 26 improves the contact characteristics by contact with the wiring layers 30a and 30b. Further, the metal silicide layer 28 formed above the first and second impurity regions 26a and 26b of the drain region 26 is cut off by the second element isolation oxide film 21b, and the drain region 26 becomes the second well region 2
By performing a ballast resistance function between the contact portion of the metal wiring layer 30b and the gate 24 by 2b, the characteristics of the ESD protection transistor are improved.

FIG. 4 is a sectional view of an ESD protection transistor according to another embodiment.

Referring to FIG. 4, the input pad 10 is connected only to the drain of the ESD protection transistor and has a predetermined conductivity type, for example, a p-type or n-type well 4.
2 is formed on one side of the gate 44 in the semiconductor substrate 40, and the element isolation film 41 is formed in the well 42.

Accordingly, source region 45 is formed on substrate 40 on the other side of gate 44. On the other hand, the drain region 46
Are formed in the well 42 and include first and second impurity regions 46 a and 46 b separated by the element isolation film 41 and electrically connected through the well 42.

The metal silicide layer 48 is formed on the source / drain regions 45 and 46 and the gate 44. In the drain region 46, the metal silicide layer 48 is
Separated by

The first metal wiring layer 50a is formed on the interlayer insulating film 49 at a contact portion of the source region 45, and the second metal wiring layer 50b is formed on the drain region 46 and the second impurity region 46.
The contact portion b is formed on the interlayer insulating film 49.

[0031]

According to the above embodiment, the metal silicide layer formed on the drain region is cut off by the element isolation oxide film, and the drain region has a ballast resistance between the gate and the contact of the second metal wiring layer by the well. By performing the function, the characteristics of the ESD protection transistor are improved.

On the other hand, the present invention is not limited to the above-described embodiment, and can be implemented with various modifications without departing from the technical scope of the present invention.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically illustrating a process of an ESD protection transistor according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view schematically illustrating a process of an ESD protection transistor according to a preferred embodiment of the present invention.

FIG. 3 is a cross-sectional view schematically illustrating a process of an ESD protection transistor according to a preferred embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating an ESD protection transistor according to an embodiment of the present invention;

FIG. 5 is a diagram showing a semiconductor circuit to which a conventional ESD protection circuit is applied.

FIG. 6 is a cross-sectional view showing a conventional ESD protection transistor.

[Explanation of symbols]

 20, 40: semiconductor substrate 21, 41: element isolation film 22, 42: well 23, 43: gate oxide film 24, 44: gate 25/26, 45/46: source / drain region 27, 47: side wall spacer 28 , 48: metal silicide layer 29, 49: interlayer insulating film 30, 50: metal wiring layer

Claims (30)

[Claims] A first conductivity type semiconductor substrate; a gate formed on the substrate; a second conductivity type well formed on the substrate on one side of the gate; A source of the second conductivity type formed on the substrate on the other side of the gate; one side of the gate and the device isolation layer in the well region; A second conductivity type drain region including a first impurity region formed therebetween and a second impurity region formed on the other side of the device isolation film; sidewall spacers formed on both sides of the gate; An electrostatic discharge protection transistor comprising a gate and a metal layer formed on the source / drain region. 2. an interlayer insulating film formed on the substrate; contact holes formed in the interlayer insulating film on second impurity regions of the source region and the drain region, respectively; The electrostatic discharge protection transistor according to claim 1, further comprising a metal wiring layer formed in each of the contact holes. 3. The transistor as claimed in claim 1, wherein the device isolation film is a field oxide film. 4. The transistor as claimed in claim 1, wherein the metal layer is a metal silicide. 5. The transistor as claimed in claim 4, wherein the metal silicide is a transition metal silicide. 6. The transistor according to claim 5, wherein the transition metal is one of Ti, Cr, Pt, and Ni. 7. The transistor according to claim 1, wherein the metal layer is tungsten. 8. The first and second drain regions of the first and second drain regions.
The transistor of claim 1, wherein the impurity region is isolated by the device isolation layer and is electrically connected through the well. 9. a semiconductor substrate of a first conductivity type; a gate formed on the substrate; a first well of a second conductivity type formed on one side of the gate on the substrate; A second well of the second conductivity type formed on the side of the gate; a first element isolation film formed in the first well and separated from one side of the gate; formed in the second well; A second device isolation film separated from the other side of the gate; formed in the first well,
A first impurity region formed between the gate and one side of the first device isolation film in a well; and a first impurity region formed in the first well.
A source region comprising a second impurity region formed on the other side of the device isolation film; a source region formed in the second well and formed between the gate and the second device isolation film in the second well. A drain region comprising a first impurity region formed and a second impurity region formed on the other side of the first element isolation film in the second well; sidewall spacers formed on both sides of the gate; An electrostatic discharge protection transistor comprising a metal layer formed on a drain region. 10. An interlayer insulating film formed on the substrate;
A contact hole formed in the interlayer insulating film on the second impurity region of the source / drain region; and a metal wiring layer formed in the contact hole on the interlayer insulating film. Item 9
3. The transistor for electrostatic discharge protection according to 1. 11. The transistor of claim 9, wherein the device isolation film is a field oxide film. 12. The transistor as claimed in claim 9, wherein the metal layer is a metal silicide. 13. The transistor as claimed in claim 12, wherein the metal silicide is a transition metal silicide. 14. The transistor of claim 13, wherein the transition metal is one of Ti, Cr, Pt, and Ni. 15. The transistor according to claim 9, wherein the metal layer is a tungsten film. 16. The device of claim 9, wherein the first and second impurity regions of the drain region are separated by the first device isolation layer and are electrically connected through a second well. ESD protection transistor. 17. The first and second of the source region.
The transistor of claim 9, wherein the impurity regions are separated by the second isolation layer and are electrically connected through the first well. 18. An element isolation film on a first conductivity type semiconductor substrate; forming a second conductivity type well on the semiconductor substrate including the element isolation film; and forming the element isolation film on the substrate. Forming a gate remote from;
A source region formed on the substrate on the negative side of the gate, first and second regions formed in the well on the other side of the gate, separated by the device isolation film, and electrically connected through the well; Forming a drain region comprising an impurity region; forming sidewall spacers on both sides of the gate; and forming the gate and the source /
A method for manufacturing an electrostatic discharge protection transistor, comprising: forming a metal layer on a drain region. 19. forming an interlayer insulating film on the substrate; etching the interlayer insulating film to expose respective metal layers on the second impurity region of the source region and the drain region. And forming a metal wiring layer on the interlayer insulating film so as to be in contact with the exposed metal layer. 20. The method of claim 18, wherein forming the device isolation layer is performed by field oxidation. 21. A method of forming a metal layer, comprising: depositing a transition metal on the substrate; forming a metal layer on the first and second impurity regions of the gate, the source region and the drain region. 20. The method of claim 18, further comprising: annealing the transition metal layer to form a silicide layer; and removing the transition metal remaining after the metal silicide layer is not formed. Of manufacturing transistors for semiconductors. 22. The method according to claim 21, wherein the metal is one of Ti, Cr, Pt, and Ni. 23. The method of claim 21, wherein the annealing is performed at a temperature of 500 to 800 ° C. 24. The method as claimed in claim 21, wherein the step of removing the transition metal is performed by wet etching. 25. The wet engraving step includes NH ₄ OH / H ₂
O ₂ / H ₂ O production method of the electrostatic discharge protection transistor as claimed in claim 24, characterized in that by mixing a solution of use. 26. The method according to claim 24, wherein the wet engraving process uses a mixed solution of H ₂ O ₄ / H ₂ O. 27. The method of claim 18, wherein the metal layer is formed by selectively depositing tungsten on the first and second impurity regions of the gate, the source, and the drain region. A method for producing the electrostatic discharge protection transistor according to the above. 28. The method of claim 27, wherein the tungsten film is selectively deposited by using a mixed gas of WF ₆ / H ₂ . 29. The tungsten film is made of WF ₆ / SiH
28. The method for manufacturing a transistor for electrostatic discharge protection according to claim 27, comprising using the mixed gas of ( ₄ ). 30. Forming first and second device isolation films separated from each other on a semiconductor substrate of a first conductivity type; forming a second device isolation film on the semiconductor substrate including the first and second device isolation films.
Forming first and second wells of a conduction type, respectively; forming a gate on the substrate between the first and second device isolation films; separating the first and second device wells by the first device isolation film; A source region that is electrically connected through the well and formed in the first well and includes first and second impurity regions; and a source region that is separated by the second isolation layer and electrically connected through the second well. Forming drain regions comprising first and second impurity regions formed in the second well in the respective first and second wells; forming sidewall spacers on both sides of the gate; and the gate And forming a metal layer on the source / drain regions.