JPH10117218A - Phase difference detection circuit - Google Patents

Abstract

(57) [Problem] To provide a phase difference detection circuit that can normally perform phase detection regardless of duty ratio disturbance. SOLUTION: An intermediate frequency signal and a local oscillation signal inputted from the outside are divided by a first and second frequency dividers 2 and 3 into signals having a double cycle, respectively, so that a duty ratio of 50% is obtained. The signals are input to the exclusive OR circuit 4 and the D-type flip-flop 5 as signals, respectively.
Is input to the decoder 8 together with the output signal of the D-type flip-flop 5 through the low-pass filter 6 and the analog-digital converter 7, and the decoder 8 outputs a phase difference between the intermediate frequency signal and the local oscillation signal. , A signal whose output signal level changes proportionally is output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase difference detection circuit used in a digital radio communication receiver, and more particularly to a phase difference detection circuit for stabilizing the operation.

[0002]

2. Description of the Related Art As in the case of analog communication, some communication systems in digital wireless communication are designed to convert information of a baseband signal into a phase shift of a carrier wave to transmit information. , Two-phase PSK (Phase Shift
It is publicly known that there is a four-phase PSK or the like. It is also known and well-known that there are synchronous detection and delay detection for demodulating such a signal such as BPSK. In particular, when delay detection is performed, the phase difference detection circuit is used for the circuit constituting the receiver. One important thing.

FIG. 7 shows an example of a conventional phase difference detection circuit. The configuration and operation of the circuit will be described below with reference to FIG. This phase difference detection circuit
Intermediate frequency signal in a value-shaped state (hereinafter referred to as “IF signal”
Say ) And a local oscillation signal that has also been subjected to binary shaping as input signals.

The IF signal whose amplitude has been limited by the limiter 1 is supplied to an exclusive OR circuit (hereinafter referred to as "EXOR circuit") 4 and a D-type flip-flop circuit (hereinafter referred to as "DF / F /
F circuit ". 5), while the local oscillation signal is also input to the EXOR circuit 4 and the DF / F circuit 5.

In the EXOR circuit 4 and the DF / F circuit 5, as a result of phase comparison, the output characteristics of the EXOR circuit 4 after passing through a low-pass filter circuit (abbreviated as "LPF" in FIG. 7) 6 And FIG. 8 (a) shows a solid line a.
As shown in the above, when the phase difference of the input signal is between 0 and π (radian), the output signal level increases in proportion to the increase of the phase difference, while the phase difference is between π and 2π (radian). Has a triangular characteristic in which the output signal level decreases in inverse proportion to the increase in the phase difference.

The output characteristic of the DF / F circuit 5 has a phase difference of 0 to π as shown by a solid line b in FIG.
(Radian), the output signal level is zero, and when the phase difference is between π and 2π (radian),
The output signal level is such as to be held at the logical output "1".

The output signal of the EXOR circuit 4 output as described above is subjected to an analog-to-digital converter ("A / D" in FIG. 7) after unnecessary high-frequency components are removed by a low-pass filter circuit 6. The signal is converted into a digital signal by the abbreviation 7 and input to the decoder 8.

The output signal of the DF / F circuit 5 is input to the decoder 8 at the same time.
The decoder 8 outputs a phase detection signal having a proportional relationship as indicated by a dotted line Φ3 in FIG. 8A with respect to the phase difference between the IF signal and the local oscillation signal.

[0009]

However, in the above-described phase difference detection circuit, it is assumed that the input IF signal and the local oscillation signal are each a signal having a duty ratio of 50%. In the case of deviation from this, the output characteristic of the decoder 8 becomes, for example, the output characteristic as shown in FIG. 9, and there is a problem that the phase angle of the received signal cannot be correctly detected.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a phase difference detection circuit capable of performing phase detection normally irrespective of disturbance in the duty ratio of an input signal. Another object of the present invention is to provide a phase difference detection circuit that performs stable and reliable phase difference detection with a simple circuit configuration.

[0011]

According to a first aspect of the present invention, there is provided a phase difference detection circuit comprising a phase difference between an intermediate frequency signal obtained by frequency-converting a signal subjected to digital phase modulation and a local oscillation signal. A phase difference detection circuit that outputs a signal corresponding to the frequency of the intermediate frequency signal and the local oscillation signal. The phase difference between the divided intermediate frequency signal and the local oscillation signal is output along with the increase in the phase difference until the phase difference reaches a magnitude corresponding to a half cycle of the intermediate frequency signal or the local oscillation signal divided by the frequency dividing means. As the level increases,
The phase difference between the intermediate frequency signal divided by the frequency divider and the local oscillation signal is large enough to correspond to a half cycle to one cycle of the intermediate frequency signal or the local oscillation signal divided by the frequency divider. In the meantime, the first phase comparing means in which the output level decreases as the phase difference increases, and the phase difference between the intermediate frequency signal and the local oscillation signal divided by the dividing means,
A period up to a size corresponding to a half cycle of the intermediate frequency signal or the local oscillation signal divided by the divider, and a half cycle of the intermediate frequency signal or the local oscillation signal divided by the divider. A second phase comparing means for outputting a signal having a signal level different from the period up to a period corresponding to one cycle, and the intermediate phase based on the output signals of the first phase comparing means and the second phase comparing means. Decoder means for outputting a signal having an output level corresponding to the phase difference between the frequency signal and the local oscillation signal. The intermediate frequency signal and the local oscillation signal input from the outside are divided by the frequency dividing means. As a result, each signal is output as a signal having a duty ratio of 50%. Even if the duty ratios of the intermediate frequency signal and the local oscillation signal input from the outside deviate from 50%, the first phase comparison means and the second phase comparison means always output a signal having a duty ratio of 50% by the frequency dividing means. Is input and the output signal is input to the decoder means, so that a stable and reliable phase difference detection is performed, unlike the related art.

In particular, the first phase comparing means includes an exclusive OR circuit for outputting an exclusive OR of the intermediate frequency signal divided by the frequency dividing means and the local oscillation signal, and the exclusive OR circuit. And an analog-to-digital converter for converting the output signal of the integrating means into a digital signal. Further, it is preferable that the second phase comparing means is one using a D-type flip-flop circuit.

According to a fourth aspect of the present invention, a phase difference detection circuit outputs a signal corresponding to a phase difference between an intermediate frequency signal obtained by frequency-converting a signal subjected to digital phase modulation and a local oscillation signal. A frequency divider that divides the intermediate frequency signal into a signal having a frequency of 1/2.
An exclusive-OR circuit that receives an output signal of the frequency divider and a signal having a period twice as long as the local oscillation signal as input signals, and outputs an exclusive-OR of these two signals; An integrating circuit for integrating the output signal of the circuit; and an analog circuit for converting the output signal of the integrating circuit into a digital signal.
A digital converter, a D-type flip-flop circuit which receives an output signal of the frequency divider as an input signal, and inputs a signal having a cycle twice as long as the local oscillation signal as a clock signal, the analog-digital converter, A decoder that outputs a signal having an output level corresponding to a phase difference between the intermediate frequency signal and the local oscillation signal based on an output signal of the D-type flip-flop circuit. The frequency signal is frequency-divided by the frequency divider to be output as a signal having a duty ratio of 50%. On the other hand, by inputting a signal having a cycle twice as long as the local oscillation signal, the exclusive OR circuit and the D Unlike the conventional type, a signal having a duty ratio of 50% is reliably input to the flip-flop circuit, so that a stable output signal can be obtained. As a result, stable reliable operation is ensured even in the subsequent circuit, and serves as a fact that the stable and reliable phase difference detection is performed.

According to a fifth aspect of the present invention, a phase difference detection circuit outputs a signal corresponding to a phase difference between an intermediate frequency signal obtained by frequency-converting a signal subjected to digital phase modulation and a local oscillation signal. A frequency divider for dividing the local oscillation signal into a signal having a frequency of 1/2.
An exclusive-OR circuit that receives an output signal of the frequency divider and a signal having a cycle twice as long as the intermediate frequency signal as an input signal, and outputs an exclusive-OR of these two signals; An integrating circuit for integrating the output signal of the circuit; and an analog circuit for converting the output signal of the integrating circuit into a digital signal.
A digital converter, a D-type flip-flop circuit for inputting a signal having a cycle twice as long as the intermediate frequency signal as an input signal, and inputting an output signal of the frequency divider as a clock signal, the analog-digital converter, A decoder for outputting a signal having an output level corresponding to the phase difference between the intermediate frequency signal and the local oscillation signal based on the output signal of the D-type flip-flop circuit, and The oscillation signal is divided by the divider to be output as a signal having a duty ratio of 50%, while the signal having a period twice as long as the intermediate frequency signal is inputted, so that the exclusive OR circuit and the D signal are inputted. Unlike the conventional type, a signal having a duty ratio of 50% is reliably input to the flip-flop circuit, so that a stable output signal can be obtained. As a result, stable reliable operation is ensured even in the subsequent circuit, and serves as a fact that the stable and reliable phase difference detection is performed.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a phase difference detecting circuit according to the present invention will be described below with reference to FIGS. Here, FIG. 1 is a configuration diagram of a phase difference detection circuit according to a first embodiment of the present invention, and FIG. 2 is a configuration diagram of a phase difference detection circuit according to a second embodiment of the present invention. FIG. 3 is a configuration diagram of a phase difference detection circuit according to a third embodiment of the present invention, and FIG. 4 is a waveform diagram showing changes in signals before and after frequency division by a frequency divider. FIG. 5 is a characteristic diagram showing the characteristics of the phase comparison, and FIG. 5A is a characteristic diagram showing the relationship between the input phase difference and the output signal level of the exclusive OR circuit. 6B is a characteristic diagram showing the relationship between the input phase difference and the output signal level of the D-type flip-flop circuit, and FIG. 6 is a characteristic diagram showing another example of the phase comparison characteristic. FIG. 3A is a characteristic diagram showing the relationship between the input phase difference of the exclusive OR circuit and the output signal level, and FIG. It is a characteristic diagram showing the relationship between the input phase difference and the output signal level type flip-flop circuit. The members, arrangements, and the like described below do not limit the present invention, and can be variously modified within the scope of the present invention.

If the function of the phase difference detection circuit is generally described, an intermediate frequency signal (hereinafter, referred to as an "IF signal") which is binary-shaped and input from an external circuit (not shown).
And an output signal of a local signal oscillation circuit (not shown) that has been subjected to binary shaping as an input signal;
The phase comparison between the local oscillation signal and the IF signal is performed, and a signal having an output level corresponding to the phase difference is output.

A phase difference detecting circuit according to an embodiment of the present invention has a limiter 1 for limiting the amplitude of an IF signal, and a first frequency divider for dividing an IF signal input via the limiter 1. 2 and a second frequency divider 3 for dividing the frequency of the local oscillation signal (see FIG. 1).

The first and second frequency dividers 2 and 3 according to the embodiment of the present invention can obtain an output signal having a frequency twice as long as the frequency of the input signal, that is, twice the frequency of the input signal. It is supposed to be. For example, if the input IF signal is
As shown in (a), when a signal whose logical value is “1” for 35% of one cycle and whose logical value is “0” for the remaining period (65%) is the first frequency divider, The output of No. 2 is a signal having a duty ratio of 50% as shown in FIG.

The output terminal of the first frequency divider 2 and the output terminal of the second frequency divider 3 are both connected to the input side of the exclusive OR circuit 4 and the output terminal of the first frequency divider 2 The output terminal is connected to a D input terminal of a D-type flip-flop circuit (hereinafter referred to as "DF / F circuit") 5, and the output terminal of the second frequency divider 3 is connected to a clock terminal (referred to as "CK" in FIG. 1). (Places described).

An exclusive OR circuit (hereinafter referred to as "EXOR circuit")
Say And 4) an output signal having a theoretical value of "1" is output when one of the two input signals is at the level of the logical value "1".

On the other hand, the DF / F circuit 5 changes the signal output from the second frequency divider 3 from a logical value "1" to a logical value "0".
In this case, when the signal output from the first frequency divider 2 has a logical value "1", an output signal having a logical value "1" is output.

The output characteristic of the DF / F circuit 5 according to the embodiment of the present invention is, as shown by the solid line B in FIG. 5B, the position of the IF signal before the frequency division and the local oscillation signal. When the phase difference is between 0 and 2π (radian), the output signal of the logical value “0” is output when the phase difference is between 2π and 4π (radian). It is output.

At the subsequent stage of the EXOR circuit 4, a low-pass filter 6 (abbreviated as "LPF" in FIG. 1) as an integrating circuit and an analog-to-digital converter (hereinafter "A")
/ D converter "and abbreviated as" A / D "in FIG. 7) are connected in order, and the output terminal of the A / D converter 7 is connected to the input side of the decoder 8 together with the output terminal of the DF / F circuit 5.

The low-pass filter 6 as an integrating circuit is
This is for removing unnecessary high-frequency components contained in the output signal from the EXOR circuit 4 and performing an integration process on the output signal of the EXOR circuit 4. The output signal is converted into a digital signal by the A / D converter 7. Input to the decoder 8.

EXOR after passing through low-pass filter 6
As shown by the solid line A in FIG. 5A, the output signal characteristic of the circuit 4 is between 0 and 2π (radian) in terms of the phase difference between the IF signal before frequency division and the local oscillation signal. As the phase difference increases, the level of the output signal also increases. When the phase difference is exactly 2π, the output signal has a logical value “1”. When the phase difference is between 2π and 4π (radian), the output signal level decreases as the phase difference increases.

Based on the output signal of the A / D converter 7 and the output signal of the DF / F circuit 5, the decoder 8 increases the phase difference between the IF signal and the local oscillation signal, and increases the output signal level. Has an output characteristic that increases. That is, the output characteristic of the decoder 8 according to the embodiment of the present invention is, as indicated by the dotted line Φ1 in FIG. 5A, 0 to 4π in terms of the phase difference between the IF signal before frequency division and the local oscillation signal. (Radian), the output signal level increases linearly with an increase in the phase difference.

The operation of the phase difference detection circuit according to the embodiment of the present invention having the above configuration will be described generally.
When the signal and the local oscillation signal are input, these two signals are frequency-divided by the first and second frequency dividers 2 and 3 so as to have a double cycle. For this reason, the duty ratio of the IF signal and the local oscillation signal is set to a value (50
%), The EXOR circuit 4 and the DF / F
The input to the circuit 5 is at a duty ratio of 50% as shown in FIG.

The EXOR circuit 4 outputs an output signal when the phase difference between the IF signal and the local oscillation signal (the phase difference between the IF signal before frequency division and the local oscillation signal) is 0 to 4π (radian). Are output along a so-called triangular characteristic as shown in FIG.

On the other hand, in the DF / F circuit 5, the IF
While the phase difference between the signal and the local oscillation signal (the phase difference between the IF signal and the local oscillation signal before frequency division) is 0 to 2π (radian), the output signal having the logical value “0” has the phase difference of 2π to 2π. 4π
During (radian), the output signal of the logical value “1” is output.

The output signal of the EXOR circuit 4 is supplied to a DF / F circuit 5 via a low-pass filter 6 and an A / D converter 7.
The signal level is input from the decoder 8 along with the increase in the phase difference between 0 and 4π (radian) in terms of the phase difference before the frequency division between the IF signal and the local oscillation signal. The output signal is output so as to increase linearly (see the dotted line Φ1 in FIG. 5A).

Note that the decoder 8 includes a dotted line Φ2 in FIG.
As shown in the above, when the phase difference between the IF signal and the local oscillation signal before the frequency division is 0 to 2π and 2π to 4π (radian), the output characteristic increases as the phase difference increases. You may comprise so that it may have. That is, the output characteristics may have a triangular characteristic with a phase difference of 0 to 2π and 2π to 4π (radian).

Next, a second embodiment will be described with reference to FIG. The same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted.
Hereinafter, different points will be mainly described. The circuit configuration of the second embodiment is different from that of the first embodiment in that the frequency divider is used only for the IF signal.

That is, in the second embodiment, the first frequency divider 2 is provided between the limiter 1 and the EXOR circuit 4, while the local oscillation signal is supplied to the EXOR circuit 4 and the DF / F The signal is directly input to the F circuit 5.
Further, in this second embodiment, FIG. 2 shows that the local oscillation signal input from the outside has a frequency of 1/2 of the frequency fIF of the IF signal, that is, fLO = fIF / 2. Input condition to the circuit.

As described above, inputting the frequency fLO of the local oscillation signal as 1/2 of the frequency fIF of the IF signal is as follows.
This corresponds to inputting the local oscillation signal to the DF / F circuit 5 via the second frequency divider 3 in the first embodiment, and the second embodiment has this frequency dividing function. The local oscillation signal is supplied to an external circuit (not shown) for generating the local oscillation signal.

Therefore, the operation of the phase difference detecting circuit according to the second embodiment is basically the same as that of the first embodiment, and the output characteristic of the decoder 8 is represented by a dotted line Φ1 in FIG. 6 or a characteristic curve indicated by a dotted line Φ2 in FIG. 6 (a).

Next, a third embodiment will be described with reference to FIG. The same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted.
Hereinafter, different points will be mainly described. In the third embodiment, a frequency divider is used only for a local oscillation signal.

That is, in the third embodiment, the point that the second frequency divider 3 is provided before the DF / F circuit 5 is the same as in the first embodiment, Limiters 1 and E
The first point is that it is directly connected to the XOR circuit 4 and the first frequency divider 2 in the first embodiment is not provided.
This is different from the embodiment. Contrary to the second embodiment, the IF signal is input to an external circuit (not shown) which is set to a frequency which is 1/2 of the frequency fLO of the local oscillation signal in advance. is there.

Therefore, the EXOR circuit 4 and the DF /
Since the signals input to the F circuit 5 are basically not different from those of the first embodiment, the basic circuit operation is the same as that of the first embodiment, and the output characteristic of the decoder 8 is 5 (a) or a characteristic curve indicated by a dotted line Φ2 in FIG. 6 (a).

[0039]

As described above, according to the present invention,
Even if the duty ratio of the intermediate frequency signal and the local oscillation signal is disturbed, the phase difference is detected stably and reliably, so that even if the duty ratio is disturbed, the signal from which the disturbance has been removed can be replaced. Since the phase difference is used for phase difference detection, unlike the related art, the phase difference cannot be detected due to the disturbance of the duty ratio, and the phase difference can be detected stably and reliably.

Further, based on the conventional circuit configuration, the number of circuit elements added to this circuit configuration is reduced as much as possible.
There is an effect that it is possible to provide a phase difference detection circuit that performs stable and reliable phase difference detection with a simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a phase difference detection circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a phase difference detection circuit according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a phase difference detection circuit according to a third embodiment of the present invention.

FIG. 4 is a waveform chart showing changes in signals before and after frequency division by a frequency divider.

5A and 5B are characteristic diagrams showing characteristics of phase comparison, wherein FIG. 5A is a characteristic diagram showing a relationship between an input phase difference and an output signal level of an exclusive OR circuit, and FIG. FIG. 4 is a characteristic diagram illustrating a relationship between an input phase difference and an output signal level of a D-type flip-flop circuit.

6A and 6B are all characteristic diagrams showing another example of the phase comparison characteristic. FIG. 6A is a characteristic diagram showing the relationship between the input phase difference and the output signal level of the exclusive OR circuit. FIG. 3B is a characteristic diagram illustrating a relationship between an input phase difference and an output signal level of the D-type flip-flop circuit.

FIG. 7 is a configuration diagram illustrating an example of a conventional phase difference detection circuit.

FIG. 8 is a characteristic diagram showing characteristics of phase comparison in a conventional phase difference detection circuit, and FIG. 8A is a characteristic line showing a relationship between an input phase difference and an output signal level of an exclusive OR circuit. FIG. 3B is a characteristic diagram showing the relationship between the input phase difference and the output signal level of the D-type flip-flop circuit.

FIG. 9 is a characteristic diagram illustrating output characteristics of the phase difference detection circuit when the duty ratio deviates from a predetermined value.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Limiter, 2 ... 1st frequency divider, 3 ... 2nd frequency divider, 4 ... Exclusive OR circuit, 5 ... D-type flip-flop, 6 ... Low-pass filter, 7 ... A / D converter,
8 ... Decoder

Claims (5)

[Claims] 1. A phase difference detection circuit for outputting a signal corresponding to a phase difference between an intermediate frequency signal obtained by frequency-converting a signal subjected to digital phase modulation and a local oscillation signal, wherein the intermediate frequency signal is Signal and the local oscillation signal
Frequency dividing means for dividing the frequency of the signal into a signal having a frequency of / 2; and a phase difference between the intermediate frequency signal divided by the frequency dividing means and the local oscillation signal, the intermediate frequency signal divided by the frequency dividing means or While the output level increases as the phase difference increases up to a size corresponding to a half cycle of the local oscillation signal, the phase difference between the intermediate frequency signal divided by the frequency dividing means and the local oscillation signal is: First phase comparing means for decreasing an output level with an increase in phase difference during a period corresponding to a half cycle to one cycle of the intermediate frequency signal or the local oscillation signal divided by the frequency dividing means; A period in which the phase difference between the intermediate frequency signal divided by the frequency dividing means and the local oscillation signal reaches a magnitude corresponding to a half cycle of the intermediate frequency signal or the local oscillation signal divided by the frequency dividing means. And the frequency dividing means Of the intermediate frequency signal or the local oscillator signal 1
A second phase comparing means for outputting a signal of a signal level different from a period corresponding to a period corresponding to a period corresponding to a period corresponding to / 2 period to one period, based on output signals of the first phase comparing unit and the second phase comparing unit And a decoder for outputting a signal having an output level corresponding to the phase difference between the intermediate frequency signal and the local oscillation signal. 2. An exclusive OR circuit for outputting an exclusive OR of an intermediate frequency signal divided by a frequency dividing means and a local oscillation signal, the first phase comparing means comprising: 2. The phase difference detection circuit according to claim 1, further comprising an integration circuit for integrating the output signal of the first and second components, and an analog / digital converter for converting an output signal of the integration means into a digital signal. 3. The phase difference detection circuit according to claim 1, wherein the second phase comparison means uses a D-type flip-flop circuit. 4. A phase difference detection circuit for outputting a signal corresponding to a phase difference between an intermediate frequency signal obtained by frequency-converting a signal subjected to digital phase modulation and a local oscillation signal; A frequency divider for dividing a signal into a signal having a frequency of 1/2, and an output signal of the frequency divider and a signal having a cycle twice as long as the local oscillation signal are used as input signals.
An exclusive OR circuit that outputs an exclusive OR of two signals, an integration circuit that integrates an output signal of the exclusive OR circuit, and an analog-to-digital converter that converts an output signal of the integration circuit into a digital signal And a D-type flip-flop circuit which receives an output signal of the frequency divider as an input signal and inputs a signal having a cycle twice as long as the local oscillation signal as a clock signal, the analog / digital converter and the D-type flip-flop A decoder for outputting a signal having an output level corresponding to a phase difference between the intermediate frequency signal and the local oscillation signal based on an output signal of the loop circuit. 5. A phase difference detection circuit for outputting a signal corresponding to a phase difference between an intermediate frequency signal obtained by frequency-converting a signal subjected to digital phase modulation and a local oscillation signal, the local oscillation signal comprising: A frequency divider for dividing a signal into a signal having a frequency of 1/2, and an output signal of the frequency divider and a signal having a cycle twice as long as the intermediate frequency signal are used as input signals.
An exclusive OR circuit that outputs an exclusive OR of two signals, an integration circuit that integrates an output signal of the exclusive OR circuit, and an analog-to-digital converter that converts an output signal of the integration circuit into a digital signal A D-type flip-flop circuit for inputting a signal having a cycle twice as long as the intermediate frequency signal as an input signal and inputting an output signal of the frequency divider as a clock signal; the analog-digital converter and the D-type flip-flop A decoder for outputting a signal having an output level corresponding to a phase difference between the intermediate frequency signal and the local oscillation signal based on an output signal of the loop circuit.