JPH04315342A - Delay detection circuit - Google Patents

Abstract

PURPOSE:To decrease the circuit scale of the delay detection circuit demodulating a reception signal subjected to phase modulation and to reduce power consumption. CONSTITUTION:The relay detection circuit is featured that a frequency of a received IF signal subjected to binary shaping is given to a D flip-flop 1, in which the IF frequency is converted into a frequency being a difference from a local oscillation frequency, the resulting output and a K-phase reference phase signal from a K-stage ring counter 2 operated by a clock whose frequency is a multiple of K of the difference frequency are compared by a phase comparator 3, phase information phi1 of a carrier of a reception signal is detected by an encoder 4 from the result of comparison, a phase difference between the information phi1 and phase information phi2 resulting from delaying the information phi1 by one symbol is discriminated to obtain a demodulated data.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay detection circuit used in a receiver for digital communication.

0002

[Prior Art] Delay detection, which receives and demodulates a phase-modulated signal in digital communication, is a detection method that uses a received signal one time slot before as a reference phase signal, and the circuit is simpler than synchronous detection. It is widely used because of its characteristics. Conventionally, the above-mentioned delay detection circuit delays the waveform of the received IF signal that has been binary-shaped by a limiter by one symbol, compares it with the original binary IF signal, determines the phase difference, and outputs the demodulated signal. There is a circuit that obtains the following. FIG. 3 is a diagram showing an example of a configuration when a conventional delay detection circuit is used in a QPSK modulation receiver. In the figure, 31 is a delay circuit that sequentially stores the waveform while sampling the received IF signal binary-shaped by a limiter using a clock (CLK) and outputs a 1-symbol delayed signal IF', and has N stages synchronized with CLK. It can be configured with a shift register. 32 is a 90° phase shift circuit, which inputs the 1-symbol delayed signal IF' and shifts the phase by 90°.
33 is a first phase difference determination circuit, which inputs the received IF signal and the 1-symbol delayed signal IF', compares the phases of the in-phase components, and calculates the phase difference between the two inputs. , demodulated data DEM-I corresponding to the value
Determine and output. 34 inputs the received IF signal and the 90° phase-shifted signal IF' of the 1-symbol delayed signal IF', compares the phases of the orthogonal components, determines the phase difference between the two inputs, and generates the demodulated data DEM-Q corresponding to the value. This is a second phase difference determination circuit that determines and outputs the result.

0003

[Problems to be Solved by the Invention] However, in the above conventional circuit, the sampling CL supplied to the delay circuit 31
K must be operated at a frequency approximately 10 times higher than that of the received IF signal, which increases power consumption. Furthermore, the number of stages of the shift register that delays the IF signal is determined by the sampling C.
Let M be the ratio between the frequency of LK and the frequency of the received IF signal,
If the number of IF cycles with one symbol time length is N, then M
×N stages are required. As an example, set the IF frequency to 10.7
MHz, the symbol rate is 64kbps, and M is 10, then N=(10.7×106)/(64×103
)≒167. Therefore, the number of stages of the shift register is M×N≒1670 (stages), and not only is the number of stages significantly large, but the frequency of the sampling CLK is 10
7MHz, which makes it difficult to realize. The purpose of the present invention is to
The object of the present invention is to provide a delay detection circuit that achieves low power consumption by solving the above problems of circuit scale and power consumption.

0004

[Means for Solving the Problems] A delay detection circuit of the present invention converts the received signal into an intermediate frequency (IF) and converts it into a binary signal in order to obtain demodulated data by receiving a phase modulated signal in digital communication. A D-type flip-flop that outputs a signal having a frequency that is the difference between the local oscillator frequency fL and the IF signal frequency fIF according to a sampling clock of the local oscillator frequency fL from the local oscillator; a K-stage ring counter that operates at the rising or falling edge of a clock pulse K times (K is a natural number) and generates and outputs a K-phase reference phase; and a signal from the D-type flip-flop and the K-phase reference. A phase comparator that compares the phases and outputs a phase comparison result, an encoder that detects the instantaneous phase of the carrier wave of the received signal from the phase comparison result and outputs phase information φ1, and temporarily holds the phase information φ1. a register that outputs the phase information φ1 according to a clock K times the frequency of the difference; a delay circuit that outputs 1-symbol delayed phase information φ2 obtained by delaying the phase information φ1 by 1 symbol; The present invention is characterized by comprising a phase difference determination circuit that calculates a phase difference with one-symbol delayed phase information φ2 and outputs the demodulated data corresponding to the phase difference.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit block diagram showing a first embodiment of the present invention. In the figure, 1 is a D-type flip-flop (D-F/F) that inputs the received IF signal that has been binary-shaped by a limiter and operates using the local oscillator signal fL as a sampling clock (CLK), and serves as a frequency converter. Function. 2 is a ring counter that generates a large number of reference phase signals. The number of stages is K, where K is the number of reference phases for phase comparison. The frequency is |fIF−
It operates on the rising or falling edge of the clock pulse fL |×K. 3 is a phase comparator composed of 1 (outer 2 is the smallest integer greater than or equal to x) D-F/F;
The input from ring counter 1 is compared with one reference phase from ring counter 2, and a phase comparison result is output. 4 is an encoder that detects the instantaneous phase of a carrier wave from the phase comparison result from the phase comparator 3 and outputs phase information φ1. 5 is a register that formats and outputs the phase information φ1 according to the operating clock of the ring counter. A delay circuit 6 outputs one-symbol delayed phase information φ2 obtained by delaying the phase information φ1 from the register 5 by one symbol length. 7 is phase information φ1 and 1 symbol delayed phase information φ
This is a phase difference determination circuit which receives two input signals, calculates the phase difference between the two inputs, and outputs demodulated data corresponding to the phase difference.

FIG. 2 is a circuit block diagram showing a second embodiment of the present invention. In the figure, 21 is a D-type flip-flop, 23 is a phase comparator, 24 is an encoder, 2
5 is a register, 26 is a delay circuit, and 27 is a phase difference determination circuit, each of which is similar to the D type flip-flop 1 in FIG.
, phase comparator 3, encoder 4, register 5, delay circuit 6, and phase determination circuit 7. Reference numeral 22 denotes a ring counter composed of two ring counters each having an outer 1 stage (outer 2 being the smallest integer equal to or greater than x) which operates at the rising and falling edges of a rectangular CLK pulse with a duty of 50%.

[0007]

[Operation] The operation of the present invention based on the first embodiment shown in FIG. 1 will be explained below. First, the binary-shaped received IF signal is D-F
/F1, and is frequency-converted to about 10 times the symbol rate using a local oscillation signal which is a sampling clock, and is output. If the frequency of the local oscillator signal is fL and the IF frequency is fIF, the output frequency of DF/F1 is |
fIF−fL | Next, the output of DF/F1 is input to the phase comparator 3, and the output from the ring counter 2 is input to the phase comparator 3.
compared to the reference phase of Ring counter 2 is |fI
A clock with a frequency of F−fL |×K is input, and this is divided by K to generate a K-phase reference phase. The reference phase of this K phase is obtained by dividing the phase from 0 to 2π into K equal parts. Inside the phase comparator 3, outer 1 (outer 2 is the smallest integer greater than or equal to x)
The output of D-F/F1 is input to each of the D-F/Fs, and the comparison with the reference phase of one phase indicating the reference phase of 0 to π among the K-phase reference phases is repeated twice. By doing so, the result of comparison with the reference phase of the K phase is equivalently outputted. This phase comparison result indicates the instantaneous phase of the carrier of the received signal. The phase comparison result is input to encoder 4;
detects the instantaneous phase of the carrier of the received signal from the input result and outputs it to the register 5 as K types of phase information φ1. Phase information φ1 output from register 5 and φ1
is delayed by one symbol in the delay circuit 6, and the one-symbol delayed phase information φ2 is input to the phase difference determination circuit 7, φ1 and φ2 are compared, and phase determination information is output as demodulated data based on the amount of phase change. . Here, the delay circuit 6 that delays one symbol can be realized by a shift register having a data bit width of phase information φ1, and if the ratio of the sampling clock supplied to the shift register to the transmission rate is L, then L may be about 10 or more, and the number of stages of shift registers required is also L, so the conventional method requires a sampling clock with a frequency M (M≧10) times the reception IF signal frequency and M×N stage registers. Compared to conventional circuits, this can be achieved at considerably lower frequencies.

Next, the operation of the present invention based on the second embodiment shown in FIG. 2 will be explained. Here, all other operations except for the operation of the ring counter 22 are equivalent to the operations of the present invention based on the first embodiment of FIG. The ring counter 22 is the first
The frequency of the clock input to the ring counter 2 in the example of |fIF−fL|×K 1/2 frequency (
A clock with |fIF-fL |×K)/2 is input, and the K-phase is calculated by the outer one-stage ring counter that operates on the rising edge of this clock pulse and the outer one-stage ring counter that operates on the falling edge of the clock pulse. Generate a reference phase. As a result, even if the frequency of the reference clock that operates the ring counter 22 is 1/2 of that in the first embodiment, the same output as the ring counter 2 in FIG. 1 can be obtained, thereby further reducing power consumption. be able to. Here, the number of shift register stages of the delay circuit 6 or 26 required in the configuration of the present invention and the frequency of the sampling clock will be compared with the conventional example. Same conditions as the conventional example (fIF=10.7MHz, symbol rate=64k
bps), if L=10, the number of stages of the shift register according to the present invention is 10 stages, and the sampling clock frequency is 640 kHz, both of which are approximately 1/167th of the conventional ones.

[0009]

As described above in detail, by implementing the present invention, it is possible to drive with a clock frequency lower than that of conventional circuits, thereby reducing power consumption. Furthermore, since the number of stages of the shift register is smaller than in the conventional case, the circuit scale is reduced, which is extremely effective in practical use.

[Brief explanation of drawings]

FIG. 1 is a configuration example diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration example diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing a configuration example of a conventional delay detection circuit.

[Explanation of symbols]

1,21 D type flip-flop 2,22
Ring counter 3, 23 Phase comparator 4, 24 Encoder 5, 25 Register 6, 26, 31 Delay circuit 7, 27, 33, 34 Phase difference determination circuit 32 90
°phase shift circuit

Claims (2)

[Claims] 1. In order to receive a phase modulated signal in digital communication and obtain demodulated data, the received signal is converted to an intermediate frequency (IF) and binary shaped.
A D-type flip-flop outputs a signal with a frequency difference between the local oscillator frequency fL and the IF signal frequency fIF according to a sampling clock of the local oscillator frequency fL from a local oscillator, and a is a natural number) and operates on the rising or falling edge of the clock pulse.
a K-stage ring counter that generates and outputs a reference phase of the phase; a signal from the D-type flip-flop;
a phase comparator that compares the reference phases of the phases and outputs a phase comparison result; an encoder that detects the instantaneous phase of the carrier wave of the received signal from the phase comparison result and outputs phase information φ1; a register that temporarily holds the phase information φ1 and outputs the phase information φ1 according to a clock K times the frequency of the difference; a delay circuit that outputs 1-symbol delayed phase information φ2 that is obtained by delaying the phase information φ1 by 1 symbol; φ1 and the one-symbol delay phase information φ2
and a phase difference determination circuit that calculates a phase difference between the two signals and outputs the demodulated data corresponding to the phase difference. 2. The ring counter according to claim 1 operates at the rising edge of a rectangular wave pulse with a duty of 50% at a frequency K/2 times the frequency of the difference (K is a natural number), However, the first outer one-stage ring counter generates and outputs the reference phase (the outer 2 is the smallest integer greater than or equal to 2. The delay detection circuit according to claim 1, further comprising a second outer one-stage ring counter that outputs the signal. [Outside 1] [Outside 2]