JPH098795A - Frame synchronizing method and communication equipment - Google Patents

Abstract

PURPOSE: To establish synchronism in a short time by shifting detected digital code data for prescribed cycles N times and defining timing, with which the prescribed number of partition codes are detected on the same time base in those data, as frame synchronizing timing. CONSTITUTION: A frame synchronizing extraction part receives digital code data, to which the partition code showing the partition of data is added for each prescribed cycle, and when the partition code is detected in those data, a synchronizing pattern detect signal is outputted. A frame synchronizing protection part 3 shifts the synchronizing pattern detect signal for the prescribed cycles outputted from the frame synchronizing extraction part on the preceding stage N times while using a shift part 10 and at the timing with which the prescribed number of partition codes are detected on the same time base among the N pieces of shifted data, a synchronism build-up signal is outputted to a high-order layer. Therefore, even when a pseudo synchronizing pattern is contained in received data, the proper synchronizing pattern contained for each prescribed cycle can be surely detected without being missed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization method and a communication device, and more particularly to a frame synchronization method and a communication device for shortening the synchronization acquisition time.

[0002]

2. Description of the Related Art Conventionally, in the case of transmitting a digital code in digital communication, whether wired or wireless, the transmitting side transmits a delimiter code for each predetermined information unit (hereinafter, referred to as a frame) called a cell or a frame. Then
The receiving side performs demodulation processing by recognizing each frame while referring to the delimiter code.

FIG. 7 shows a frame structure of the secondary group interface (communication speed 6.312 Mbit / s). In this example, the period of one frame is 125 μs, and one frame has 98 time slots (1 (Time slot = 8 bits), followed by 5 bits of frame bits, for a total of 789 bits of data.

The interface speed of the secondary group interface is 6312 kbit / s, 6144 kbit / s excluding the 97th and 98th time slots and frame bits are used for user information transfer, and a 4-multiframe structure is provided. By taking the above, the synchronization pattern is composed of a total of 9 bits of the frame bits (4 bits) excluding the last bit of the first frame and the frame bits (5 bits) of the second frame.

8 to 10 are diagrams for explaining synchronization acquisition in a conventional receiving device, FIG. 8 is a block diagram showing a main configuration of the receiving device, and FIG. 9 is a frame shown in FIG. 8 is a timing chart of the synchronization protection unit, and FIG.
4 is a state transition diagram of the frame synchronization protection unit shown in FIG.

As shown in FIG. 8, the receiving device 1'includes a frame synchronization extraction unit 2, a frame synchronization protection unit 3, and an upper layer 4. The frame synchronization extraction unit 2
The received data is supplied to the upper layer 4 and a synchronization pattern detection signal is output to the frame synchronization protection unit 3. The frame synchronization protection unit 3 outputs the synchronization pattern detection signal output from the frame synchronization extraction unit 2 and , CRC
The synchronization protection operation is performed by detecting an error detection signal (in this case, whether to count or not is determined depending on whether or not the synchronization is established), and the upper layer 4
To the synchronization establishment signal.

Specifically, as shown in FIG. 10, the frame synchronization protection unit 3 starts from a hunting state,
It becomes the pre-synchronization state with one correct synchronization pattern. After that, if the correct synchronization pattern comes twice in a row, the synchronization is established (see FIG. 9) and the synchronization state is set. Here, during the previous synchronization state, even if the synchronization pattern or CRC
When an error is detected, it returns to the hunting state again. Also, in the synchronized state, the hunting state is again established when an incorrect synchronization pattern is detected seven times in succession or a CRC error is detected 32 times in succession. As described above, in the conventional synchronization acquisition, the synchronization acquisition processing is performed by transitioning the three states of the hunting state, the pre-synchronization state, and the synchronization state according to the determined processing procedure.

[0008]

However, the frame synchronization protection unit 3 in the conventional receiving apparatus 1'as described above is used.
In this case, however, if a pseudo sync pattern having the same pattern as the sync pattern in the payload exists in the received data, there is a problem that it takes a very long time to establish the sync for the reason described below.

Specifically, the state of the frame synchronization protection unit 3 will be described assuming that a synchronization pattern detection signal as shown in FIG. 11 is sent to the frame synchronization protection unit 3, for example. First, by detecting the pulse (1) indicating the pseudo sync pattern, the pre-synchronization state is established, and it is detected whether or not there is a sync pattern pulse one multiframe after the pseudo sync pattern pulse (1). Here, since the conventional frame synchronization protection unit 3 is configured so that the pulses (2) and (3) during one multiframe cannot be detected, in this case, there is no pulse after one multiframe. Therefore, hunting occurs.

Next, the pseudo sync pattern pulse (4) is detected to enter the pre-sync state, and it is further detected whether or not there is a pulse after one multiframe. In this manner, the correct sync pattern pulse (15) is finally detected to enter the pre-sync state, and the correct sync pattern pulses (18) and (20) are detected twice consecutively to enter the sync state. The synchronization establishment signal to the upper layer 5
Output to 3.

That is, from the detection of the sync pattern pulse including the pseudo sync pattern pulse for entering the pre-synchronization state, even if a correct sync pattern pulse exists during this one multi-frame, the hardware configuration makes sense. It could not be detected. In this example, the synchronization acquisition is attempted for 4 multiframes, but the synchronization cannot be acquired, and eventually, the correct synchronization pattern pulse is detected after 6 multiframes. However, in the conventional method,
In the worst case, it is theoretically possible that synchronization will not be established for an additional multiple of the number of bits in the multiframe.

[Object] The present invention has been made under such circumstances, and an object of the present invention is to provide a frame synchronization method and a communication device capable of realizing synchronization establishment in an extremely short time. It is in.

[0013]

A communication device of the present invention receives digital code data to which a delimiter code indicating a delimiter of data is added every predetermined period, and when a delimiter code is detected in the data, a synchronization pattern detection signal is received. And a synchronization pattern detection signal output from the frame synchronization extraction unit N times in a predetermined cycle, and a predetermined number of delimiter codes on the same time axis among the N shifted data. And a frame synchronization protection unit that outputs a synchronization establishment signal to an upper layer at the timing of detecting.

In this case, the frame synchronization protection unit shifts the synchronization pattern detection signal output from the frame synchronization extraction unit N times in a predetermined cycle to output N pieces of data in parallel, and among the N pieces of data, The synchronization establishment signal may be output to the upper layer using the timing at which a predetermined number of delimiter codes are detected on the same time axis as the frame synchronization timing.

[0015]

The frame synchronization method of the present invention receives digital code data to which a delimiter code indicating a delimiter of data is added every predetermined period, and the timing at which the delimiter code is detected N times consecutively within the predetermined period is detected. In the frame synchronization method of using the frame synchronization point, when a delimiter code is detected from the received digital code data, the digital code data is shifted by a predetermined period N times,
The timing at which a predetermined number of delimiter codes are detected on the same time axis among the shifted N pieces of data is extracted as the frame synchronization timing.

Further, when a delimiter code is detected from the received digital code data, the digital code data is shifted by a predetermined period N times to output N pieces of data in parallel, and this is output. The timing at which a predetermined number of delimiter codes are detected on the same time axis among the N pieces of data is extracted as the frame synchronization timing.

As a result, even if the received data contains a pseudo sync pattern, it is possible to reliably detect the correct sync pattern pulse included in each predetermined cycle without dropping it.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a frame synchronization protection unit of a communication device 1 to which the frame synchronization method of the present invention is applied. In FIG. 1, the same elements as those of the configuration of the conventional example of FIG.

As shown in FIG. 1, the communication device 1 of this embodiment.
Like the conventional example shown in FIG. 8, is composed of a frame synchronization extraction unit 2, a CRC error detection unit (not shown), a frame synchronization protection unit 3, and an upper layer 4. The frame synchronization extraction unit 2 supplies the received data to the upper layer and outputs a synchronization pattern detection signal to the frame synchronization protection unit 3, and the CRC error detection unit
CRC error is detected and CRC is applied to the frame synchronization protection unit 3.
It outputs an error detection signal.

As shown in FIG. 1, the frame synchronization protection unit 2 includes a shift unit 10, a CRC reset unit 11, a multi-frame counter 12, an error reset unit 13, a pulse detection unit 14, AND gates A1, A2, A3, RS. The flip-flop F1 is included, and the sync pattern detection signal output from the frame sync extraction unit 2 and the CRC
By detecting a CRC error detection signal or the like output from the error detection unit, a synchronization protection operation is performed and a synchronization establishment signal is output to the upper layer 4.

The shift unit 10 branches the sync pattern detection signal output from the preceding frame sync extraction unit 2 into three, the first of which is directly connected to the first input terminal of the 3-input AND gate A1. The second is to connect the signal shifted by one multi-frame via the RAM 21 to the second input end of the 3-input AND gate A1, and the third is to connect to the second input via the RAM 22.
A signal shifted by multiple frames is connected to the third input terminal of the 3-input AND gate A1. As a result, the AND gate A1 outputs "H" only when the signal in the current frame, the signal one multiframe before, and the signal two multiframes before become "H" at the same timing. The output end of the AND gate A1 is connected to one input end of the AND gate A2. The other input end of the AND gate A2 is connected to the output end of the RS flip-flop F1, and the output end of the AND gate A2 is connected to the set input end of the RS flip-flop F1.

The CRC reset section 11 outputs a reset signal to the AND gate A1 when it detects a CRC error flag from the CRC error detection section in the preceding stage, and the AND gate A1.
The output from 1 is stopped. The multi-frame counter 12 is for confirming the cycle of one multi-frame by counting the output pulse from the AND gate A2.
Is connected to the error reset section 13 and one input terminal of the AND gate A3. The AND gate A3 detects whether the synchronization pattern detection signal is always output at the timing of one multi-frame by inputting the synchronization pattern detection signal to the other input end, and the output end of the AND gate A3 has a pulse detection unit. It is connected to 14 input terminals.

The error reset unit 13 refers to the CRC error flag and the pulse counting one multi-frame to detect whether or not the CRC error has continued 32 times in one multi-frame. Here, if an error is detected, a reset signal is output to the reset terminal of the RS flip-flop F1 and the AND gate A1 in order to remove the synchronization, and the output of the synchronization signal is stopped.

The pulse detector 14 outputs a reset signal to the reset terminal of the RS flip-flop F1 and the AND gate A1 in the same manner as the error reset unit 13 when the synchronization pattern detection signal is not detected seven times in a row. Further, the reset signal is output even when the synchronization is lost irrespective of the state transition diagram such as an alarm or disconnection of input.

Next, the operation of the above embodiment will be described with reference to FIGS. 2 to 4 are diagrams for explaining an operation example of the present embodiment, FIG. 2 is a signal waveform diagram in the frame synchronization protection unit 3 of the present embodiment, and FIG. 3 is a frame synchronization of the present embodiment. It is a state transition diagram of a protection part. Since the frame synchronization extraction unit 2 outputs the synchronization pattern detection signal not only to the correct normal synchronization pattern but also to the pseudo synchronization pattern, the pseudo synchronization pattern is represented by a pulse waveform with diagonal lines in FIG. The two are distinguished from each other by showing the correct synchronization pattern by a pulse waveform without hatching.

In FIG. 2, (a) is a CRC error signal output from the CRC error detection section, and (b) is one pulse when the frame synchronization extraction section 2 detects a synchronization pattern in the received signal. The synchronization pattern detection signal is shown. (C) and (d) are signals obtained by shifting the synchronization pattern detection signal shown in (b) by one multiframe or two multiframes, and (c) is the RAM 21.
Output, and (d) is the output of the RAM 22. (E)
AND gate A which is the logical product of (b), (c) and (d)
1 output signal.

In this embodiment, as in the conventional example shown in FIG. 8, the synchronization establishment signal is generated when the synchronization pattern detection signal is generated continuously for 3 multiframes. As shown in FIG. 7, in the present embodiment, there is no pre-synchronization state, and if the synchronization pattern detection signal is detected continuously in three multiframes in the hunting state, the synchronization establishment signal is immediately generated without passing through the pre-synchronization state.

That is, in the present embodiment, as shown in FIG. 2, the synchronization establishment signal is output only when a pulse having a correct synchronization pattern which is generated continuously in three multiframes on the same time axis is detected. Therefore, the AND gate A2 outputs only the first one pulse of the output of the AND gate A1, and the RS flip-flop F1 outputs the pulse serving as a criterion for determining whether or not the synchronization is captured. Become.

FIG. 4 is a timing chart for explaining the effect of this embodiment. When the synchronization pattern detection signal as shown in FIG. 11 is detected, in the conventional example, it takes a long time to establish synchronization, but in the present embodiment, as shown in FIG. It is possible to establish synchronization in a short time by surely detecting the correct synchronization pattern pulse in the above.

In the above embodiment, the synchronization is established by using the synchronization pattern detection signal. However, the present invention is not limited to this example. For example, the frame data structure is as shown in FIG. It is also applicable to the one that puts a header on the head and follows the data. That is, the cell header includes a header error control field (1 octet),
The header error protection target header bits (4 octets). In general, cell synchronization is performed using the result of header error control, and the synchronization extraction unit inspects for each bit whether or not the header error control coding rule is applied to an area assumed to be a header.

When the present invention is applied to such a cell flow, a synchronization detection signal is generated once the result of the above inspection reaches a predetermined state. Therefore, this signal is used as the synchronization pattern detection signal in the above-described embodiment. 6 and by outputting it to the frame synchronization protection unit 3 (for example, even in the SDH-based interface), by using σ RAMs in the shift unit 10 shown in FIG. The synchronization can be captured according to the state transition diagram including the header error control pattern detection condition.

In this case, α = 7 and σ = 6 have been proposed as values for the SDH base interface, and α = 7 and σ = 8 as values for the cell base interface.

[0033]

According to the present invention, even if the received data includes a pseudo sync pattern, the correct sync pattern pulse included in each predetermined cycle can be detected without fail, so that it can be performed in a short time. Synchronization can be established.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a frame synchronization protection unit according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram in a frame synchronization protection unit according to an embodiment of the present invention.

FIG. 3 is a state transition diagram of a frame synchronization protection unit according to an embodiment of the present invention.

FIG. 4 is a timing chart for explaining an effect of one embodiment of the present invention.

FIG. 5 is a diagram showing frame data according to another embodiment of the present invention.

FIG. 6 is a state transition diagram of a frame synchronization protection unit according to another embodiment of the present invention.

FIG. 7 is a diagram showing a frame structure of a secondary group interface.

FIG. 8 is a block diagram showing a main configuration of a receiving device in a conventional example.

9 is a timing chart of the frame synchronization protection unit shown in FIG.

10 is a state transition diagram of the frame synchronization protection unit shown in FIG.

FIG. 11 is a timing chart for explaining problems in the conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 communication device 2 frame synchronization extraction unit 3 frame synchronization protection unit 4 upper layer 10 shift unit 11 CRC reset unit 12 multi-frame counter 13 error reset unit 14 pulse detection unit 21 RAM 22 RAM A1 to A3 AND gate F1 RS flip-flop

Claims (4)

[Claims] 1. A frame which receives digital code data to which a delimiter code indicating a delimiter of data is added at every predetermined cycle, and which has a timing at which the delimiter code is continuously detected N times within a predetermined cycle as a frame synchronization point. In the synchronization method, when a delimiter code is detected from the received digital code data, the digital code data is shifted by a predetermined period N times and a predetermined time is shifted from the N shifted data on the same time axis. A frame synchronization method, wherein a timing at which a number delimiter code is detected is extracted as a frame synchronization timing. 2. A frame in which digital code data to which a delimiter code indicating a delimiter of data is added at every predetermined cycle is received, and a timing at which the delimiter code is detected N times consecutively within a predetermined cycle is set as a frame synchronization point. In the synchronizing method, when a delimiter code is detected from the received digital code data, the digital code data is shifted by a predetermined period N times to output N pieces of data in parallel, and the output N A frame synchronization method characterized in that the timing at which a predetermined number of delimiter codes are detected on the same time axis among the pieces of data is extracted as frame synchronization timing. 3. A frame synchronization extraction unit that receives digital code data to which a delimiter code indicating a delimiter of data is added at every predetermined cycle, and outputs a synchronization pattern detection signal when the delimiter code is detected in the data, said frame The synchronization pattern detection signal output from the synchronization extraction unit is shifted N times in a predetermined cycle, and a synchronization establishment signal is sent to the upper layer at a timing when a predetermined number of delimiter codes are detected on the same time axis among the N shifted data. And a frame synchronization protection unit that outputs 4. A frame synchronization extraction unit that receives digital code data to which a delimiter code indicating a delimiter of data is added at every predetermined cycle, and outputs a synchronization pattern detection signal when a delimiter code is detected in the data, said frame Timing at which the synchronization pattern detection signal output from the synchronization extraction unit is shifted N times in a predetermined cycle to output N pieces of data in parallel, and a predetermined number of delimiter codes are detected on the same time axis among the N pieces of data. And a frame synchronization protection unit that outputs a synchronization establishment signal to an upper layer using the frame synchronization timing as a frame synchronization timing.