JPH08204693A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE: To maintain a normal synchronization state by restoring the frame synchronization earlier when the frame synchronization is established by FAS and multi-frame synchronization is established by chance. CONSTITUTION: A guard timer 5 takes guard for T seconds to a multi-frame synchronization alarm 16 from a multi-frame synchronization detection circuit 4 and provides an output of a multi-frame alarm pulse 17. A FASB detection circuit 6 monitors a FASB in input data 11 and when the FASB differs when frame synchronization is established, it is discriminated to be synchronization establishment by pseudo synchronization and a FASB detection pulse 18 of L level is outputted. A forced hunting clock inhibit circuit 7 inhibits a frame synchronization detection block 19 to the frame synchronization detection circuit 2 by one clock when the FASB detection pulse 18 is at L level and the multi- frame alarm pulse 17 is at H.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit, and more particularly to a PCM (Pulse Code Module).
The present invention relates to a frame synchronization circuit in digital communication.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 4, a frame synchronizing circuit of this type has a clock (CLK) extracting tank circuit 1
A frame sync detection circuit 2, an elastic store memory 3, and a multi-frame sync detection circuit 4.

The clock extraction tank circuit 1 extracts a clock component from input data 11 (2.048 Mbps PCM digital data) of a transmission line (not shown) and outputs a transmission line extraction clock 12. Further, the clock extraction tank circuit 1 maintains the transmission path extraction clock 12 by the previously extracted clock component even when the transmission path clock is cut off.

Here, the input data 11 is composed of 16 multi-frames (4096 bits) as shown in FIG. 5, and the bit length of each frame is 256 bits. Further, FAS (Frame Alignment Signal) that is a specific bit pattern is included in one frame.
l; "10011011"), or FASB [Fra
me Alignment Signal Ber;
"******" (* indicates indefinite)] and a MFS [Multi FrameSi].
gnal; “0000 ****” (* indicates indefinite)]
And a multi-frame synchronization signal. Incidentally, M
The FS is added only to the 0th frame.

The frame sync detection circuit 2 is based on the transmission path extraction clock 12 from the clock extraction tank circuit 1 and is a frame sync signal of the input data 11, that is, FAS and FAS.
B Each match is detected and frame synchronization is established. When the frame synchronization is not established, the frame synchronization detection circuit 2
Outputs the frame synchronization alarm 15.

Input data 11 is written to the elastic store memory 3 based on the transmission path extraction clock 12 from the clock extraction tank circuit 1, and the content is output as output data 13 in response to the internal clock 14. It

The multi-frame sync detection circuit 4 uses the internal clock 14 to output the multi-frame sync signal of the output data 13 from the elastic store memory 3, that is, MF.
A match of S is detected and multiframe synchronization is established.
When the multiframe synchronization is not established, the multiframe synchronization detection circuit 4 outputs the multiframe synchronization alarm 16.

In the frame synchronization circuit described above, at the time of synchronous pull-in hunting from the asynchronous state to the synchronous state, first, it is detected that the frame synchronization signals match FAS, FASM, FAS in this order, and frame synchronization is established. After that, matching of MFS which is a multi-frame synchronization signal is detected, and synchronization of 16 multi-frames is established. Further, after the synchronization is established, the frame synchronization re-hunting is performed by monitoring only the established state of the frame synchronization by FAS detection.

[0009]

In the above-described conventional frame synchronization circuit, in the case of a line having a high bit error rate such as fading which may cause fading, the data bit in the frame and the frame synchronization are synchronized at the time of synchronization pull-in. The bit patterns of the signals FAS and FASB may coincide with each other, resulting in false synchronization.

In this case, since only the establishment state of the frame synchronization by FAS is monitored after the synchronization is established, if the multi-frame synchronization is accidentally established when the frame synchronization by FAS is established due to the incorrect synchronization, the frame synchronization is established. There is no means for recovering, and once it falls into that state, it becomes difficult to recover the frame synchronization other than taking measures such as artificially disconnecting the line.

Therefore, an object of the present invention is to solve the above-mentioned problems, and to promptly perform frame synchronization recovery even when multi-frame synchronization is accidentally established when frame synchronization by FAS is established by erroneous synchronization. An object of the present invention is to provide a frame synchronization circuit capable of maintaining a normal synchronization state.

[0012]

A frame synchronization circuit according to the present invention detects a frame synchronization based on first and second frame synchronization signals which are alternately set for each frame data of multi-frame data. Frame synchronization detection means and multi-frame synchronization detection means for detecting multi-frame synchronization based on a multi-frame synchronization signal set in the multi-frame data, each of the frame synchronization detection means and the multi-frame synchronization detection means A frame synchronization circuit for establishing frame synchronization of the multi-frame data based on a detection result of the second frame synchronization detection means for detecting the frame synchronization based on the second frame synchronization signal; When out-of-sync is detected by each of the frame synchronization detection means 2 and the multi-frame synchronization detection means And means for forcibly outputting an alarm signal indicating an out-of-synchronization from the first frame synchronization detection means.

Another frame synchronization circuit according to the present invention comprises, in addition to the above configuration, means for maintaining the detection result of the multi-frame synchronization detection means for a predetermined time when out-of-sync is detected by the multi-frame synchronization detection means. It has.

Another frame synchronization circuit according to the present invention is an extraction means for extracting a transmission path clock from each frame data of multi-frame data, and first and second frame synchronization signals alternately set to each frame data. And first frame synchronization detecting means for detecting frame synchronization based on the transmission path clock extracted by the extracting means, and multiframe synchronization detection based on a multiframe synchronization signal set in the multiframe data. A frame synchronization circuit that establishes frame synchronization of the multi-frame data based on detection results of the frame synchronization detection means and the multi-frame synchronization detection means. Second frame synchronization detecting means for detecting the frame synchronization based on the frame synchronization signal of , The second frame synchronization detecting means detects the out-of-sync of the second frame synchronization signal and the multi-frame synchronization detecting means detects the out-of-sync of the multi-frame synchronization. No. 1 to the frame synchronization detecting means is temporarily suppressed.

In addition to the above configuration, the frame synchronization circuit according to the present invention further comprises means for maintaining the detection result of the multiframe synchronization detection means for a predetermined time when the multiframe synchronization detection means detects out-of-sync. It is equipped with.

[0016]

A guard timer, a FASB detection circuit, and a forced hunting clock inhibit circuit are added to the conventional frame synchronization circuit to monitor only FASB separately from the frame synchronization detection, and the multiframe synchronization detection circuit is out of multiframe synchronization. An alarm is output, and when the FASB detection circuit detects a FASB difference, the frame synchronization detection circuit is forced to output a frame synchronization alarm.

As a result, even if the multi-frame synchronization is accidentally established when the frame synchronization by FAS is established by erroneous synchronization, the pseudo synchronization is quickly escaped.
And the normal synchronization state can be maintained.

[0018]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a frame synchronization circuit according to an embodiment of the present invention is a clock (CLK) extraction tank circuit 1
A frame sync detection circuit 2, an elastic store memory 3, a multi-frame sync detection circuit 4, a guard timer 5, a FASB detection circuit 6, and a forced hunting clock inhibit circuit 7. .

The clock extraction tank circuit 1 extracts a clock component from input data 11 (2.048 Mbps PCM digital data) of a transmission line (not shown) and outputs a transmission line extraction clock 12. Further, the clock extraction tank circuit 1 maintains the transmission path extraction clock 12 by the previously extracted clock component even when the transmission path clock is cut off.

The frame synchronization detection circuit 2 detects a frame synchronization signal of the input data 11, that is, a match between FAS and FASB on the basis of the frame synchronization detection clock 19 generated by the forced hunting clock inhibit circuit 7, and the frame synchronization is detected. Establish. When the frame synchronization is not established, the frame synchronization detection circuit 2 outputs the frame synchronization alarm 15.

Input data 11 is written in the elastic store memory 3 based on the transmission path extraction clock 12 from the clock extraction tank circuit 1, and the content is output as output data 13 in response to the in-apparatus clock 14. It

The multi-frame sync detection circuit 4 uses the internal clock 14 to output the multi-frame sync signal of the output data 13 from the elastic store memory 3, that is, MF.
A match of S is detected and multiframe synchronization is established.
When multi-frame synchronization is not established, the multi-frame synchronization detection circuit 4 outputs the multi-frame synchronization alarm 16, and when the frame synchronization detection circuit 2 outputs the frame synchronization alarm 15, the output of the multi-frame synchronization alarm 16 is reset. .

The guard timer 5 guards the multi-frame synchronization alarm 16 from the multi-frame synchronization detection circuit 4 for a preset T seconds based on the internal clock 14 and forcibly hunts as a multi-frame alarm pulse 17. Output to the clock inhibit circuit 7.

The FASB detection circuit 6 generates a timing pulse matching FASB in the input data 11 to generate FAS.
B is monitored and FASB is set when frame synchronization is established.
If it is different, it is determined that the synchronization is established by pseudo synchronization,
The FAS detection pulse 18 of "L" is output to the forced hunting clock inhibit circuit 7.

Further, the FASB detection circuit 6 judges that the FASB detection is normal when the FASBs match when the frame synchronization is established, and the FASB detection pulse 18 of "H" is sent to the forced hunting clock inhibit circuit 7. Output.

The forced hunting clock inhibit circuit 7 normally generates a frame synchronization detection clock 19 based on the transmission path extraction clock 12 extracted by the clock extraction tank circuit 1 and outputs it to the frame synchronization detection circuit 2.

In the forced hunting clock inhibit circuit 7, when the FASB detection pulse 18 is "L" and the multi-frame alarm pulse 17 is "H", the frame synchronization detection clock 19 to the frame synchronization detection circuit 2 is 1 clock. However, the frame sync detection circuit 2 is forced to output the frame sync alarm 15.

In the frame synchronization circuit described above, at the time of synchronous pull-in hunting from an asynchronous state to a synchronous state, first, it is detected that the frame synchronization signals match FAS, FASM, FAS in this order, and frame synchronization is established. After that, matching of MFS which is a multi-frame synchronization signal is detected, and synchronization of 16 multi-frames is established. Further, after the synchronization is established, the state of establishment of the frame synchronization by FAS detection and the FASB only are monitored to perform the frame synchronization re-hunting.

FIG. 2 is a timing chart showing the FASB detection operation according to the embodiment of the present invention, and FIG. 3 is a timing chart showing the clock inhibit operation according to the embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS.

Input data 11 from the transmission line is input to the clock extraction tank circuit 1, and also to the frame synchronization detection circuit 2, elastic store memory 3 and FASB detection circuit 6, respectively.

The FASB detection circuit 6 generates a timing pulse matching FASB in the input data 11 to generate FAS.
B is monitored and FASB is set when frame synchronization is established.
If it is different, it is determined that the synchronization is established by pseudo synchronization,
The FAS detection pulse 18 of "L" is output to the forced hunting clock inhibit circuit 7.

Further, the FASB detection circuit 6 judges that the FASB detection is normal when the FASBs match when the frame synchronization is established, and the FASB detection pulse 18 of "H" is sent to the forced hunting clock inhibit circuit 7. Output.

The elastic store memory 3 is a transmission path extraction clock 12 extracted by the clock extraction tank circuit 1.
And the internal device clock 14 are input, and the input data 11 is transferred to the phase of the internal device clock 14.

At this time, the elastic store memory 3
Even if the transmission line clock is lost due to line disconnection, etc., the previously written data is read by the in-device clock 14, so that the output data 13 is output to the outside and multi-frame synchronization is established for establishing multi-frame synchronization. It is output to the frame synchronization detection circuit 4, and 16 multiframe synchronization detection is performed in the multiframe synchronization detection circuit 4.

In this case, when multi-frame out-of-sync occurs, this multi-frame out-of-sync is detected by the multi-frame sync detection circuit 4, and the multi-frame out-of-sync alarm 16 is output from the multi-frame sync detection circuit 4.
Is output.

The multi-frame out-of-sync alarm 16 is input to the guard timer 5, and after being guarded for a preset T seconds by the guard timer 5, it is output to the clock hunting circuit 7 for forced hunting as a multi-frame alarm pulse 17. It

In the forced hunting clock inhibit circuit 7, when the FASB detection pulse 18 is "L" and the multi-frame alarm pulse 17 is "H", the frame synchronization detection clock 19 input to the frame synchronization detection circuit 2 is 1 Only the clock is inhibited, and the frame sync alarm circuit 15 is forced to output the frame sync alarm 15.

When the frame sync detection circuit 2 outputs the frame sync alarm 15, the multiframe sync detection circuit 4 resets the output of the multiframe out-of-sync alarm 16. Therefore, in the frame synchronization circuit, synchronization re-hunting is performed by a circuit (not shown), so that normal synchronization is established.

As described above, the guard timer 5, the FASB detection circuit 6, and the forced hunting clock inhibit circuit 7 are added to the conventional frame synchronization circuit, and only the FASB is monitored separately from the frame synchronization detection, and the multi-frame synchronization is performed. Detection circuit 4 multi-frame out-of-sync alarm 1
6 is output, and when the FASB detection circuit 6 detects the difference in FASB, the frame synchronization detection circuit 2 is forced to output the frame synchronization alarm 15, so that when the frame synchronization by FAS is established due to erroneous synchronization. Even if multi-frame synchronization is accidentally established, it is possible to quickly exit pseudo synchronization and maintain a normal synchronization state.

[0041]

As described above, according to the present invention, the first frame for detecting frame synchronization based on the first and second frame synchronization signals which are alternately set in each frame data of multi-frame data. Sync detection means and multi-frame synchronization detection means for detecting multi-frame synchronization based on the multi-frame synchronization signal set in the multi-frame data, the detection results of the frame synchronization detection means and the multi-frame synchronization detection means respectively. In the frame synchronization circuit that establishes the frame synchronization of the multi-frame data based on the second frame synchronization detection means and the multi-frame synchronization detection means that detect the frame synchronization based on the second frame synchronization signal, the out-of-sync is detected. When this happens, the first frame sync detection means forcibly outputs an alarm signal indicating out-of-sync. By doing so, even when multi-frame synchronization is accidentally established when the frame synchronization by FAS is established by erroneous synchronization, the frame synchronization can be restored early and the normal synchronization state can be maintained. effective.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing a FASB detection operation according to an embodiment of the present invention.

FIG. 3 is a timing chart showing a clock inhibit operation according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional example.

FIG. 5 is a diagram showing a frame format of 2.048 Mbps PCM digital data.

[Explanation of symbols]

 1 Clock extraction tank circuit 2 Frame synchronization detection circuit 3 Elastic store memory 4 Multi frame synchronization detection circuit 5 Guard timer 6 FASB detection circuit 7 Forced hunting clock inhibit circuit 11 Input data 12 Transmission path extraction clock 15 Frame synchronization alarm 16 Multi frame Out-of-sync alarm 17 Multi-frame alarm pulse 18 FASB detection pulse 19 Frame sync detection clock

Claims (4)

[Claims] 1. A first frame synchronization detecting means for detecting frame synchronization based on first and second frame synchronization signals which are alternately set for each frame data of the multi-frame data, and the multi-frame data. A multi-frame synchronization detecting means for detecting multi-frame synchronization based on the generated multi-frame synchronization signal, and the frame of the multi-frame data based on the detection result of each of the frame synchronization detecting means and the multi-frame synchronization detecting means. A frame synchronization circuit for establishing synchronization, the second frame synchronization detection means detecting the frame synchronization based on the second frame synchronization signal, the second frame synchronization detection means and the multi-frame synchronization detection. When out-of-sync is detected by each means, the first out-of-sync detection means indicates the out-of-sync. A frame synchronization circuit having means for forcibly outputting an alarm signal. 2. The frame synchronization circuit according to claim 1, further comprising means for maintaining a detection result of the multi-frame synchronization detection means for a predetermined time when out-of-sync is detected by the multi-frame synchronization detection means. 3. Extraction means for extracting a transmission path clock from each frame data of multi-frame data, first and second frame synchronization signals alternately set for each frame data, and said extraction means. A first frame synchronization detecting means for detecting frame synchronization based on the transmission path clock; and a multiframe synchronization detecting means for detecting multiframe synchronization based on a multiframe synchronization signal set in the multiframe data. A frame synchronization circuit for establishing frame synchronization of the multi-frame data based on the detection results of the frame synchronization detection means and the multi-frame synchronization detection means, wherein the frame synchronization circuit includes: A second frame synchronization detecting means for detecting frame synchronization, and the second frame synchronization detecting means. Supply of the transmission path clock to the first frame synchronization detecting means when the synchronization loss of the second frame synchronization signal is detected and the multiframe synchronization detecting means detects the synchronization loss of the multiframe synchronization. A frame synchronization circuit having means for temporarily suppressing. 4. The frame synchronization circuit according to claim 3, further comprising means for maintaining a detection result of said multiframe synchronization detection means for a predetermined time when out of synchronization is detected by said multiframe synchronization detection means.