JPH01253335A - Multi-frame synchronism inspecting method - Google Patents

Abstract

PURPOSE:To improve the reliability for inspection of the multi-frame synchronism by detecting and storing successively the synchronizing bits in each frame and checking whether a bit pattern equal to the prescribed number of stored frames is normal or not in the synchronism inspection timing set every prescribed number of frames. CONSTITUTION:An FA counter circuit 205 is count-loaded by '1' of a received FA signal and counts the subsequent five frames. An FA synchronism detecting signal is equal to '1' if the FA signal is equal to '1' in the three continuous gate timings. While the FA synchronism detecting signal is equal to '0' in case the step-out is caused by some reason and the FA signal is equal to '0' in the two continuous gate timings. An FA synchronism protecting circuit 206 can work when the frame synchronism is set up; while an M synchronism protecting circuit 208 can work when the FA synchronism is set up. Thus the M synchronism inspection is started to set up the M synchronism. Then the multi-frame synchronism is set up.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-frame synchronization verification method in I5DN.

[Prior art] Regarding the multiframe structure in l5DN, CC
It is in ITT Recommendation ■430.

FIG. 2 is a diagram showing an overview of the multiframe structure and Q-bit identification. In FIG. 0, a network terminal equipment (NT) sends a multiframe to a terminal equipment (TE). Each frame contains an FA bit and an M bit for frame synchronization, the FA bit has a content of 1" every 5 frames, and the M bit has a content of 1" every 20 frames. Bit = 1 identifies the first frame of a multiframe, and while synchronization is established, frames with FA bit = 1 identify NT.
Send Qn bits to Also, while out of sync “
To obtain and maintain this synchronization, the TE needs to perform M synchronization (synchronization of M bit = 1 and FA bit = 1) and FA synchronization (FA bit = 1).

[Problems to be Solved by the Invention] However, no effective method for this type of synchronization test has been shown in the past. This synchronization test is important,
If communication continues without being able to detect not only the presence or absence of synchronization but also any abnormality, there is a risk that a serious secondary failure of information will occur.

The present invention has been made in view of the background of the prior art described above, and its purpose is to propose a multiframe synchronization verification method that can perform multiframe synchronization verification with high reliability.

[Means for Solving the Problems] In order to achieve the above object, the multi-frame synchronization verification method of the present invention detects synchronization bits in each frame and sequentially stores the contents, The outline of the synchronization test is to check whether or not the stored bit patterns of the predetermined number of frames are normal at the timing of the synchronization test.

[Description of Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[First embodiment] In the first embodiment, the FA bit “1゛° and the M bit “
Multi-frame synchronization verification is performed with a simple configuration by checking 1".

FIG. 1 is a diagram showing a multi-frame synchronization verification circuit of the first embodiment. In the figure, a frame synchronization detection circuit 204 receives a frame signal, performs synchronization detection for the frame, and outputs a frame synchronization detection signal indicating the presence or absence of frame synchronization. 205 is an FA counter circuit, which outputs a gate signal a (=1) by counting 5 frames after inputting each received FA signal=1. 206 is an FA synchronization protection circuit, and gate signal a=1
The contents of the received FA signal are taken into the internal shift register at the timing of . When the content of the received received FA signal is "1" three times in a row, it is determined that the FA synchronization is established, and when it is "0" twice in a row, it is determined that the FA synchronization is out of synchronization. Outputs an FA synchronization detection signal indicating this.

This synchronous/asynchronous determination method takes into consideration erroneous reception of FA bits due to noise or the like.

207 is an M counter circuit, which outputs a gate signal b (=1) by counting 20 frames after receiving the received FA signal=1 and the received M signal=1 at the same time. Reference numeral 208 denotes an M synchronization protection circuit, which takes in the contents of the received M signal into an internal shift register at the timing of gate signal b=1. Then, the content of the received received M signal is 3
When it is "1" twice in a row, it is determined that the M synchronization is established, and when it is "o" twice in a row, it is determined that the M synchronization is out, and an M synchronization detection signal to that effect is output.

Further, a negative signal of the frame synchronization detection signal is led to the FA synchronization protection circuit 206. This enables the operation of the FA synchronization protection circuit 206 when frame synchronization is achieved, and resets the FA synchronization protection circuit 206 when frame synchronization is lost. Further, each negative signal of the frame synchronization detection signal and the FA synchronization detection signal is led to the M synchronization protection circuit 208. As a result, the M synchronization protection circuit 208 is enabled when frame synchronization and FA synchronization are established, and the M synchronization protection circuit 208 is reset when frame synchronization or FA synchronization is lost.

FIG. 3 is a timing chart of the received FA signal and the received M signal in the first embodiment. In the figure, a frame signal is received from the line side.

There are an FA bit and an M bit at predetermined positions in one frame signal. The received FA signal is a signal that is set when the FA bit=1 and reset when the FA bit=O. Receive M
The signal is a signal that is set when M bit=1 and reset when M bit=0.

FIG. 4 is a timing chart illustrating the operation of establishing FA synchronization in the first embodiment. It is assumed that frame synchronization is achieved. In state 1, FA counter circuit 2
05 is count-loaded (reset) by l'' of the received FA signal, and the 1st, 2nd, and 3rd gate signals a shown in the figure are generated by counting the subsequent 5 frames.Reception is performed at these three consecutive gate timings. If the FA signal is "1", the FA synchronization detection signal becomes "1" in state 2. Also, if the synchronization is lost for some reason, the received FA signal becomes "1" at two consecutive gate timings.
0”, the FA synchronization detection signal becomes “O” in state 3.

Note that the M synchronization test is performed in the same manner as above by setting the count number to 20.

FIG. 5 is a diagram showing the mutual relationship between frame synchronization, FA synchronization, and M synchronization in the first embodiment. In the figure, in state 1, frame synchronization is established.

This enables the FA synchronization protection circuit 206 to operate and starts the FA synchronization verification. In state 2, FA synchronization is established. This enables the M synchronization protection circuit 208 to operate, and the M synchronization verification is started. In state 3, M synchronization is established. This completes the establishment of multiframe synchronization. In state 4, frame synchronization is lost for some reason, so F
The A synchronization protection circuit 206 and the M synchronization protection circuit 208 are reset, and FA synchronization and M synchronization are removed.

In state 5, FA synchronization is lost for some reason, so M synchronization is lost. In this case, all you have to do is redo FA synchronization and M synchronization. Further, in state 6, only M synchronization is out of order for some reason. In this case, all you have to do is perform M synchronization again.

[Second Embodiment] In the second embodiment, a strict multi-frame synchronization test is performed by inspecting the FA bit pattern of a plurality of consecutive frames and the M bit pattern of a plurality of consecutive frames.

FIG. 6 is a block diagram of a multi-frame synchronization verification circuit according to the second embodiment. Note that components equivalent to those in FIG. 1 are given the same numbers and their explanations will be omitted. In the figure, reference numeral 112 denotes an FA synchronization pattern verification circuit, which accumulates the contents of the received FA signal for five consecutive frames and examines the pattern.

113 is an M synchronization pattern verification circuit, and 20 consecutive
The contents of one frame's worth of received M signals are accumulated and their patterns are inspected.

FIG. 7(A) is a circuit diagram showing details of the FA synchronization pattern verification circuit 112 of the second embodiment.

In the figure, 112-1 is a five-stage shift register;
2-2 is an AN with 4 inverters, 112-3 is a 5-person AN
This is the D gate. The received FA signal for each frame is sequentially shifted into the shift register 112-1 &::. In this way, the output FA synchronization pattern detection signal C has the contents of the shift register 112-1 (7) starting from the oldest [1, O, O, O,
When it is Ol, it becomes "l".

FIG. 7(B) shows the M synchronization pattern verification circuit 1 of the second embodiment.
In Figure 0, which is a circuit diagram showing details of 113-
1 is a 20-stage shift register, 113-2 is a 19-inverter, and 113-3 is a 20-manpower AND gate. The received M signal for each frame is transferred to the shift register 113-1.
Shift in sequentially. In this way, the output M synchronization pattern detection signal d becomes "1" when the contents of the shift register 113-1 are [1, O, O, O, . . . , 0] from the oldest one.

FIG. 8 is a timing chart explaining the FA synchronization verification operation of the second embodiment. In the figure, received FA signal = 1
When the FA counter circuit 205 receives the count load (
reset).

The FA counter circuit 205 outputs 0.1, 2, 3.4, etc. according to the subsequent frame signals. O (load).

1.2,3,4. ... and count. Count value =
4 is the timing of signal a=1. The FA synchronization pattern verification circuit 112 outputs a signal c=1 when the contents of the shift register 112-1 are [1, O, O, O, Ol. As a result, if FA synchronization is established, the FA synchronization protection circuit 206 accumulates the first (a=1*c=1). In this way, if this synchronized state continues, the second and third
(a=1*c=1) is accumulated. FA synchronization protection circuit 2
06 determines that FA synchronization is established when the third consecutive (a = 1 * e = 1) is accumulated, and the FA synchronization detection signal is "1".
Then, as long as this synchronization state continues, the FA synchronization detection signal "1" is output.

Further, if for some reason the FA synchronization pattern [1, O, O, O, Ol] cannot be detected at the timing of signal a=1, signal C=O. The FA synchronization protection circuit 206 is the first (
a=1*c=o). This is the case when synchronization is lost or when synchronization is achieved but the FA bit specified in the ISDN multiframe is not received. However, in the first case (a=1*c=o), it is not determined that synchronization has been lost. This is to prevent malfunctions due to noise.

However, if this asynchronous state continues, the second (a
=1*c=o). When the FA synchronization protection circuit 206 accumulates the second continuous signal (a=1*c=O), it determines that the FA synchronization has been lost, and outputs "0" as the FA synchronization detection signal.

Note that the same applies to the M synchronization verification operation, except that the signal a=1 at a count value of 19.

[Effects of the Invention] As described above, according to the present invention, stricter synchronization verification can be performed, not only out-of-synchronization but also abnormalities in the transmission system can be detected, and serious secondary failures of information can be prevented.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the multi-frame synchronization verification circuit of the first embodiment, Fig. 2 is a diagram showing an overview of the multi-frame structure and Q-bit identification, and Fig. 3 is a diagram showing the received FA signal and reception of the first embodiment. A timing chart of the M signal; FIG. 4 is a timing chart explaining the operation of establishing FA synchronization in the first embodiment; FIG. 5 is a diagram showing the interrelationship between frame synchronization, FA synchronization, and M synchronization in the first embodiment; FIG. 6 is a block diagram of the multi-frame synchronization verification circuit of the second embodiment, FIG. 7(A) is a circuit diagram showing details of the FA synchronization pattern verification circuit 112 of the second embodiment, and FIG. 7(B) is the M synchronization pattern verification circuit 1 of the second embodiment.
FIG. 8 is a timing chart explaining the FA synchronization verification operation of the second embodiment. In the figure, 204... frame synchronization detection circuit, 205...
・FA counter circuit, 112...FA synchronization pattern verification circuit, 206...FA synchronization protection circuit, 207...
M counter circuit, 113...M synchronization pattern verification circuit, 208...M synchronization protection circuit.

Claims (1)

[Claims] In a multi-frame frame synchronization verification method in ISDN, synchronization bits in each frame are detected and their contents are sequentially stored, and at the timing of synchronization verification every predetermined number of frames, the stored predetermined A multi-frame synchronization verification method characterized by testing whether or not bit patterns for a number of frames are normal.