JPH0955514A - Thin film semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: C-MO having impurities implanted in a channel region
When manufacturing an S thin film transistor, the number of manufacturing steps is reduced. As shown in FIG. 2C, by performing impurity implantation three times using dedicated impurity implantation masks, an n-type low impurity concentration region is formed on both sides of a channel region of a n-MOS thin film transistor. Source consisting of
A drain region 15b is formed on both sides of which a source / drain region 15c is formed of an n-type impurity high concentration region, and p
Both sides of the channel region 16a of the -MOS thin film transistor are used as the source / drain regions 16b formed of the p-type impurity high concentration region. Next, as shown in FIG. 2 (D), p-type impurities are implanted into the entire polycrystalline silicon thin film 32 at a low concentration, but in this case, the impurity implantation mask is not used at all.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device capable of reducing a leak current and a manufacturing method thereof.

[0002]

2. Description of the Related Art C-MOS, which is one of thin film semiconductor devices
In the thin film transistor, as shown in FIG.
The gate electrodes of the thin film transistor 1 and the n-MOS thin film transistor 2 are connected to the input terminal 3, the drain electrodes of the p-MOS thin film transistor 1 and the n-MOS thin film transistor 2 are connected to the output terminal 4, and the source of the p-MOS thin film transistor 1 is connected. Connect the electrodes to the power supply terminal 5 and
The structure is such that the source electrode of the S thin film transistor 2 is connected to the ground terminal 6. The power consumption of this C-MOS thin film transistor is dynamic power consumption (f · C · Vdd ² ) and static when the operating frequency is f, the load capacitance is C, the power supply voltage is Vdd, and the leakage current is IL. Power consumption (IL
It is represented by the sum of Vdd).

By the way, in a thin film transistor having a general structure using a polycrystalline silicon thin film as a semiconductor thin film,
Since the influence of leak current and the like via the trap levels unevenly distributed in the grain boundaries of the polycrystalline silicon thin film is large, C-MO
It is no exaggeration to say that the power consumption of the entire S thin film transistor is almost determined by the static power consumption. Therefore,
In order to reduce the leak current of the thin film transistor, by implanting impurities of a conductivity type different from the impurities contained in the source / drain regions into the channel region at a low concentration,
There is a device in which the threshold voltage is adjusted.

[0004]

However, p-M
Since the impurities injected into the channel region are different between the OS thin film transistor and the n-MOS thin film transistor, the impurities are injected into the respective channel regions separately by using the exclusive impurity injection masks (photoresist), and therefore, the manufacturing is performed. There was a problem that the number of steps would increase. An object of the present invention is to reduce the number of manufacturing steps.

[0005]

A thin film semiconductor device according to a first aspect of the present invention comprises an n-MOS thin film transistor and a p-type thin film transistor.
In a thin film semiconductor device having a -MOS thin film transistor, an n-MOS thin film transistor and a p-MOS thin film semiconductor device are provided.
It is characterized in that substantially the same amount of p-type impurities is diffused in each channel region of the thin film transistor. A thin film semiconductor device according to a second aspect of the present invention is the thin film semiconductor device according to the first aspect, wherein the n-MOS thin film transistor has a substantially intrinsic channel region interposed between n-type source / drain regions. It is characterized in that the p-type impurity is diffused after the diffusion more than before the diffusion, in an amount closer to the true nature. A thin film semiconductor device according to a third aspect of the present invention is the thin film semiconductor device according to the first or second aspect of the invention, wherein the n-MOS thin film transistor and the p-type
A C-MOS thin film transistor is constituted by a MOS thin film transistor.
According to a fourth aspect of the present invention, there is provided a method of manufacturing a thin film semiconductor device, wherein a p-type impurity is implanted into the entire semiconductor thin film of the n-MOS thin film transistor and the entire semiconductor thin film of the p-MOS thin film transistor, thereby forming an n-MOS thin film transistor and a p-type thin film transistor. A p-type impurity of substantially the same amount is implanted into each channel region of the MOS thin film transistor. A method of manufacturing a thin film semiconductor device according to a fifth aspect of the present invention is the method according to the fourth aspect, wherein the n
In a MOS thin film transistor, p-type impurities are implanted into an n-type source / drain region and a substantially intrinsic channel region interposed therebetween in an amount such that the channel region is closer to the intrinsic state after the diffusion than before the diffusion. It is characterized by. A method of manufacturing a thin film semiconductor device according to a sixth aspect of the present invention is characterized in that, in the fourth or fifth aspect of the invention, a C-MOS thin film transistor is formed by an n-MOS thin film transistor and a p-MOS thin film transistor. Is.

According to the thin film semiconductor device and the method of manufacturing a thin film semiconductor device according to the first and fourth aspects, the threshold values of the n-MOS thin film transistor and the p-MOS thin film transistor are used without using the impurity implantation mask or using only one of them. Since the voltage can be adjusted, the number of manufacturing steps can be reduced.

[0007]

FIG. 1 shows a C-MOS thin film transistor according to an embodiment of the present invention.
In this C-MOS thin film transistor, an n-MOS thin film transistor 12 and a p-MOS thin film transistor 13 are provided at predetermined positions on the upper surface of an insulating substrate 11 made of glass or the like. Each of the thin film transistors 12 and 13 includes semiconductor thin films 15 and 16 formed at predetermined locations on the upper surface of the base layer 14 made of silicon oxide and provided on the upper surface of the insulating substrate 11. The semiconductor thin film 15 of the n-MOS thin film transistor 12 has a central region as a channel region 15a, both sides thereof as a source / drain region 15b composed of an n-type impurity low concentration region, and both sides thereof from an n-type impurity high concentration region. The source / drain region 15c has a structure. The semiconductor thin film 16 of the p-MOS thin film transistor 13 has a structure in which a central portion is a channel region 16a and both sides thereof are source / drain regions 16b formed of a p-type impurity high concentration region.

Underlayer 14 including both semiconductor thin films 15 and 16
On the entire upper surface of the lower gate insulating film 17 made of silicon oxide and the upper gate insulating film 18 made of silicon nitride.
Is provided. Gate electrodes 19 and 20 made of chromium are provided on the upper surface of the upper gate insulating film 18 and above the channel regions 15a and 16a. An interlayer insulating film 21 made of silicon nitride is provided on the entire upper surface of the upper gate insulating film 18 including both gate electrodes 19 and 20. The contact holes 2 are formed in the interlayer insulating film 21 in the portions corresponding to the source / drain regions 15c and 16b.
2, 23 are provided. Each contact hole 22,
Source / drain electrodes 24 and 25 made of aluminum are provided at predetermined places on the upper surfaces of the interlayer insulating film 23 and the interlayer insulating film 21, respectively.

Next, a specific example of the method of manufacturing the C-MOS thin film transistor will be described with reference to FIGS.
Will be described in order. First, as shown in FIG. 2A, a base layer 14 made of silicon oxide is formed on the upper surface of the insulating substrate 11 made of glass by using a sputtering apparatus.
Is deposited to a thickness of about 1000Å. Next, the underlayer 12
On the upper surface of the plasma C using a mixed gas of SiH ₄ and H _2.
50 by hydrogenation amorphous silicon thin film 31 by VD
Deposit to a thickness of 0Å. Next, in order to prevent hydrogen from bumping and causing defects when high energy is applied by excimer laser irradiation in a later step, dehydrogenation treatment is performed in a nitrogen gas atmosphere at a temperature of about 450 ° C. for about 1 hour. Is performed so that the hydrogen content in the amorphous silicon thin film 31 is several atomic% or less. Next, an excimer laser is used at an energy density of about 350 mJ / cm ²
By irradiating once or several times, as shown in FIG. 2B, the amorphous silicon thin film 31 is polycrystallized to form a polycrystalline silicon thin film 32.

Next, as shown in FIG. 2C, a protective layer 33 made of silicon oxide is deposited on the upper surface of the polycrystalline silicon thin film 32 to a thickness of about 200 Å by using a sputtering apparatus. Next, an ion implantation apparatus is used to perform three times of impurity implantation using respective dedicated impurity implantation masks (photoresists). That is, the polycrystalline silicon thin film 32 in the region where the source / drain region 15b of the n-MOS thin film transistor 12 is to be formed is diluted with hydrogen to 1% PH.
Using a mixed gas of ₃ (5 ccm) and H ₂ (45 ccm), phosphorus ions were supplied with a high frequency power of 10 W and an acceleration voltage of 20 K.
Implantation is performed under the conditions of V and a dose amount of 5 × 10 ¹³ atm / cm ² to form an n-type impurity low concentration region. Further, 1% PH ₃ (50 ccm) gas diluted with hydrogen is used for the polycrystalline silicon thin film 32 in the region where the source / drain region 15 c of the n-MOS thin film transistor 12 is to be formed, and phosphorus ions are supplied at a high frequency power of 100 W and an acceleration voltage of 20 KV. , Dose 2x
Implantation is performed under the condition of 10 ¹⁵ atm / cm ² to form an n-type impurity high concentration region. Furthermore, the p-MOS thin film transistor 1
In the polycrystalline silicon thin film 32 in the region where the source / drain region 16b of No. 3 is to be formed, hydrogen diluted with 1% B ₂ H ₆ (50
(ccm) gas is used to generate boron ions at high frequency power 10
0 W, acceleration voltage 20 KV, dose 2 × 10 ¹⁵ atm /
Implantation is performed under the condition of cm ² to form a p-type impurity high concentration region.

Next, as shown in FIG. 2 (D), 1% B ₂ H ₆ ( ₂ ccm) and H ₂ (48 c) diluted with hydrogen are formed on the entire polycrystalline silicon thin film 32 without using any impurity implantation mask.
cm), and boron ions are used for high-frequency power 10 W, acceleration voltage 25 KV, and dose 2 × 10 ¹³ at.
Inject under the condition of m / cm ² . After that, the protective film 33 is peeled off by a well-known method, the implanted impurities are activated by heat treatment, the polycrystalline silicon thin film 32 is separated into elements to form semiconductor thin films 15 and 16, and lower and upper gate insulation is performed. The films 17 and 18 are deposited, the gate electrodes 19 and 20 are formed, the interlayer insulating film 21 is deposited, and the contact holes 22 and
After forming 23 and forming the source / drain electrodes 24 and 25, the C-MOS thin film transistor shown in FIG. 1 is manufactured.

By the way, by the above manufacturing method,
When a plurality of C-MOS thin film transistors are formed on an insulating substrate and the distribution of the threshold voltage Vt1n is examined for each of the n-MOS thin film transistor and the p-MOS thin film transistor, FIG. 3 (A) and FIG. 4 (A) are shown. The respective results were obtained (the vertical axis in the figure represents the number of thin film transistors). However, the threshold voltage Vt1n of the n-MOS thin film transistor is equal to the drain applied voltage of +1.
It is the gate applied voltage when the drain current is +1 nA at V, and the threshold voltage Vt1n of the p-MOS thin film transistor is the gate applied voltage when the drain applied voltage is -1 V and the drain current is -1 nA.

Further, for comparison, among the above-described manufacturing methods, a manufacturing method in which the step shown in FIG. 2D (step of implanting a p-type impurity into the channel region) is not performed, a plurality of insulating substrates are formed. C-MOS thin film transistor is formed, and n-
When the distribution of the threshold voltage Vt1n was examined for each of the MOS thin film transistor and the p-MOS thin film transistor, the results shown in FIGS. 3B and 4B were obtained (the vertical axis in the figure indicates the number of thin film transistors). Indicates). However, the threshold voltage Vt1n is the same as that described above.

Then, for the n-MOS thin film transistor, when the channel region p-type impurity is implanted (see FIG. 3).
Comparing (A)) and without (Fig. 3 (B)),
Although the distribution shapes of the threshold voltage Vt1n are similar, the threshold voltage Vt1n (-2 to -1V) has a peak in the range of FIG. 3A and the threshold voltage Vt1n of FIG. 3B. It peaks in the range of (-4 to -3V), and therefore, in the case of FIG. 3A, it is shifted by about 2V to the plus side as compared with the case of FIG. 3B. On the other hand, comparing the p-MOS thin film transistor with the channel region p-type impurity implantation (FIG. 4A) and without it (FIG. 4B), the threshold voltage V
The distribution shapes of t1n are similar to each other, and the threshold voltages Vt1n of both are peaked in the range of (−4 to −3V).

Considering the above points, the threshold voltage Vt
Assuming that the channel region is a pure intrinsic region when 1n is 0V, the threshold voltage Vt1n in the case of FIG.
Since the peak of is in the range of (-4 to -3V), n-M
The channel region of the OS thin film transistor is not a pure intrinsic region but an n-type region. On the other hand, FIG. 3 (A)
In the case of, the peak of the threshold voltage Vt1n is (−2 to −1).
In the range of V), the channel region of the n-MOS thin film transistor is shifted to the plus side by about 2V as compared with the case of FIG. After spreading, it is closer to the true nature. By the way, as shown in FIGS. 4A and 4B, in the case of the p-MOS thin film transistor, the peak of the threshold voltage Vt1n hardly changes. Considering this point, in the case of a thin film transistor using a polycrystalline silicon thin film, the Fermi level Ef and the threshold voltage Vt
The relationship with 1n seems to be as shown in FIG. Then, the threshold voltage Vt1 of the n-MOS thin film transistor
Since the Fermi level Ef comes in the region where n is sensitive and the region where the threshold voltage Vt1n of the p-MOS thin film transistor is insensitive, when the p-type impurity is diffused in the channel region,
Only the threshold voltage Vt1n of the -MOS thin film transistor seems to shift to the positive side.

Next, the threshold voltage Vt1n and the drain current Idss of the n-MOS thin film transistor and the p-MOS thin film transistor in which the p-type impurities are implanted in the channel region.
The relationship shown in FIG. 6 was examined, and the results shown in FIG. 6 were obtained. However, the drain current Idss of the n-MOS thin film transistor is the drain current when the gate applied voltage is 0V and the drain applied voltage + 12V, and the drain current Idss of the p-MOS thin film transistor is the gate applied voltage 0V and the drain applied voltage -12V. Is the drain current. As is clear from this figure, it is confirmed that the leak current of the n-MOS thin film transistor can be reduced without increasing (changing) the leak current of the p-MOS thin film transistor.

By the way, since the current consumption of the n-MOS thin film transistor is larger than that of the p-MOS thin film transistor, even if the leak current of the p-MOS thin film transistor cannot be reduced, the leak current of the n-MOS thin film transistor is reduced. If it can be reduced, C-
The static power consumption of the entire MOS thin film transistor can be reduced. Also, as described above, n
Since no impurity implantation mask is used when p-type impurities are implanted into the channel regions of the -MOS thin film transistor and the p-MOS thin film transistor, the number of manufacturing steps can be reduced.

In the above embodiment, as shown in FIG. 2D after the step shown in FIG. 2C, the entire polycrystalline silicon thin film 32 is diluted with hydrogen to 1% B ₂ H ₆ ( ₂ ccm). H
Using a mixed gas with ₂ (48 ccm), boron ions are supplied with high-frequency power of 10 W, acceleration voltage of 25 KV, and dose of 2 ×.
The implantation is performed under the condition of 10 ¹³ atm / cm ² , but the implantation is not limited to this. For example, after the hydrogenated amorphous silicon thin film is deposited and before the dehydrogenation process is performed, and without using the protective film 33 and the impurity implantation mask, the entire hydrogenated amorphous silicon thin film is 0.05% diluted with hydrogen. B ₂ H ₆ (5 ccm) and H ₂ (45 ccm)
High-frequency power of boron ions 10 using a mixed gas of
W, acceleration voltage 10 KV, dose amount 5 × 10 ¹³ atm / c
It may be injected under the condition of m ² . Even in this case, it is possible to obtain the same effect as that of the above embodiment. Moreover, compared with the case of the above embodiment, B ₂ H ₆
Flow rate increased from 2 ccm to 5 ccm, and the dose amount was 2 × 10 ¹³ atm / cm ² to 5 × 10 ¹³ atm /
Since it is increased to cm ² , the controllability of the number of ions actually implanted can be improved.

Further, in the above-mentioned embodiment, the case of applying to the thin film transistor of the top gate coplanar structure has been described, but the present invention is not limited to this, and can be applied to the thin film transistor of the bottom gate inverted stagger structure. Also,
In the above embodiment, the n-MOS thin film transistor is an LD.
Although the case of the D structure has been described, the p-MOS thin film transistor may also have the LDD structure.

[0020]

As described above, according to the present invention, no impurity implantation mask is used when p-type impurities are implanted into the entire semiconductor thin film of the n-MOS thin film transistor and the entire semiconductor thin film of the p-MOS thin film transistor. Alternatively, since only one sheet needs to be used, the number of manufacturing steps can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view of a C-MOS thin film transistor according to an embodiment of the present invention.

2A to 2D are C-MOs shown in FIG. 1, respectively.
Sectional drawing of each manufacturing process shown in order to demonstrate a specific example of the manufacturing method of an S thin film transistor.

3A and 3B are diagrams showing distributions of respective threshold voltages in the case where a p-type impurity is implanted into a channel region of an n-MOS thin film transistor and the case where it is not implanted.

FIGS. 4A and 4B are graphs showing distributions of threshold voltages when p-type impurities are implanted into a channel region of a p-MOS thin film transistor and when no p-type impurity is implanted into the channel region, respectively.

FIG. 5 is a diagram showing a relationship between a Fermi level and a threshold voltage of an n-MOS thin film transistor and a p-MOS thin film transistor using a polycrystalline silicon thin film.

FIG. 6 shows n-M when impurities are implanted in a channel region.
FIG. 7 is a graph showing a relation between a threshold voltage and a drain current of an OS thin film transistor and a p-MOS thin film transistor.

FIG. 7 is a circuit diagram of a C-MOS thin film transistor.

[Explanation of symbols]

 12 n-MOS thin film transistor 13 p-MOS thin film transistor 15 and 16 semiconductor thin film 15a channel region 15b source / drain region 15c source / drain region 16a channel region 16b source / drain region

Claims (6)

[Claims] 1. An n-MOS thin film transistor and a p-MO
In a thin film semiconductor device having an S thin film transistor, the n-MOS thin film transistor and the p-MO thin film transistor are provided.
A thin film semiconductor device in which substantially the same amount of p-type impurities are diffused in each channel region of an S thin film transistor. 2. The invention according to claim 1, wherein the n-
In the MOS thin film transistor, a substantially intrinsic channel region is interposed between the n-type source / drain regions, and the p-type impurity is diffused in the channel region after the diffusion in an amount closer to the intrinsic nature. Characteristic thin film semiconductor device. 3. The method according to claim 1, wherein
A thin film semiconductor device, wherein a C-MOS thin film transistor is constituted by the n-MOS thin film transistor and the p-MOS thin film transistor. 4. The n-MO is formed by implanting p-type impurities into the entire semiconductor thin film of the n-MOS thin film transistor and the entire semiconductor thin film of the p-MOS thin film transistor.
A method of manufacturing a thin film semiconductor device, wherein substantially the same amount of p-type impurities is injected into each channel region of the S thin film transistor and the p-MOS thin film transistor. 5. The invention according to claim 4, wherein the n-
In a MOS thin film transistor, p-type impurities are implanted into an n-type source / drain region and a substantially intrinsic channel region interposed therebetween in an amount such that the channel region is closer to the intrinsic state after the diffusion than before the diffusion. A method of manufacturing a thin film semiconductor device characterized by the above. 6. The invention according to claim 4, wherein
A method of manufacturing a thin film semiconductor device, characterized in that a C-MOS thin film transistor is formed by the n-MOS thin film transistor and the p-MOS thin film transistor.