JP3577523B2 - Method for manufacturing thin film semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
This invention relates to a method of manufacturing a thin film semiconductor device capable of reducing the leakage current.
[0002]
[Prior art]
In a C-MOS thin film transistor which is one of the thin film semiconductor devices, as shown in FIG. 7, each gate electrode of a p-MOS thin film transistor 1 and an n-MOS thin film transistor 2 is connected to an input terminal 3, and the p-MOS thin film transistor 1 a structure in which each drain electrode of the n-MOS thin film transistor 2 is connected to the output terminal 4, the source electrode of the p-MOS thin film transistor 1 is connected to the power supply terminal 5, and the source electrode of the n-MOS thin film transistor 2 is connected to the ground terminal 6; Has become. Power consumption of C-MOS thin film transistor, the operating frequency f, when the load capacitance C, and the power supply voltage Vdd, the leakage current and IL, a static dynamic power dissipation (f · C · Vdd ²⁾ It is expressed by the sum of power consumption (IL · Vdd).
[0003]
By the way, in a thin film transistor having a general structure using a polycrystalline silicon thin film as a semiconductor thin film, a C-MOS thin film transistor is largely affected by a leak current or the like via a trap level unevenly distributed in a crystal grain boundary of the polycrystalline silicon thin film. It is no exaggeration to say that overall power consumption is almost determined by static power consumption. Therefore, in order to reduce the leakage current of the thin film transistor, a threshold voltage is adjusted by injecting a impurity of a conductivity type different from that contained in the source / drain regions into the channel region at a low concentration. There is.
[0004]
[Problems to be solved by the invention]
However, the impurities to be implanted into the channel region are different between the p-MOS thin film transistor and the n-MOS thin film transistor. Therefore, it is necessary to separately implant the impurities into each channel region using a dedicated impurity implantation mask (photoresist). Therefore, there is a problem that the number of manufacturing steps increases.
An object of the present invention is to reduce the number of manufacturing steps.
[0005]
[Means for Solving the Problems]
2. The method for manufacturing a thin film semiconductor device according to claim 1, wherein n-type ions are implanted into the semiconductor thin film at a low concentration to form n-type impurity low-concentration regions on both sides of the channel region, and the respective n-type impurities are formed. N-type ions are implanted at a high concentration on the opposite side of the channel region of the low-concentration region to form a high-concentration n-type impurity region. An n-MOS thin film transistor having a drain region is formed, and p-type ions are implanted at a high concentration on both sides of the channel region, and p and p regions having a source / drain region comprising a p-type impurity high concentration region are directly formed on both sides of the channel region. a method of manufacturing a thin film semiconductor device forming the -MOS TFT, the n-type impurity low concentration region and the n-type high impurity concentration of the n-MOS thin film transistor Forming a band, after forming the p-type high impurity concentration region of the p-MOS thin film transistor, the entire semiconductor thin film constituting the n-MOS thin film transistor and the p-MOS thin film transistor, n-type impurity of the n-MOS thin film transistor The method is characterized in that p-type ions are implanted at a dose smaller than the dose of n-type ions implanted in the low concentration region .
According to a second aspect of the present invention, in the method for manufacturing a thin film semiconductor device according to the first aspect, the dose of n-type ions implanted into the n-type impurity low concentration region of the n-MOS thin film transistor is 5 × 10 ^13. atm / cm ² , and the dose of p-type ions implanted into the semiconductor thin film forming the n-MOS thin film transistor and the p-MOS thin film transistor is 2 × 10 ¹³ atm / cm ^2. is there.
According to a third aspect of the invention, there is provided a method of manufacturing a thin film semiconductor device according to the first aspect, wherein n-type ions are implanted into the n-type impurity low concentration region and the n-type impurity high concentration region of the n-MOS thin film transistor. Implanting p-type ions into the p-type impurity high-concentration region of the p-MOS thin film transistor and implanting p-type ions into the semiconductor thin film forming the n-MOS thin film transistor and the p-MOS thin film transistor are performed on the semiconductor thin film. A protective film is formed on the protective film, and the process is performed through the protective film.
A method of manufacturing a thin film semiconductor device according to a fourth aspect of the invention is characterized in that, in the invention of the third aspect , after all ions are implanted, the protective film is peeled off, and impurities are activated. It is.
According to a fifth aspect of the invention, there is provided a method of manufacturing a thin film semiconductor device according to the fourth aspect , wherein a gate insulating film is formed after activating impurities.
[0006]
According to the method of manufacturing a thin film semiconductor device according to claim 1, an n-type impurity thin region and an n-type impurity high concentration region of the n-MOS thin film transistor are formed, and the p-type impurity high concentration region of the p-MOS thin film transistor is formed. After the formation, the threshold voltages of the n-MOS thin film transistor and the p-MOS thin film transistor can be adjusted by implanting p-type impurities into the entire semiconductor thin film of the n-MOS thin film transistor and the whole semiconductor thin film of the p-MOS thin film transistor. The number of manufacturing steps can be reduced, and the power consumption of the n-MOS thin film transistor can be reduced.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a C-MOS thin film transistor according to an embodiment of the present invention. In this C-MOS thin-film transistor, an n-MOS thin-film transistor 12 and a p-MOS thin-film transistor 13 are provided at predetermined locations on the upper surface of an insulating substrate 11 made of glass or the like. Each of the thin film transistors 12 and 13 includes semiconductor thin films 15 and 16 respectively formed at predetermined positions on the upper surface of a base layer 14 made of silicon oxide provided on the upper surface of the insulating substrate 11. The semiconductor thin film 15 of the n-MOS thin film transistor 12 has a channel region 15a at the center, a source / drain region 15b formed of a low-concentration n-type impurity region on both sides thereof, and further includes a source-drain region 15b on both sides thereof. The source / drain region 15c is formed. The semiconductor thin film 16 of the p-MOS thin film transistor 13 has a structure in which a central portion is a channel region 16a and both sides are source / drain regions 16b formed of a p-type impurity high concentration region.
[0008]
A lower gate insulating film 17 made of silicon oxide and an upper gate insulating film 18 made of silicon nitride are provided on the entire upper surface of the underlayer 14 including both the semiconductor thin films 15 and 16. Gate electrodes 19 and 20 made of chromium are provided on the upper surface of the upper gate insulating film 18 and above the channel regions 15a and 16a. An interlayer insulating film 21 made of silicon nitride is provided on the entire upper surface of the upper gate insulating film 18 including both the gate electrodes 19 and 20. Contact holes 22 and 23 are provided in the interlayer insulating film 21 at portions corresponding to the source / drain regions 15c and 16b. Source / drain electrodes 24 and 25 made of aluminum are provided at predetermined positions on each of the contact holes 22 and 23 and the upper surface of the interlayer insulating film 21.
[0009]
Next, a specific example of a method of manufacturing the C-MOS thin film transistor will be described with reference to FIGS. First, as shown in FIG. 2A, a base layer 14 made of silicon oxide is deposited on the upper surface of an insulating substrate 11 made of glass to a thickness of about 1000 ° by using a sputtering apparatus. Next, a hydrogenated amorphous silicon thin film 31 is deposited on the upper surface of the underlayer 12 to a thickness of about 500 ° by plasma CVD using a mixed gas of SiH ₄ and H ₂ . Next, in order to avoid the occurrence of defects due to bumping of hydrogen when high energy is applied by excimer laser irradiation in a later step, dehydrogenation treatment is performed in a nitrogen gas atmosphere at a temperature of about 450 ° C. for about 1 hour. Is performed so that the hydrogen content in the amorphous silicon thin film 31 becomes several atomic% or less. Next, an excimer laser is irradiated once or several times at an energy density of about 350 mJ / cm ² to polycrystallize the amorphous silicon thin film 31 into a polycrystalline silicon thin film 32 as shown in FIG. .
[0010]
Next, as shown in FIG. 2C, a protective layer 33 made of silicon oxide is deposited on the upper surface of the polycrystalline silicon thin film 32 to a thickness of about 200 ° by using a sputtering device. Next, three times of impurity implantation are performed using an ion implantation apparatus by using a dedicated impurity implantation mask (photoresist). That is, a mixed gas of 1% PH ₃ (5 ccm) and H ₂ (45 ccm) diluted with hydrogen is used for the polycrystalline silicon thin film 32 in a region where the source / drain region 15 b of the n-MOS thin film transistor 12 is to be formed. Phosphorus ions are implanted under the conditions of a high-frequency power of 10 W, an acceleration voltage of 20 KV, and a dose of 5 × 10 ¹³ atm / cm ² to form an n-type impurity low concentration region. Further, the polycrystalline silicon thin film 32 in the region where the source / drain region 15c of the n-MOS thin film transistor 12 is to be formed is doped with hydrogen-diluted 1% PH ₃ (50 ccm) gas, using phosphorus ions at a high frequency power of 100 W and an acceleration voltage of 20 KV. , At a dose of 2 × 10 ¹⁵ atm / cm ² to form an n-type impurity high concentration region. Further, the polycrystalline silicon thin film 32 in the region where the source / drain region 16b of the p-MOS thin film transistor 13 is to be formed is formed by using boron-diluted 1% B ₂ H ₆ (50 ccm) gas and applying high-frequency power of 100 W to boron ions. Implantation is performed under the conditions of an acceleration voltage of 20 KV and a dose of 2 × 10 ¹⁵ atm / cm ² to form a p-type impurity high concentration region.
[0011]
Next, as shown in FIG. 2 (D), 1% B ₂ H ₆ ( ₂ ccm) and H ₂ (48 ccm) diluted with hydrogen are applied to the entire polycrystalline silicon thin film 32 without using any impurity implantation mask. Using a mixed gas, boron ions are implanted under the conditions of a high-frequency power of 10 W, an acceleration voltage of 25 KV, and a dose of 2 × 10 ¹³ atm / cm ² . Thereafter, the protective film 33 is peeled off by a well-known method, the implanted impurities are activated by heat treatment, and the polycrystalline silicon thin film 32 is subjected to element isolation to form semiconductor thin films 15 and 16. When films 17 and 18 are deposited, gate electrodes 19 and 20 are formed, an interlayer insulating film 21 is deposited, contact holes 22 and 23 are formed, and source / drain electrodes 24 and 25 are formed. -A MOS thin film transistor is manufactured.
[0012]
By the way, a plurality of C-MOS thin-film transistors were formed on an insulating substrate by the above manufacturing method, and the distribution of the threshold voltage Vt1n was examined for each of the n-MOS thin-film transistor and the p-MOS thin-film transistor. The results shown in FIGS. 4A and 4A were obtained (the vertical axis in the figure indicates the number of thin film transistors). However, the threshold voltage Vt1n of the n-MOS thin film transistor is a gate applied voltage when the drain applied voltage is +1 V and the drain current is +1 nA, and the threshold voltage Vt1n of the p-MOS thin film transistor is the drain applied voltage. This is the gate applied voltage when the drain current becomes -1 nA at -1 V.
[0013]
For comparison, a plurality of C-MOS transistors are formed on an insulating substrate by the above-described manufacturing method in which the step shown in FIG. 2D (the step of implanting a p-type impurity into a channel region) is not performed. When a thin film transistor was formed and the distribution of the threshold voltage Vt1n was examined for each of the n-MOS thin film transistor and the p-MOS thin film transistor, the results shown in FIGS. 3B and 4B were obtained (FIG. 3B). The vertical axis indicates the number of thin film transistors.) However, the threshold voltage Vt1n is the same as in the case described above.
[0014]
When the n-MOS thin film transistor is compared with the case where the p-type impurity is implanted in the channel region (FIG. 3A) and the case where it is not (FIG. 3B), the distribution shapes of the threshold voltages Vt1n are similar. However, in FIG. 3A, the peak is in the range of the threshold voltage Vt1n (−2 to −1V), and in FIG. 3B, the peak is in the range of the threshold voltage Vt1n (−4 to −3V). Therefore, in the case of FIG. 3 (A), it is shifted by about 2 V to the plus side as compared with the case of FIG. 3 (B). On the other hand, when the p-MOS thin film transistor is compared with the case where the p-type impurity is implanted in the channel region (FIG. 4 (A)) and the case where it is not (FIG. 4 (B)), the distribution shapes of the threshold voltages Vt1n are similar. In addition, both of the threshold voltages Vt1n peak in the range of (−4 to −3 V).
[0015]
Considering the above points, assuming that the channel region is a pure intrinsic region when the threshold voltage Vt1n is 0 V, in the case of FIG. −3V), the channel region of the n-MOS thin film transistor is not a pure intrinsic region but an n-type region. On the other hand, in the case of FIG. 3A, the peak of the threshold voltage Vt1n is in the range of (−2 to −1V), and is shifted by about 2 V to the plus side as compared with the case of FIG. Therefore, the channel region of the n-MOS thin film transistor becomes closer to intrinsic after diffusion than before diffusion due to diffusion of the p-type impurity. By the way, as shown in FIGS. 4A and 4B, in the case of a p-MOS thin film transistor, the peak of the threshold voltage Vt1n hardly changes. Considering this point, in the case of a thin film transistor using a polycrystalline silicon thin film, the relationship between the Fermi level Ef and the threshold voltage Vt1n seems to be as shown in FIG. Since the Fermi level Ef comes to a region where the threshold voltage Vt1n of the n-MOS thin film transistor is sensitive and a region where the threshold voltage Vt1n of the p-MOS thin film is insensitive, when p-type impurities are diffused into the channel region, It seems that only the threshold voltage Vt1n of the n-MOS thin film transistor shifts to the plus side.
[0016]
Next, when the relationship between the threshold voltage Vt1n and the drain current Idss of the n-MOS thin film transistor and the p-MOS thin film transistor into which the p-type impurity was implanted into the channel region was examined, the result shown in FIG. 6 was obtained. Here, the drain current Idss of the n-MOS thin film transistor is a drain current when the gate applied voltage is 0 V and the drain applied voltage is +12 V, and the drain current Idss of the p-MOS thin film transistor is the gate applied voltage of 0 V and the drain applied voltage of −12 V. The drain current. As is clear from this figure, it is confirmed that the leak current of the n-MOS thin film transistor can be reduced without increasing (changing) the leak current of the p-MOS thin film transistor.
[0017]
By the way, since the current consumption of the n-MOS thin film transistor is larger than that of the p-MOS thin film transistor, it is necessary to reduce the leakage current of the n-MOS thin film transistor even if the leakage current of the p-MOS thin film transistor cannot be reduced. When this is achieved, the static power consumption of the entire C-MOS thin film transistor can be reduced. Further, as described above, when p-type impurities are implanted into each channel region of the n-MOS thin film transistor and the p-MOS thin film transistor, no impurity implantation mask is used, so that the number of manufacturing steps can be reduced.
[0018]
In the above embodiment, as shown in FIG. 2D, after the step shown in FIG. 2C, 1% B ₂ H ₆ ( ₂ ccm) diluted with hydrogen and H ₂ ( 48 ccm), and boron ions are implanted under the conditions of a high-frequency power of 10 W, an acceleration voltage of 25 KV, and a dose of 2 × 10 ¹³ atm / cm ² , but the present invention is not limited to this. For example, after depositing the hydrogenated amorphous silicon thin film and before performing the dehydrogenation process, and without using the protective film 33 and the impurity implantation mask, the hydrogen-containing amorphous silicon thin film may be diluted with 0.05% of hydrogen dilution. Using a mixed gas of B ₂ H ₆ (5 ccm) and H ₂ (45 ccm), boron ions are implanted under the conditions of a high-frequency power of 10 W, an acceleration voltage of 10 KV, and a dose of 5 × 10 ¹³ atm / cm ^2. Is also good. Even in this case, the same effect as in the above embodiment can be obtained. Moreover, the flow rate of B ₂ H ₆ is increased from ₂ ccm to 5 ccm and the dose is increased from 2 × 10 ¹³ atm / cm ² to 5 × 10 ¹³ atm / cm ^{2 as} compared with the case of the above embodiment. Therefore, the controllability of the number of ions to be actually implanted can be improved.
[0019]
Further, the above embodiment has been described as applied to a thin film transistor of a top gate co Plana structure is not limited thereto, Ru can be applied to the thin film transistor of a bottom gate reverse stagger structure.
[0020]
【The invention's effect】
As described above, according to the present invention, after forming the n-type impurity low concentration region and the n-type impurity high concentration region of the n-MOS thin film transistor, and after forming the p-type impurity high concentration region of the p-MOS thin film transistor, , by implanting the p-type impurity on the entire semiconductor thin film of the entire semiconductor thin film of n-MOS thin film transistor and a p-MOS thin film transistor, it is possible to adjust the threshold voltage of the n-MOS thin film transistor and a p-MOS thin film transistors, the number of manufacturing steps Can be reduced, and the power consumption of the n-MOS thin film transistor can be reduced.
[Brief description of the drawings]
FIG. 1 is a sectional view of a C-MOS thin film transistor according to an embodiment of the present invention.
2 (A) to 2 (D) are cross-sectional views of respective manufacturing steps for explaining a specific example of a method for manufacturing the C-MOS thin film transistor shown in FIG. 1;
FIGS. 3A and 3B are diagrams showing distributions of respective threshold voltages when a p-type impurity is implanted into a channel region of an n-MOS thin film transistor and when it is not implanted.
FIGS. 4A and 4B are diagrams showing distributions of respective threshold voltages when a p-type impurity is implanted into a channel region of a p-MOS thin film transistor and when it is not implanted.
FIG. 5 is a diagram showing a relationship between a Fermi level and a threshold voltage of an n-MOS thin film transistor and a p-MOS thin film transistor using a polycrystalline silicon thin film.
FIG. 6 is a diagram showing a relationship between a threshold voltage and a drain current of an n-MOS thin film transistor and a p-MOS thin film transistor when an impurity is implanted into a channel region.
FIG. 7 is a circuit diagram of a C-MOS thin film transistor.
[Explanation of symbols]
12 n-MOS thin film transistor 13 p-MOS thin film transistor 15, 16 semiconductor thin film 15a channel region 15b source / drain region 15c source / drain region 16a channel region 16b source / drain region

Claims (5)

N-type ions are implanted at a low concentration into the semiconductor thin film to form n-type impurity low-concentration regions on both sides of the channel region, and n-type ions are implanted on the opposite side of each of the n-type impurity low-concentration regions to the channel region. An n-MOS thin film transistor having a source / drain region comprising the n-type impurity low-concentration region and the n-type impurity high-concentration region is formed by injecting the impurity into the n-type impurity high-concentration region. A p-type thin film semiconductor device comprising a p-MOS thin film transistor having a source / drain region comprising a p-type impurity high-concentration region directly on both sides of a channel region by implanting p-type ions at a high concentration.
After forming an n-type impurity low concentration region and an n-type impurity high concentration region of the n-MOS thin film transistor and forming a p-type impurity high concentration region of the p-MOS thin film transistor , the n-MOS thin film transistor and the p-MOS A thin-film semiconductor device, wherein p-type ions are implanted into a whole semiconductor thin film constituting a thin-film transistor at a dose smaller than that of n-type ions implanted into an n-type impurity low-concentration region of the n-MOS thin-film transistor. Manufacturing method. 2. The n-MOS thin film transistor and the p-type MOS transistor according to claim 1, wherein the dose of n-type ions implanted into the n-type impurity low concentration region of the n-MOS thin film transistor is 5 × 10 ¹³ atm / cm ^2. A method for manufacturing a thin film semiconductor device, wherein the dose of p-type ions implanted into a semiconductor thin film forming a MOS thin film transistor is 2 × 10 ¹³ atm / cm ² . 2. The invention according to claim 1, wherein n-type ions are implanted into an n-type impurity low concentration region and an n-type impurity high concentration region of the n-MOS thin film transistor, and p-type ions are implanted into a p-type impurity high concentration region of the p-MOS thin film transistor. The implantation of p-type ions and the implantation of p-type ions into the semiconductor thin film forming the n-MOS thin film transistor and the p-MOS thin film transistor are performed by forming a protective film on the semiconductor thin film and through the protective film. A method for manufacturing a thin-film semiconductor device. 4. The method according to claim 3 , wherein after all the ions are implanted, the protective film is peeled off to activate the impurities. 5. The method according to claim 4 , wherein a gate insulating film is formed after activating the impurities.

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