JPH04313238A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the structure of a highly reliable semiconductor device which is used in an analog circuit or other devices. CONSTITUTION:This semiconductor device has two gates (5) which are installed near to each other in the channel direction on the layer (21) of one conductivity type formed in an active region of a semiconductor substrate (1), an impurity region (6) which is formed at enough depth to separate the conductive layer (21) completely in a part of the substrate which is between the gates, a main gate (7) which is so formed as to fill the space between these gates and to stretch over the two gates, and source.drain regions (8) which are formed on both sides of the two gates.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, particularly the structure of transistors used in analog circuits and the like.

0002

2. Description of the Related Art Transistors in integrated circuits are becoming increasingly finer with advances in microfabrication technology. With the miniaturization of transistors, several problems have become apparent, and among them, the problem of deterioration of the gate film of a MOS transistor due to hot electrons is important in terms of reliability of the transistor.

[0003] In a fine transistor with a gate length of 2 μm or less, reliability cannot be ensured with a normal structure, and it is necessary to take some countermeasures. A typical structure is (a) double drain (DD
D) and (b) light lead-putodrain (LDD). In either structure, the impurity concentration of the N layer is lowered at the channel junction where the electric field is concentrated, thereby relaxing the electric field and suppressing the generation of hot electrons.

In the case of a DDD structure, as in a normal transistor, after a gate is formed, impurities having different diffusion coefficients are doubly implanted when forming a source/drain. N.M.O.
In S transistors, it is common to first introduce phosphorus and then arsenic. By doing this, phosphorus with a large diffusion coefficient is also diffused in the channel direction, and N-
form a layer.

On the other hand, in an LDD structure, taking an NMOS transistor as an example, after the gate is formed, phosphorus or arsenic is first implanted at a relatively low dose to form an N- layer. Subsequently, a CVD oxide film is formed on the entire surface, and anisotropic etching is performed on this. By doing this,
A CVD oxide film remains on the sides of the gate. (referred to as sidewalls) After this, when a source/drain is formed, an N+ layer is not formed under the sidewalls, so an N- layer remains in the channel portion. In this way, by creating a junction between the N- layer and the P layer at the junction of the channel,
It can alleviate the electric field.

[0006]

[Problems to be Solved by the Invention] However, in such conventional techniques, it is difficult to freely control the junction concentration in the channel portion, and it is necessary to pay attention to alignment when diffusing or implanting a predetermined impurity. can be,
The disadvantage is that the manufacturing process is complicated.

[0007]

[Means for Solving the Problems] The present invention provides a transistor requiring high reliability, in which the entire active region in which the transistor is formed is an N- layer or a P layer having a lower impurity concentration than the channel region. After that, two gates that will become electric field relaxation regions are formed close to each other, and the gap between the two gates is adjusted to the desired channel concentration.
Form the main gate. Thereafter, sources and drains are formed by self-alignment.

[0008]

[Operation] By forming the entire active region as an N- layer or a P- layer having a lower impurity concentration than the channel region, generation of hot carriers can be suppressed and the impurity concentration in the channel region can be easily suppressed.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory diagram of a manufacturing method according to a first embodiment of the present invention. The present invention will be explained using an NMOS transistor as an example. As before, after the substrate is separated into an active region and a field region by a field oxide film 3 using LOCOS, an N- layer 21 (FIG. 1a) is applied to the active region where a highly reliable transistor is formed. ) to form.

The concentration setting of this N- layer 21 is important. First, when forming the N- layer 21, this concentration is higher than that of the conventional DDD transistor or LDD transistor.
− Corresponds to a layer. If you place more emphasis on transistor performance (response speed), set it to a higher value, and if you place more emphasis on reliability, set it to a lower value. In either case, the concentration of the P layer 6 (formed in a later process) in the channel region of the transistor and this N
- The concentration difference in layer 21 determines the amount of hot carriers generated.

Next, two polysilicon gates (hereinafter referred to as side gates) 5 are formed close to each other in the channel direction. (FIG. 1b) Here, the gate lengths of these two gates 5 correspond to the sidewall regions of the LDD transistor. Further, the gate interval between the two gates corresponds to the gate length of this transistor.

After forming the side gates 5, impurities are introduced between the side gates to obtain a desired channel concentration. (Fig. 1c) At this time, 1, the P layer 6 formed in the channel is N-
It is important to ensure that layer 21 is divided. After adjusting the concentration of the channel 6, polysilicon is again filled into this gap, and this is used as the main gate 7. After this (corresponding to FIG. 1d), the source/drain 8 is formed by self-alignment (FIG. 1e), and the subsequent steps are similar to the conventional steps.

In FIG. 1, the side gate 5 and the main gate 7 are electrically insulated, and it is possible to apply separate voltages, but basically the side gate and the main gate are , it is also possible to use them at the same potential, and when they are used at the same potential, they do not necessarily need to be insulated.

FIG. 3 is an explanatory diagram of a manufacturing method according to a second embodiment of the present invention. In this embodiment, a P- layer 22 is formed in place of the N- layer 21 formed in the first embodiment. (FIG. 3a) The concentration setting of the P- layer 22 is important as in the case of the N- layer 21, and is set to be thinner than the concentration of the P layer 6 in the channel region. As for how thin it should be, this P- layer 22
This is determined depending on the concentration difference between the source and drain N- layers 8 forming the junction, that is, the reliability requirements.

The subsequent steps are carried out in the same manner as in the first embodiment to form the structure of the second embodiment of the present invention.

Further, although only polysilicon is shown as the gate material for the sake of explanation, it is also possible to use so-called polycide.

Furthermore, as shown in FIG.
A combination with DD or DDD structure is also possible. By doing so, a structure with even better resistance to hot carriers can be obtained.

Although the transistor structure of the present invention has performance similar to that of conventional transistors and can achieve high reliability, the size of the transistor becomes large. Therefore, it cannot be said that it is very advantageous to use the structure of the present invention as a cell transistor in a memory, etc., but it is suitable for use in analog circuits where reliability is particularly severe (bias conditions near Vgs = 1/2 Vds). It is advantageous to improve reliability for certain transistors when using high-voltage transistors or when Vds is as high as 9V).

[0019]

As described in detail above, since the structure is such that the junction concentration of the channel portion of the transistor can be freely controlled, the transistor can be constructed in accordance with the required reliability. Moreover, since the effective gate length of the transistor is the same as that of conventional transistors, performance etc. do not deteriorate. Furthermore, since all steps can be performed in self-alignment, there is an advantage that alignment errors do not occur.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the structure of a first embodiment of a semiconductor device according to the present invention according to its manufacturing steps.

FIG. 2 is a diagram showing the structure of a conventional transistor.

FIG. 3 is a diagram showing the structure of a second embodiment of the semiconductor device of the present invention according to its manufacturing steps;

FIG. 4 is a diagram showing another embodiment of the present invention.

[Explanation of symbols]

1 P type board 5 1st gate 6 P-type channel diffusion layer 21, 22 Diffusion layer 7 2nd gate 8 Source drain 3 Field oxide film 4 Gate oxide film

Claims (5)

[Claims] 1. Two gates provided close to each other in the channel direction on a layer of one conductivity type formed in an active region of a semiconductor substrate, and a portion of the substrate between these gates completely covered with the layer. An impurity region formed with a depth sufficient to separate the gates, a main gate formed to fill the space between the gates and to span the two gates, and source/drain regions formed on both sides of the two gates. A structure of a semiconductor device including. 2. The structure of claim 1, wherein the impurity concentration of the impurity region is greater than the impurity concentration of the one conductivity type layer. 3. The structure of claim 2, wherein said two gates and said main gate are electrically isolated. 4. The structure of claim 2, wherein said impurity region is of the same conductivity type as said layer. 5. The structure of claim 2, wherein said impurity region is different in conductivity type from said layer.