JPH0936271A - Semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a small-sized high-speed semiconductor package which can be manufactured easily. SOLUTION: A multilayer thin film wiring board which is constituted as a heat radiating body is provided with a built-up multilayered wiring layer B1 on one surface of a tough-pitch copper plate having high thermal conductivity. A die pad 17 for mounting LSI chips 18 and 19 which are electronic parts and a pad which is a first connecting terminal group are provided on the wiring layer B1. I/O pins 29 are formed as an input-output terminal group on one surface of a printed wiring board 25a constituting a base unit 25. A through window 26 is provided as a housing space at the central part of the printed wiring board 25a. A pad 30 is provided as a second connecting terminal groups electrically connected to the pad is provided near the window 26. The pad 30 is electrically connected to the pad through a film-like anisotropic conducting adhesive 33.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly to a semiconductor package (MCM: having a structure in which a plurality of electronic components are mounted on a build-up multilayer wiring layer).
The present invention relates to an electrical connection structure in a multi-chip module).

[0002]

2. Description of the Related Art Generally, an electric connection between an IC chip or an LSI chip and a printed wiring board which is a mother board is made through a semiconductor package. In recent years, resin-encapsulated semiconductor packages (so-called plastic packages) have become the mainstream. When manufacturing a plastic package, it is necessary to surely dissipate the heat generated by the LSI chip in order to prevent malfunction and thermal destruction of the LSI chip. Therefore, in the conventional plastic package, for example, a measure is taken to dispose a radiator, which is a plate material made of a high thermal conductive material such as Cu-W, on the back surface side of the chip mounting portion.

However, if an attempt is made to secure a large heat radiation area in the package by using a large heat radiator, the area where the wiring cannot be formed (dead area) is increased by the area of the heat radiation area. for that reason,
There is no choice but to increase the size of the entire package, which eventually delays the signal propagation speed. Therefore, speeding up of the package is hindered. On the contrary, if the dead area is made as small as possible to maintain the current state of the package size, the heat radiator must be made small, and as a result, a sufficient heat radiation area cannot be secured.

As a semiconductor package capable of solving such a problem, for example, the following packages have been proposed. FIG. 14 shows an example of the semiconductor package 101. The semiconductor package 101 includes a radiator 103 mainly made of a plate material 102 made of copper or the like, and the radiator 103.
And a base unit 105 having a through window 104 for mounting the. A build-up multilayer wiring layer B1 is formed on one side surface of the plate member 102 that constitutes the radiator 103. This build-up multilayer wiring layer B
An electronic component mounting portion for mounting the LSI chip 106 is provided in the central portion of the upper surface of 1. The semiconductor package 101 shown in the figure has an MCM structure in which a plurality of LSI chips 106 are mounted. A plurality of bonding pads 107 are provided on the outer peripheral portion of the upper surface of the buildup multilayer wiring layer B1.

On the other hand, a large number of I / O pins 108 are projected from one surface of the base unit 105. On the same surface, a plurality of bonding pads 109 are provided around the through window 104 so as to correspond to the bonding pads 107. The bonding pads 107 and 109 are bonded to each other via a bonding wire 110. As a result, LS
Electrical connection is made between the radiator 103 side on which the I-chip 106 is mounted and the base unit 105 side.

[0006]

However, in the case of this semiconductor package 101, the bonding pads 107,
Since the conductor connecting between 109 is the bonding wire 110, there are the following problems.

First, in the connection by the bonding wire 110, the wire length is longer than the actual inter-pad distance. Therefore, the inductance increases correspondingly, and the signal propagation speed is delayed. Therefore, the speedup of the semiconductor package 101 cannot be sufficiently achieved.

Second, the bonding pads 107 and 10
When the pitch of 9 becomes narrower, it is necessary to use the thin bonding wire 110 correspondingly. Then
The increase in inductance becomes more remarkable. Further, in this case, a problem in manufacturing is likely to occur, such that the wire bonding work itself becomes difficult.

Thirdly, in order to further reduce the outer size of the semiconductor package 101, it is considered that the structure in which the two bonding pads 107 and 109 are arranged side by side is not very advantageous.

The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor package which is small in size, high in speed, and easy to manufacture.

[0011]

In order to solve the above-mentioned problems, the invention according to claim 1 is characterized in that a build-up multilayer wiring layer is provided on one side surface of a plate material made of a high thermal conductive material,
A heat radiator provided with an electronic component mounting portion for mounting an electronic component on the wiring layer and a first connection terminal group, and substantially the center of the opposite side surface of a printed wiring board having an input / output terminal group on one side surface. A housing space in which the electronic component can be housed is provided, and a second connection terminal group electrically connected to the first connection terminal group is provided in the vicinity of the housing space. In a semiconductor package constituted by a base unit for mounting a heat radiator mounted with the side surface of the build-up multilayer wiring layer facing the printed wiring board side, the first connection terminal group and the second connection terminal group. A gist of the present invention is a semiconductor package in which a connection terminal group is electrically connected via an anisotropic conductive adhesive.

A second aspect of the present invention is based on the first aspect, and is characterized in that the accommodation space penetrates the printed wiring board. According to a third aspect of the present invention, the gist of the first aspect is that the accommodation space is a recess that does not penetrate the printed wiring board.

According to a fourth aspect of the present invention, in the second or third aspect, the outer dimension of the accommodation space is smaller than the outer dimension of the radiator by 1 mm to 2 mm, and the second portion is provided around the outer dimension.
The connection terminal is formed, and the anisotropic conductive adhesive is provided so as to surround the accommodation space.

According to the first aspect of the present invention, the length of the connecting portion is surely shortened as compared with the case where both connecting terminal groups are connected via wire bonding. Therefore, the inductance is reduced and the delay of the signal propagation speed is prevented. In addition, since wire bonding is not performed, it is not necessary to arrange both connection terminal groups side by side,
Moreover, the process can be simplified.

According to the second aspect of the invention, the accommodation space in the penetrating state is easier to process than the case where a non-penetrating state is formed. According to the third aspect of the present invention, if the accommodation space is a recess which is in a non-penetrating state, the wiring can be drawn even in the central portion of the printed wiring board, so that the dead space becomes smaller. Further, in this case, the input / output terminals can be provided on the entire printed wiring board, and the sealing with a sealing cap or the like becomes unnecessary.

According to the fourth aspect of the present invention, since the interface between both connecting terminal groups is sealed by the anisotropic conductive adhesive that surrounds the housing space, the need for resin sealing the interface is reduced.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION [First Embodiment] Hereinafter, an embodiment in which the present invention is embodied in a semiconductor package 11 will be described in detail with reference to FIGS.

As shown in FIG. 3, the semiconductor package 11 of this embodiment is basically composed of a PGA type base unit 25 and a multilayer thin film wiring board 12 as a radiator.

As shown in FIGS. 3 and 4, the multilayer thin-film wiring board 12 is formed by using a tough pitch copper plate 13 as a base material made of a material having high thermal conductivity as a base. The entire one side surface of this tough pitch copper plate 13 is a heat dissipation area,
In addition, the entire opposite side surface is an electronic component mounting area. A build-up multilayer wiring layer B1 is formed as a high-density and thin wiring layer over the entire electronic component mounting area. In this embodiment, the build-up multilayer wiring layer B1
Has a structure in which an insulating layer 14 and an extremely fine wiring pattern 15 are alternately laminated. The wiring patterns 15 of the respective layers are connected to each other by via holes 16 formed in the insulating layer 14.

As shown in FIGS. 3 and 4, a plurality of die pads 17 as electronic component mounting portions are provided on the build-up multilayer wiring layer B1. LSI chips 18 and 19 as electronic components are mounted on the die pad 17. The LSI chips 18 and 19 and the bonding pad 20 on the build-up multilayer wiring layer B1 are electrically connected via a bonding wire 21. The LSI chips 18 and 19 may be connected to the buildup multilayer wiring layer B1 via bumps.
On the outer peripheral portion of the upper surface of the build-up multi-layer wiring layer B1, a large number of pads 2 as connection terminals constituting the first connection terminal group are formed.
2 are laid out regularly. The LSI chips 18 and 19 and the pad 22 are electrically connected to each other via the wiring pattern 15 on the inner layer or the outer layer of the buildup multilayer wiring layer B1. In this embodiment, the width of the pads 22 is 0.3 mm, and the space between the pads 22 is 0.2 mm.

The base unit 25, which is a member for mounting a radiator, is manufactured using a printed wiring board 25a whose main material is a plastic plate material (copper clad laminate made of glass epoxy in this embodiment). . Basically, this type of plate material is easier to process than ceramics or metal. A so-called four-layer board having four conductor layers is used as the printed wiring board 25a of the present embodiment.

As shown in FIGS. 1 and 2, one square through window 26 as an accommodation space is formed in the center of the printed wiring board 25a constituting the base unit 25. The multilayer thin film wiring board 12 is mounted in one opening of the through window 26 with the surface side on which the buildup multilayer wiring layer B1 is formed facing the printed wiring board 25a side. At that time, the outer peripheral portion of the multilayer thin film wiring board 12 is wholly supported by the printed wiring board 25a. The outer dimensions of the through window 26 are smaller than the outer dimensions of the multilayer thin film wiring board 12 by 1 mm to 2 mm. If the difference in size between the two is too small, the area of the supported portion is reduced, so that the multilayer thin film wiring board 12 may not be reliably attached. On the other hand, if the difference in size between the two is too large,
While the area of the supporting portion increases, there is a disadvantage that the electronic component mounting area decreases.

Here, the through window 26 as the accommodation space is provided.
Is preferably larger than at least the height of the LSI chips 18, 19 (including the bonding wire 21) on the build-up multilayer wiring layer B1. In the present embodiment, since the four-layer board is used as the printed wiring board 25a, the dimension of such depth is sufficiently secured in advance.

As shown in FIG. 1, a large number of pads 30 serving as connection terminals constituting the second connection terminal group are laid out around the through window 26 so as to surround the through window 26 from four sides. ing. The positions of these pads 30 correspond to the positions of the pads 22 that form the first connection terminal group. In this embodiment, the width of the pads 30 is 0.3 mm, and the space between the pads 30 is 0.2 mm.
mm. The printed wiring board 2 is provided around each pad 30.
A large number of through holes 28 penetrating the front and back surfaces of 5a are formed. A metal I / O pin 29 as an input / output terminal is fitted into each through hole 28. The tip of each I / O pin 29 projects from the surface side where the pad 30 forming the second connection terminal group is not provided.

The pad 30 and the land 31 of the through hole 28 are electrically connected via a wiring pattern 32. In addition, the pad 30 on the base unit 25 side
And the pad 22 on the multilayer thin film wiring board 12 side are thin (thickness of about 15 μm to 100 μm) anisotropic conductive adhesive 3
3 are electrically connected. The anisotropic conductive adhesive 33 is provided so as to completely surround the through window 26. The surface of the base unit 25 on which the wiring pattern 32 is formed is covered with a solder resist 34 for protecting the wiring pattern 32 from moisture and the like.

The anisotropic conductive adhesive 33 is electrically different from the anisotropic conductive adhesive 33 in that it is electrically conductive in the thickness direction of the adhesive and insulative in the direction orthogonal to the thickness direction (plane direction). This refers to an adhesive material that becomes anisotropic. A film-like adhesive is used as such an adhesive. It is easy to handle and easy to attach. As shown in FIGS. 5A and 5B, such an anisotropic conductive adhesive 33 has conductive particles 33b in a thermosetting adhesive 33a.
Are evenly dispersed. Here, the conductive particles 33b
Examples thereof include metal particles and metal-coated resin particles. As the metal particles, for example, a relatively soft and conductive metal such as solder is used. As the metal-coated resin particles, for example, resin particles plated with solder or nickel / gold are used.

Anisotropically conductive adhesive 3 containing metal-coated resin particles
3 is suitable for achieving fine pitch and high insulation reliability as compared with the anisotropic conductive adhesive 33 containing metal particles. On the contrary, the anisotropic conductive adhesive 33 containing metal particles is more cost effective than the anisotropic conductive adhesive 33 containing metal-coated resin particles. The adhesive 33a may be a mixed system of thermosetting resin and thermoplastic resin. In this way, the preferable connection reliability of the thermosetting resin,
This is because the adhesive 33a has the suitable workability (repairability, long-term storage property, etc.) of the thermoplastic resin.

When the anisotropic conductive adhesive 33 is used, at least one of the pads 22 and 30 facing each other is preferably projected from the upper surface of the surrounding resin. More specifically, the opposing pads 22, 30
At least one of them is preferably a conductor pattern formed by a subtractive process. This is because if the pads 22 and 30 are lower than the resin surface, the pressure is less likely to be concentrated between the pads 22 and 30 when the anisotropic conductive adhesive 33 is permanently bonded, and reliable connection may not be achieved. .

As shown in FIG. 3, the semiconductor package 11 of the present embodiment is mounted by a I / O pin 29 on a mother board (not shown) in a face-down manner. That is, the heat dissipation area faces upward (outward) and the electronic component mounting area faces downward (inward) during mounting. And in this semiconductor package 11,
The entire one surface of the tough pitch copper plate 3 is a surface that is involved in heat dissipation. In this case, the four side surfaces of the tough pitch copper plate 3 also become surfaces involved in heat dissipation. LSI chip 1
The heat of 8 and 19 is efficiently dissipated to the outside via these surfaces, so that the thermal destruction of the LSI chips 18 and 19 is prevented.

As shown in FIGS. 3 and 4, potting resin 36 seals the electrical connection between the LSI chips 18 and 19 side and the multilayer thin film wiring board 12 side. In this embodiment, an epoxy resin having a viscosity of 1500 cps to 2500 cps (Kyushu Matsushita, trade name: CCN2001-23P) is used as the potting resin 36. Specifically, the electrical connection portion refers to the bonding pad 20, the bonding pads (not shown) on the upper surfaces of the LSI chips 18 and 19 and the bonding wire 21 connecting them. The electrically connecting portion between the base unit 25 side and the multilayer thin film wiring board 12 side is sealed by the anisotropic conductive adhesive 33. Regarding this part, if necessary, the potting resin 36
May also be performed together.

A metallic sealing cap 37 is bonded to the pin projecting surface side of the printed wiring board 25a with an adhesive agent and solder (not shown). As a result, one of the openings in the through window 26 is closed. Therefore, the area defined by the sealing cap 37, the inner wall surface of the through window 26 and the buildup multilayer wiring layer B1 is a hermetically sealed area.

Next, an example of a procedure for manufacturing the semiconductor package 11 will be introduced. First, the semiconductor package 11
The multi-layered thin film wiring board 12 constituting the above is manufactured as follows. One surface of the tough pitch copper plate 13 as a starting material is blackened by a conventionally known method, and a photosensitive epoxy resin is applied on the blackened surface. Then, by performing exposure and development, an insulating layer 14 having a thickness of 15 μm having a via hole forming hole having an inner diameter of 40 μm is formed. 0.1 μm thick on the insulating layer 14 by sputtering
A thin Cr layer of 0.2 μm thick is formed by further forming a thin Cr layer of No. 2 and then sputtering. L
A plating resist for forming the wiring pattern 15 of / S = 25 μm / 25 μm is arranged on the Cu thin layer. In this state, electrolytic Cu plating and electrolytic Ni plating are sequentially performed to form a Cu plating layer having a thickness of 6 μm and a Ni plating layer having a thickness of 1 μm, respectively. After removing the plating resist, the Cu thin layer and the Cr thin layer in the non-plated portion are etched using a cupric chloride solution and a 20% hydrochloric acid aqueous solution. Then, the insulating layer 14 and the wiring pattern 15 made of a plurality of kinds of metals are alternately formed by repeating the above steps as needed. As a result, the wiring pattern 15
Multi-layer thin film wiring board with 4 layers (35mm square, 1.0mm thickness)
12 are produced. Then, after this, the multilayer thin film wiring board 1
Conduct 2 open / short tests.

On the other hand, the base unit 25 is manufactured as follows. First, patterning is performed according to a conventionally known additive process to produce an inner layer substrate (54 mm square) 38 having inner layer conductor patterns on both surfaces. This inner layer substrate 38 is used as a core material, and a copper clad laminate is laminated on both surfaces of the core substrate 38 with prepregs interposed therebetween. Then, by drilling the outer peripheral portion, a through-hole forming hole for inserting an I / O pin is formed. After applying the catalyst nuclei and activating the catalyst nuclei, electroless Cu plating is performed to deposit Cu in the through-hole forming holes. Through-bore processing (31 mm square) is performed to form a through-window 26 in the central portion. Electrolytic Cu plating is performed in a state where a plating resist is arranged on a predetermined portion, to deposit Cu on a necessary portion. After removing the plating resist, unnecessary Cu is etched. Through this etching, through holes 28, pads 30, and wiring patterns 32 are formed.
After this, the land 31 of the through hole 28 and the pad 30
After the other parts are covered with the solder resist 34, the I / O pins 29 are fitted into the through holes 28. And
After this, an open / short test of the base unit 25 is performed. An uncured film-shaped anisotropic conductive adhesive (manufactured by Hitachi Chemical Co., Ltd., trade name: Anisolm AC-7104) 33 is preliminarily adhered to the base unit 25 that has passed the open / short test. In addition, temporary adhesion is performed at about 80 ° C, 1
It is performed under the conditions of MPa and 5 minutes. As shown in FIG. 6A, the film-shaped anisotropic conductive adhesive 33 is still protected by the release film 39 at this time.

Multilayer thin film wiring board 1 for base unit 25
The attachment of No. 2 is performed as follows. First, the release film 39 is peeled off to expose the film-shaped anisotropic conductive adhesive 33 to the outside (see FIG. 6B). Next, the pads 30 on the base unit 25 side and the pads 22 on the multilayer thin film wiring board 12 side are aligned. After this,
Film-shaped anisotropic conductive adhesive 3
The main bonding of No. 3 (around 170 ° C., 2 MPa, 20 seconds) is performed to bond both pads 22 and 30. At this time, the pressure is concentrated between the pads 22 and 30, so that the conductive particles 33b existing in that portion are plastically deformed. Then, the pads 22 and 30 facing each other have the conductive particles 3
It is electrically connected via 3b (see FIG. 7 (b)). In this case, since the pressure does not concentrate so much in the space between the pads 22 and 30, the conductive particles 33 in that portion are not concentrated.
No plastic deformation occurs in b. Therefore, the pads 22, 3
The space between 0s remains non-conducting.

Next, using the die bonder, the tested LSI chip 18 for the CPU is mounted on the die pad 17.
6 and memory LSI chips 19 are mounted. Here, a wire bonding device (made by Kyushu Matsushita, trade name: H
W-2200) is used to wire-bond the LSI chips 18 and 19. The wire bonding step may be performed before the step of mounting the multilayer thin film wiring board 12 on the base unit 25. However, performing the wire bonding process after the mounting process is advantageous in that the risk of the bonding wire 21 deforming is reduced. And
Finally, the electrical connection portion is sealed by performing resin sealing by the potting method. Semiconductor package 11
Is manufactured through the above procedure.

Now, the semiconductor package 11 of the present embodiment.
The characteristic effects of the above are listed below. (A) In this semiconductor package 11, the pad 22 on the side of the multilayer thin film wiring board 12 forming the first connection terminal group and the pad 30 on the side of the base unit 25 forming the second connection terminal group are film-shaped. It is electrically connected via the anisotropic conductive adhesive 33. Therefore, as compared with the case where both pads 22 and 30 are connected by wire bonding,
The length of the connecting portion is surely shortened (L1 in Figs. 7 (a) and 7 (b)).
, L2). That is, in the conventional case, the length L1 of the connecting portion is
Is about several mm, whereas the length L2 of the connection portion is extremely short, about several .mu.m to ten and several .mu.m, in this embodiment. This is because the film-shaped anisotropic conductive adhesive 33 having a thickness of several tens of μm is used originally. As a result, the inductance is reduced and the delay of the signal propagation speed is prevented. Therefore, the speedup of the semiconductor package 11 can be achieved.

Further, since the film-shaped anisotropic conductive adhesive 33 is used in the electrical connection portion, the difficult wire bonding work is unnecessary, and the process can be simplified and the manufacturing can be facilitated. Of course, since such a joint structure can be formed without being greatly influenced by the space between the pads 22 and 30, the pitch is extremely suitable for narrowing the pitch.
Furthermore, this joint structure also eliminates the need for soldering, so that it is possible to avoid the use of Pb, which causes environmental deterioration. In addition, since the connection by solder or the like is not performed, it is not necessary to set the process sequence in consideration of the remelting of the solder, and the manufacturing is facilitated also in this respect.

(B) In this semiconductor package 11, the pads 22 and the base unit 25 on the multilayer thin film wiring board 12 side are provided.
The pad 30 on the side is not arranged so as to be aligned in the lateral direction. That is, they are arranged side by side in the thickness direction (that is, so as to face each other). Therefore, it is not necessary to previously provide a region where the pad 30 is to be formed on the printed wiring board 25a, and it is possible to reduce the outer size of the semiconductor package 11 as compared with the conventional case.

(C) In this semiconductor package 11, in addition to the entire one surface of the tough pitch copper plate 3, four side surfaces are surfaces that are involved in heat dissipation. Therefore, the heat dissipation area is further increased as compared with the conventional type shown in FIG. 14, and as a result, the heat dissipation of the semiconductor package 11 is improved.

(D) In this semiconductor package 11, a through window 26 penetrating the central portion of the printed wiring board 25a is formed as a housing space. Such a through hole has an advantage in manufacturing that it is easier to process than a case where a non-through hole is formed. This also facilitates manufacturing.

(E) In this semiconductor package 11, the outer dimensions of the through window 26 are smaller than the outer dimensions of the multilayer thin film wiring board 12 by 1 mm to 2 mm, the pad 30 is formed around it, and the anisotropic conductive adhesive 33 is used. Are provided so as to completely surround the through window 26. Therefore, the interface between the multilayer thin film wiring board 12 and the base unit 25 is sealed by the film-shaped anisotropic conductive adhesive 33 itself. In this case, since the film-shaped anisotropic conductive adhesive 33 provides a suitable sealing property, the necessity of resin-sealing the interface between the both 12 and 25 becomes smaller than in the conventional case. Therefore, for example, by omitting the resin sealing of that portion, further simplification of the process can be achieved. In addition, the fact that the resin sealing at the interface is unnecessary also has a positive effect in achieving a reduction in external size. That is, since the problem of the expansion of the potting resin 36 for sealing cannot occur, it is not necessary to provide a space in consideration of the expansion. [Second Embodiment] Next, a semiconductor package 41 of a second embodiment will be described with reference to FIG. The same parts as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

In the central portion of the base unit 42 in this embodiment, a square through window 43 is formed as in the first embodiment. However, this through window 43
The inner wall surface is provided with a step portion 43a over the entire circumference thereof. The size of the opening in the through window 43 on the side where the multilayer thin film wiring board 12 is mounted is substantially equal to the outer diameter dimension of the multilayer thin film wiring board 12. In addition, the size of the other opening is 1 mm to the outer diameter of the multilayer thin film wiring board 12.
It is 2 mm smaller. Therefore, when the multi-layered thin film wiring board 12 is fitted, the outer edge of the lower surface of the multi-layered thin film wiring board 12 is the step portion 4.
Supported by 3a. On the entire upper surface of the stepped portion 43a,
A plurality of pads 30 forming the second connection terminal group are formed. These pads 30 are used for the printed wiring board 25.
In a, it belongs to the second conductor layer (that is, the inner conductor pattern) from the top. The pad 30 and the pad 22 on the multilayer thin film wiring board 12 side are electrically connected via a film-like anisotropic conductive adhesive 33. The semiconductor package 41 can be manufactured basically through the same procedure as in the first embodiment.

Now, the semiconductor package 41 as described above is used.
However, since the basic configuration is the same as that of the first embodiment, it is obvious that the same operational effect is achieved. The characteristic effects of this embodiment will be described below.

(A) Since the through window 26 into which the multilayer thin film wiring board 12 can be fitted is provided, the protruding portion from the semiconductor package 41 is reduced. Therefore, the thickness can be reduced.

(B) At the time of fitting, the multilayer thin film wiring board 12 is positioned by the inner wall surface of the through window 26. Therefore, even if the joint portion between the pads 22 and 30 is not visible, the multilayer thin film wiring board 12 can be positioned easily and reliably. [Third Embodiment] Next, a semiconductor package 51 according to a third embodiment will be described with reference to FIG.

In the central portion of the base unit 52 in this embodiment, a square recess 53 that does not penetrate the front and back surfaces of the printed wiring board 25a is provided as a storage space. The depth of the recess 53 is set so that the LSI chips 18 and 19 which are electronic components and the bonding wire 21 bonded thereto are accommodated. Except for the above, the same configuration as that of the first embodiment is adopted. The semiconductor package 51 can be manufactured basically through the same procedure as in the first embodiment. However, the step of mounting the multilayer thin film wiring board 12 on the base unit 52 needs to be performed after the wire bonding step of the LSI chips 18 and 19.

Now, the semiconductor package 51 as described above is used.
However, since the basic configuration is the same as that of the first embodiment, it is obvious that the same operational effect is achieved. The characteristic effects of this embodiment will be described below.

(A) Since the recess 53, which is the accommodation space, is in the non-penetrating state, the inside of the recess 53 is in a suitable sealed state without providing the sealing cap 37 in the opening on the pin projecting surface side. Therefore, the number of parts is reduced and the structure is simplified. In this case, the potting resin 36 does not need to be sealed for the same reason.

(B) Since the wiring can be drawn also in the central portion of the printed wiring board 25a, the dead area is further reduced, and the miniaturization is achieved. (C) The I / O pin 54 can be provided not only in the outer peripheral portion of the back surface of the printed wiring board 25a but also in the central portion of the back surface. Therefore, it is possible to achieve a large number of pins while avoiding an increase in the size of the semiconductor package 51. [Fourth Embodiment] Next, a semiconductor package 61 of a fourth embodiment will be described with reference to FIG. In the case of this semiconductor package 61, a large number of pads 62 are formed on the outer peripheral surface of the back surface of the printed wiring board 25a forming the base unit 25. Then, on these pads 62, solder bumps 63 are protrudingly provided as input / output terminals replacing the I / O pins 29. Except for the above, the same configuration as that of the first embodiment is adopted. The semiconductor package 61 is basically the first package.
It can be manufactured through a procedure similar to that of the above embodiment.
In this case, the solder bumps 63 can be joined before or after the step of mounting the multilayer thin film wiring board 12 on the base unit 25. Even the semiconductor package 61 as described above has the same basic configuration as that of the first embodiment, and therefore, it is obvious that the semiconductor package 61 has the same operational effect. [Fifth Embodiment] Next, a semiconductor package 71 according to a fifth embodiment will be described with reference to FIG. In the case of this semiconductor package 71, a non-penetrating recessed portion 74 as a housing space is formed in the central portion of the printed wiring board 25a forming the base unit 72. This recess 74
Projections 73 are provided at a plurality of locations on the bottom surface of the.
On the upper surface of these protrusions 73, some pads 30 that form the second connection terminal group are provided. Further, in this semiconductor package 71, the pads 22 are also arranged at positions other than the outer edge of the buildup multilayer wiring layer B1. Then, these pads 22 and the pads 30 of the protruding portions 73 are electrically connected via the anisotropic conductive adhesive 33. Except for the above, the same configuration as that of the first embodiment is adopted. In addition, this semiconductor package 71 can be manufactured basically through the same procedure as in the first embodiment. The protruding portion 73 can be formed, for example, by leaving only a predetermined portion when the printed wiring board 25a is counterbored.

Now, the semiconductor package 71 as described above is used.
However, since the basic configuration is the same as that of the first embodiment, it is obvious that the same operational effect is achieved. The characteristic effects of this embodiment will be described below.

(A) Since the recess 74, which is the accommodation space, is in the non-penetrating state, the inside of the recess 74 is in a suitable sealed state without providing the sealing cap 37 in the opening on the pin projecting surface side. Therefore, the number of parts is reduced and the structure is simplified. In this case, the potting resin 36 does not need to be sealed for the same reason.

(B) Since the wiring can be drawn also in the central portion of the printed wiring board 25a, the dead area is further reduced, and the miniaturization is achieved. (C) The I / O pin 54 can be provided not only in the outer peripheral portion of the back surface of the printed wiring board 25a but also in the central portion of the back surface. Therefore, it is possible to achieve a large number of pins while avoiding an increase in the size of the semiconductor package 71.

(D) Since the protrusions 73 are provided in the recesses 74 and the pads 30 are provided thereon, the pads 22 should be laid out at a place other than the outer edge of the upper surface of the build-up multilayer wiring layer B1. You can Therefore, it is not necessary to forcibly lay out a large number of pads 22 only on the outer peripheral portion of the upper surface, and the size reduction of the semiconductor package 71 can be easily achieved accordingly. Further, with this configuration, the wiring length in the build-up multilayer wiring layer B1 is shortened, so that further speedup can be achieved. [Sixth Embodiment] Next, a semiconductor package 81 according to a sixth embodiment will be described with reference to FIG. In this semiconductor package 81, the anisotropic conductive adhesive 33 is also used for electrical connection between the LSI chips 18 and 19 and the build-up multilayer wiring layer B1. In this case, a large number of pads (not shown) are formed on the back surfaces of the LSI chips 18 and 19, and a large number of pads (not shown) are formed in the die area on the build-up multilayer wiring layer B1 so as to face them. It Of course, this semiconductor package 81 is basically the first
It can be manufactured through a procedure similar to that of the above embodiment.

Now, the semiconductor package 81 as described above is used.
However, since the basic configuration is the same as that of the first embodiment, it is obvious that the same operational effect is achieved. The characteristic effects of this embodiment will be described below.

(A) Bonding wire 2 for connecting the LSI chips 18, 19 and the buildup multilayer wiring layer B1
1 is omitted and the anisotropic conductive adhesive 33 is used instead. For this reason, the length of the connection portion is shortened, which in turn leads to higher speed of the semiconductor package 81.

(B) Since wire bonding is not adopted as a method of electrical connection, the manufacturing disadvantages associated therewith are eliminated, and the semiconductor package 81 is easier to manufacture. [Seventh Embodiment] Next, a semiconductor package 91 of a seventh embodiment will be described with reference to FIG. In this semiconductor package 91, the pads 22 and 30 are electrically connected to each other through a square-shaped anisotropic conductive adhesive 33. A void is formed between the film-like anisotropic conductive adhesive 33 and the build-up multilayer wiring layer B1, and the LSI chips 18 and 19 are just accommodated in the void. The anisotropic conductive adhesive 33 cuts off the flow of air in and out of the voids to achieve a certain degree of sealing. That is, in this embodiment, the film-shaped anisotropic conductive adhesive 33 itself plays a role similar to that of the potting resin 36. Now, even the semiconductor package 91 as described above has the same basic configuration as that of the first embodiment, and therefore, it is obvious that the same operational effect is achieved.

The present invention can be modified, for example, as follows. (1) As the anisotropic conductive adhesive 33, one containing metal particles may be used. (2) The printed wiring board 25a may be a double-sided board or a single-sided board, or conversely may be a multilayer board having five or more layers.

(3) When manufacturing the multilayer thin film wiring board 12 which is a radiator, the tough pitch copper plate 1 used in each embodiment
Besides 3, it is of course possible to use a metal plate such as a phosphor bronze plate, an aluminum plate, and an alumite plate.
Further, it is not limited to the metal plate, and it is possible to use a ceramics substrate such as an alumina plate, a mullite plate, a silicon nitride plate, a boron nitride plate or the like. It should be noted that these plate materials do not necessarily have to be completely plate-shaped, and for example, the surface on the heat dissipation area side may have some irregularities.

(4) The shapes of the through windows 26, 43 and the recesses 53, 74, which are the accommodation spaces, are not limited to the square shape, but can be changed to other shapes. in this case,
Minimize the size of the accommodation space (LSI chip 18,
It is preferable to make the size larger than 19) because it leads to a further reduction in dead area.

Here, in addition to the technical ideas described in the claims, the technical ideas grasped by the above-described embodiment will be listed below together with their effects. (1) In Claims 2 and 3, a step portion for supporting the radiator is provided on an inner wall surface of the accommodation space, and a second connection terminal group is provided on an upper surface of the step portion. With this configuration,
It is possible to achieve thinner semiconductor packages and
Positioning during mounting becomes easy.

(2) In any one of claims 3 and technical idea 1, a protrusion is provided in the recess which is the accommodation space, and the second connection terminal group is also provided on the upper surface thereof. With this configuration, it is possible to further reduce the size and speed of the semiconductor package.

(3) In any one of claims 1 to 4, the anisotropic conductive adhesive is also used for electrical connection between the electronic component and the build-up multilayer wiring layer. With this configuration, it is possible to achieve higher speed and easier manufacturing.

(4) A heat radiator mounting base unit to which a heat radiator having a built-up multi-layer wiring layer is mounted, wherein an input / output terminal group provided on one side surface of the printed wiring board and an opposite side surface thereof are provided. An accommodating space for accommodating electronic components provided in a substantially central portion, a connecting terminal group provided in the vicinity of the accommodating space on the opposite side surface, and an uncured film-like film covering the connecting terminal group. A base unit comprising a unidirectional conductive adhesive and a release sheet for protecting the film-shaped anisotropic conductive adhesive. With this configuration, since the film-shaped anisotropic conductive adhesive is preliminarily adhered,
The package can be manufactured more easily.

The technical terms used in this specification are defined as follows. "High thermal conductivity material: A material having a higher thermal conductivity than a plastic material, for example, a ceramic material such as aluminum nitride, alumina, or mullite, or a metal material such as copper or aluminum."

[0065]

As described above in detail, according to the inventions described in claims 1 to 4, it is possible to provide a small-sized and high-speed semiconductor package which is easy to manufacture. According to the second aspect of the present invention, since the accommodation space is formed so as to penetrate therethrough, it is possible to further facilitate manufacturing. According to the invention described in claim 3, since the accommodation space is a non-penetrating recess, it is possible to obtain a suitable sealing property without using a sealing cap or the like. According to the invention described in claim 4, it is possible to obtain a suitable sealing property without performing resin sealing of the interface between both connection terminal groups.

[Brief description of drawings]

FIG. 1 is a plan view showing a base unit used in a semiconductor package according to a first embodiment.

FIG. 2 is a bottom view showing the base unit.

FIG. 3 is a partially cutaway schematic cross-sectional view showing the semiconductor package of the first embodiment.

FIG. 4 is an enlarged partial sectional view of the same main portion.

5A and 5B are partial schematic cross-sectional views for explaining a method of joining the connection terminal groups.

6A and 6B are plan views showing the base unit when in use.

7A and 7B are enlarged schematic cross-sectional views of a main part for comparing the connection portion of the conventional semiconductor package and that of the first embodiment.

FIG. 8 is a partial schematic cross-sectional view showing the semiconductor package of the second embodiment.

FIG. 9 is a partial schematic sectional view showing a semiconductor package of a third embodiment.

FIG. 10 is a partial schematic cross-sectional view showing a semiconductor package of a fourth embodiment.

FIG. 11 is a partial schematic cross-sectional view showing a semiconductor package of a fifth embodiment.

FIG. 12 is a partial schematic cross-sectional view showing a semiconductor package of a sixth embodiment.

FIG. 13 is a partial schematic cross-sectional view showing a semiconductor package of a seventh embodiment.

FIG. 14 is a partially cutaway schematic sectional view showing a conventional semiconductor package.

[Explanation of symbols]

11, 41, 51, 61, 71, 81, 91 ... Semiconductor package, 12 ... Multi-layer thin film wiring board as heat radiator, 13
... a tough pitch copper plate as a plate made of a high thermal conductive material, 17 ... a die pad as an electronic component mounting portion, 18,
19 ... LSI chip as electronic component, 22 ... Pads constituting first connection terminal group, 25, 42, 52, 72 ...
Base unit, 25a ... Printed wiring board, 26, 43
... Through windows as accommodating spaces, 53, 74 ... Recesses as accommodating spaces, 29, 54 ... I / O configuring input / output terminal groups
Pins 30, 62 ... Pads forming second connection terminal group, 33 ... Film-like anisotropic conductive adhesive, 63 ... Solder bumps forming input / output terminal group, B1 ... Build-up multilayer wiring layer.

Claims (4)

[Claims] 1. A build-up multilayer wiring layer is provided on one side surface of a plate material made of a high thermal conductive material, and an electronic component mounting portion for mounting electronic components and a first connection terminal group are provided on the wiring layer. A heat dissipating body and a housing space in which the electronic component can be housed are provided substantially at the center of the opposite side of a printed wiring board having an input / output terminal group on one side, and the first space is provided near the housing space. A second connection terminal group that is electrically connected to the connection terminal group is provided, and the heat dissipation body is mounted with the heat dissipation body with the side surface of the buildup multilayer wiring layer facing the printed wiring board side. A semiconductor package including a base unit for use in a semiconductor package, wherein the first connection terminal group and the second connection terminal group are electrically connected via an anisotropic conductive adhesive. 2. The semiconductor package according to claim 1, wherein the housing space penetrates the printed wiring board. 3. The semiconductor package according to claim 1, wherein the accommodation space is a recess that does not penetrate the printed wiring board. 4. The outer dimension of the accommodation space is smaller than the outer dimension of the radiator by 1 mm to 2 mm, and the second portion is provided around the outer dimension.
2. The connection terminal of claim 2 is formed, and the anisotropic conductive adhesive is provided so as to surround the accommodation space.
The semiconductor package described in.