JP3256040B2 - Semiconductor package - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates to a semi-conductor package.

[0002]

2. Description of the Related Art Generally, an electrical connection between an IC chip or an LSI chip and a printed wiring board as a motherboard is made via a semiconductor package. In recent years, resin-sealed semiconductor packages (so-called plastic packages) have become the mainstream.

When manufacturing a plastic package, it is necessary to reliably dissipate the heat generated by the LSI chip in order to prevent malfunction and thermal destruction of the LSI chip. Therefore, in the conventional plastic package, for example, a measure is taken to dispose a radiator, which is a plate made of a high heat conductive material such as Cu-W, on the back surface side of the chip mounting portion.

[0004]

However, when a large heat radiator is used to secure a large heat radiating area in the package, the area where the wiring cannot be formed (dead area) corresponds to the area of the heat radiating area. Will increase. For this reason, there has been a problem that the size of the entire package must be increased, and as a result, electrical characteristics such as a reduction in signal propagation speed are deteriorated.

Conversely, if the dead area is reduced as much as possible to maintain the current package size, the heat radiator must be reduced, and as a result, a sufficient heat radiating area cannot be secured.

In addition to using a radiator,
For example, it is conceivable to replace the substrate itself constituting the plastic package with a high heat conductive material such as metal such as Cu or ceramics.

However, in the case of such a package, since a material harder than a plastic material is used for the substrate, it has been difficult to perform substrate processing such as drilling. Further, in the case of the package, it is difficult to form fine wiring on the surface of metal or ceramic. For this reason, there has been a problem that the package is increased in size and cost is increased.

[0008] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an inexpensive and compact heat-dissipating material.
It is to provide a simple semiconductor package.

[0009]

[0010]

According to the first aspect of the present invention, a plastic material is provided.
In the semiconductor package comprised of a base unit which is formed from the heat radiating body and which is mounted on the base unit
The radiator has a heat dissipation area on one side of a plate made of a material having high thermal conductivity and an electronic component mounting area having a high-density wiring layer on the opposite side, and mounts electronic components on the high-density wiring layer. the provided parts, arranged a plurality of connection terminals electrically connected to the electronic component side through the high-density wiring layer at the outer edge of the electronic component mounting region, the base unit
The heat radiation area of the heat radiator is exposed to the outside at almost the center of
Windows to allow multiple entry and exits around the windows
Force terminal, and the connection terminal side of the radiator and the base
That the input and output terminals of the base unit are electrically connected
The gist is a semiconductor package characterized by the following.

According to the second aspect of the present invention, the first aspect of the present invention is provided.
In the semiconductor package described above, a step is formed on the inner wall surface of the window.
The upper surface of the step portion and the inner wall surface of the window portion form
The gist is that the heat radiator is fitted to the housing .

[0012]

In the case of the first aspect of the present invention, since the wiring layer formed on one side of the plate material has a high density, even when the semiconductor package is formed together with the base unit, the area of the heat radiator is formed on the surface thereof. There is no dead area corresponding to. Therefore, it is necessary to secure a sufficient heat dissipation area without increasing the size of the entire package (ie,
(A large heat radiator can be used.)

Further, when mounting the heat radiator to base Suyunitto, a state in which the heat radiation region of the radiator is exposed largely through the window. Therefore, the heat conducted from the electronic component mounting area, which is the back surface of the heat dissipation area, to the heat dissipation area can be efficiently dissipated into the atmosphere through the window. This semiconductor package can be manufactured at low cost and can be made compact as a whole.

Further, according to the structure of the invention described in claim 2,
When a step is provided on the inner wall surface of the window, and the radiator is fitted into the housing formed by the upper surface of the step and the inner wall of the window, the radiator can be securely fixed to the base unit. . In addition, with such a configuration, the step on the surface of the heat radiator and the surface of the base unit are reduced, so that, for example, bonding for connecting the both becomes easy, and the semiconductor package becomes thin.

[0015]

[Embodiment 1] Hereinafter, a semiconductor package according to a first embodiment of the present invention will be described in detail with reference to FIGS.

As shown in FIG. 3, the semiconductor package 1 according to the present embodiment basically has a base unit 15 of a PGA type and a build-up multilayer thin film wiring board 2 serving as a radiator.
And is constituted by.

As shown in FIG. 4, the build-up multilayer thin-film wiring board 2 as a radiator is mainly formed of a phosphor bronze plate 3 as a plate made of a material having a high thermal conductivity. The entire one side of the phosphor bronze plate 3 is a heat dissipation area, and the entire opposite side is an electronic component mounting area. A build-up layer B as a high-density wiring layer is formed in the entire electronic component mounting area. In the present embodiment, the build-up layer B has a configuration in which insulating layers 4 and extremely fine wiring patterns 5 are alternately laminated. The wiring patterns 5 of each layer are connected to each other by via holes 6 formed in the insulating layer 4.

As shown in FIG. 4, the build-up layer B
On the upper side, a plurality of die pads 7 as electronic component mounting portions are provided. On the die pad 7, LSI chips 8 and 9 as electronic components are mounted. LSI chips 8 and 9 and bonding pad 10 on build-up layer B
Are bonded via a bonding wire 11. The LSI chips 8, 9 are sealed with a potting resin or the like as necessary. A large number of connection pads 12 as connection terminals are regularly arranged on the outer edge of the build-up layer B. And the LSI chips 8, 9
The side and the connection pad 12 are electrically connected via the wiring pattern 5 of the inner layer or the outer layer of the buildup layer B.

The base unit 15 is formed mainly of a plastic material which is basically easy to process. As shown in FIGS. 1 and 2, a window 16 having an outer shape substantially equal to the outer shape of the build-up multilayer thin film wiring board 2 is provided in a substantially central portion of the base unit 15. As shown in FIGS. 1 and 3, a step portion 17 is provided on the inner wall surface of the window portion 16. The build-up multilayer thin-film wiring board 2 is fitted into an accommodation portion formed by the upper surface of the step portion 17 and the inner wall surface of the window portion 16. Around the window 16, a large number of through holes 18 penetrating the front and back are formed. In each through hole 18, a metal pin 19 as an input / output terminal is inserted.

As shown in FIG. 3, the connection pads 20 arranged to surround the window 16 and the lands 21 of the through holes 18 are electrically connected via the wiring pattern 22. . The connection pads 20 on the base unit 15 side and the connection pads 12 on the build-up multilayer thin-film wiring board 2 are joined via bonding wires 23. The surface of the base unit 15 where the wiring pattern 22 is formed is covered with a solder resist 24 for protecting the wiring pattern 22 from moisture and the like.
Covered by

As shown in FIGS. 3 and 4, when the build-up multilayer thin-film wiring board 2 is mounted on the base unit 15, the heat radiation area of the build-up multilayer thin-film wiring board 2
6 to the outside. The semiconductor package 1 according to the present embodiment is mounted on a motherboard (not shown) in a face-down manner by pins 19. That is, at the time of mounting, the heat radiation area is directed upward (outward), and the electronic component mounting area is directed downward (inward). The area of the heat dissipation region, more specifically, the area of the portion of the heat dissipation region exposed from the window 16 is the actual heat dissipation area of the semiconductor package 1.

Here, an example of a procedure for manufacturing the semiconductor package 1 will be introduced. The build-up multilayer thin-film wiring board 2 constituting the semiconductor package 1 is manufactured as follows. First, one surface of the phosphor bronze plate 3 as a starting material is blackened, and a photosensitive epoxy resin is applied thereon. Then, by performing exposure and development, an insulating layer 4 having a thickness of 15 μm and having a via hole formation hole having an inner diameter of 40 μm is formed. A Cr thin layer having a thickness of 0.1 μm is formed on the insulating layer 4 by sputtering, and a Cu thin layer having a thickness of 0.2 μm is further formed thereon by sputtering. A plating resist for forming the wiring pattern 5 of L / S = 25 μm / 25 μm is arranged on the Cu thin layer. In this state, electrolytic Cu plating and electrolytic Ni plating are sequentially performed, thereby forming a Cu plating layer having a thickness of 6 μm and a Ni plating layer having a thickness of 1 μm, respectively. After removing the plating resist, the Cu thin layer and the Cr thin layer in the non-plated portion are etched using a cupric chloride solution and a 20% hydrochloric acid aqueous solution. By repeating the above steps as necessary, the insulating layers 4 and the wiring patterns 5 made of a plurality of kinds of metals are alternately formed. As a result, a build-up multilayer thin film wiring board (3
(5 mm square, 1.0 mm thickness) 2 is manufactured.

On the other hand, the base unit 15 is manufactured as follows. First, an outer peripheral portion of a copper-clad laminate (50 mm square, 1.7 mm thick) having a plastic plate as a core is drilled to form through holes for inserting pins. After catalyst nucleation and activation, electroless Cu
By performing plating, Cu is precipitated in the through-hole forming holes. After counterboring (35 mm square, depth 1.0 mm) the approximate center of the copper-clad laminate, the same portion is further counterbored (31 mm square) to form a step 17.
Is formed. By performing electrolytic Cu plating in a state where a plating resist is arranged in a predetermined portion,
Precipitate Cu in the required portions. After stripping the plating resist, unnecessary Cu is etched. Through this etching, the through hole 18, the connection pad 20, and the wiring pattern 22 are formed. Thereafter, a solder resist 24 is formed so as to cover portions other than the lands 21 and the connection pads 20 of the through holes 18, and then the through holes 1 are formed.
Insert pin 19 into 8.

The base unit 15 and the build-up multilayer thin film wiring board 2 are adhered by an adhesive seal (manufactured by Mitsubishi Yuka, trade name: YEF-040) 25 disposed on the step 17 of the copper-clad laminate. Before the two 2 and 15 are bonded, an open / short test for each is performed in advance. Then, the tested CPU is mounted on the die pad 7.
1 LSI chip 8 for memory and 6 LSI chips 9 for memory
Are mounted and connected by bonding wires 11, respectively. Further, the connection pads 12 and 20 are connected to each other by a bonding wire 23. Finally, the LSI chips 8, 9 and the connection pads 12, 20 are individually sealed with a potting resin (not shown). Through the above procedure, the semiconductor package 1 as shown in FIGS. 3 and 4 is obtained.

In this embodiment, a build-up layer B, which is a high-density wiring layer, is formed on one side of the phosphor bronze plate 3 constituting the build-up multilayer thin film wiring board 2.
Therefore, even when the semiconductor package 1 is formed together with the base unit 15, a dead area corresponding to the area of the build-up multilayer thin-film wiring board 2 does not occur on the surface of the semiconductor package 1. Therefore,
A sufficient heat dissipation area can be secured without increasing the size of the entire semiconductor package 1. In addition, electrical characteristics are improved, such as an increase in signal propagation speed due to avoiding an increase in size. As the heat dissipation of the semiconductor package 1 is improved as described above, the LSI
Malfunction, thermal destruction, and the like of the chips 8 and 9 are extremely reduced as compared with the related art.

In this embodiment, the base unit 1
When the build-up multilayer thin-film wiring board 2 is mounted in the housing section 5, the heat radiation area on one side of the phosphor bronze board 3 is largely exposed from the window 16. Therefore, there is an advantage that heat conducted from the electronic component mounting area to the heat radiation area via the buildup layer B and the phosphor bronze plate 3 is efficiently radiated into the atmosphere through the window 16.

Further, in the case of the present embodiment, a step 17 is provided on the inner wall surface of the window 16, and the build-up multilayer thin-film wiring board 2 is provided in a housing formed by the upper surface of the step 17 and the inner wall surface of the window 16. Is to be fitted. For this reason, the base unit 1
5 can securely fix the build-up multilayer thin-film wiring board 2. With such a configuration, it is possible to eliminate a step on the surfaces of the build-up multilayer thin film wiring board 2 and the base unit 15. Accordingly, wire bonding for connecting the two 2 and 15 can be easily and reliably performed, and the thickness of the semiconductor package 1 can be reduced.

The present embodiment is characterized in that the build-up layer B is formed only on one side of the phosphor bronze plate 3. That is, since no through hole is formed in the phosphor bronze plate 3 itself, drilling is not required, and the overall manufacturing cost is reduced. Further, the semiconductor package 1 is characterized in that parts other than the build-up multilayer thin-film wiring board 2 at the center are easy to process and inexpensive plastic. Therefore, the manufacturing cost is lower than that of a conventional semiconductor package mainly composed of only metal or only ceramic.

Furthermore, the base unit 1 according to this embodiment
5, the build-up multilayer thin film wiring board 2 to be mounted
Can be exchanged according to the application. Therefore,
It is extremely versatile.

The present embodiment is characterized in that a plurality of LSI chips 8 and 9 are mounted on the build-up layer B of the build-up multilayer thin film wiring board 2. With such a configuration, the manufacturing process is simplified as compared with the conventional method in which it is necessary to attach a heat radiator to each individual chip. Further, by adopting this configuration, the dead space can be surely reduced.

The size of the semiconductor package 1 manufactured according to the above-described procedure is about 50% of that of the conventional type semiconductor package. Moreover,
The area of the heat radiation region reached about 70% of the area on one side of the semiconductor package 1. Therefore, it can be said that an extremely large heat radiation area is secured. Embodiment 2 Next, a semiconductor package according to Embodiment 2 will be described. Since the semiconductor package of the second embodiment and the semiconductor package 1 of the first embodiment do not have a particularly large difference in structure, description of such a point is omitted, and only the manufacturing procedure will be described.

In this embodiment, an AlN substrate (AlN: Y ₂ O ₃ = 9) is used as a starting material for a build-up multilayer thin film wiring board.
6: 4) is used. Ti, M on one side of AlN substrate
A thin film pattern made of o and Ni is formed, and a photosensitive epoxy resin is applied thereon. Then, by performing exposure and development, an insulating layer having a thickness of 23 μm having a hole for forming a via hole having an inner diameter of 50 μm is formed. A Cr thin layer having a thickness of 0.1 μm is formed on the insulating layer by sputtering, and a Cu thin layer having a thickness of 0.2 μm is formed thereon by sputtering. L / S = 50
A plating resist for forming a μm / 50 μm wiring pattern is arranged on the Cu thin layer. In this state, electrolytic Cu
By sequentially performing plating and electrolytic Ni plating, a Cu plating layer having a thickness of 10 μm and a Ni plating layer having a thickness of 2 μm are formed. After removing the plating resist, the Cu thin layer and the Cr thin layer in the non-plated portion are etched using a cupric chloride solution and a 20% hydrochloric acid aqueous solution. And
By repeating the above steps as necessary, insulating layers and wiring patterns made of a plurality of types of metals are alternately formed. As a result, a build-up multilayer thin film wiring board (30 mm square, 0.7 mm thickness) having five wiring patterns is manufactured.

On the other hand, the base unit is manufactured as follows. First, an outer peripheral portion of a copper-clad laminate (45 mm square, 1.4 mm thick) having a plastic plate as a core is drilled to form a through hole forming hole for pin insertion. After the catalyst nucleus is applied and activated, electroless Cu plating is performed, so that C is formed in the through hole.
u is precipitated. After counterboring (30 mm square, depth 0.7 mm) the approximate center of the copper clad laminate, the same portion is further counterbored (26 mm square) to form a window having a step. By performing electrolytic Cu plating in a state where a plating resist is arranged in a predetermined portion, C
u is precipitated. After stripping the plating resist, unnecessary Cu is etched. Through this etching, through holes, connection pads, and wiring patterns are formed. Thereafter, a solder resist is formed so as to cover portions other than the lands and the connection pads of the through hole, and pins are inserted into the through hole.

After performing a predetermined test, the base unit and the build-up multilayer thin-film wiring board are joined by an adhesive seal in the same manner as in the first embodiment. And C
One PU LSI chip and three LSI chips for memory
Each is mounted on a die pad and connected by a bonding wire. Further, the connection pads are connected by bonding wires. Finally, the LSI chip and the connection pad are individually sealed with a potting resin. 3 and 4 through the above-described procedure.
A semiconductor package having the same configuration as the semiconductor package 1 of the first embodiment shown in FIG.

The configuration of the semiconductor package of the second embodiment is almost the same as that of the semiconductor package 1 of the first embodiment. In the case of a semiconductor package manufactured according to the above-described procedure, its size is about 50% of the conventional type semiconductor package. Moreover, the area of the heat radiation region is about 75% of the area of one side of the semiconductor package.
It was also extended. Therefore, similarly to the first embodiment, it can be said that an extremely large heat radiation area is secured.

The present invention is not limited to the first and second embodiments, but may be modified as follows. For example, (a) As the material for forming the base unit , a material other than the plastic, for example, another material which is easy to process and is relatively inexpensive can be used.

(B) Of course, instead of the PGA type base unit , for example, a QFP type (that is, surface mount type) base unit may be used. In other words, based Uni
This means that the input / output terminal of the unit can be replaced by a pin or a lead.

(C) The number of LSI chips mounted on the heat radiator may be plural or one. In addition, it is of course possible to mount electronic components generating a large amount of heat in addition to the LSI chip. (D) It is not particularly necessary to seal the connection portion between the heat radiator and the base unit or the wire bonding portion with a resin. For example, a method of sealing the entire portion with a cap may be used. Of course, these may be used in combination.

(E) The plate material constituting the heat radiator does not necessarily have to be completely plate-shaped, and may have, for example, a slightly uneven surface on the heat radiating region side. (F) The pins of the base unit are not limited to the type to be inserted into the through holes. For example, a type may be used in which the base unit is directly bonded to a pad or the like provided on the surface without forming a through hole in the base unit.

(G) When manufacturing a build-up multilayer thin film wiring board as a heat radiator, a metal plate such as an aluminum plate or an alumite plate may be used in addition to the phosphor bronze plate used in the first embodiment. Of course it is possible. Similarly, other than the AlN substrate used in Example 2, for example, an alumina plate,
Ceramic substrates such as a mullite plate, a silicon nitride plate, and a boron nitride plate can be used.

[0041]

As described above in detail, according to the semi-conductor package of the present invention, an excellent effect that it is possible to obtain a compact semiconductor package with excellent and inexpensive heat dissipation.

[Brief description of the drawings]

FIG. 1 is a bottom view illustrating a base unit according to a first embodiment.

FIG. 2 is a plan view showing the base unit of FIG. 1;

FIG. 3 is a partially cutaway sectional view showing a semiconductor package.

FIG. 4 is a partially broken enlarged sectional view showing a state in which a build-up multilayer thin film wiring board is mounted on a base unit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor package, 2 ... Build-up multilayer thin film wiring board as a heat radiator, 3 ... Phosphor bronze plate as a plate material made of high thermal conductive material, 7 ... Die pad as electronic component mounting part, 8, 9 ... LSI chip, 12 ... connection pad as connection terminal, 15 ... base unit, 1
6 Window, 17 Step, 19 Pins as input / output terminals, B Build-up layer as high-density wiring layer.

Claims (2)

(57) [Claims] And 1. A base unit is formed from a plastic material, Toka heat radiating body which is mounted on the base unit
A heat dissipation body , wherein one side of a plate made of a high thermal conductive material is a heat dissipation area, and the other side is an electronic component mounting area having a high-density wiring layer; provided an electronic component mounting portion on the wiring layer, it arranged a plurality of connection terminals electrically connected to the electronic component side through the high-density wiring layer at the outer edge of the electronic component mounting region, the base unit Near the center of the radiator,
A window for exposing the heat area to the outside is provided, and the window is provided.
A plurality of input / output terminals are arranged around the
Connect the connection terminal side to the input / output terminal side of the base unit.
A semiconductor package characterized by being connected pneumatically. 2. A step portion is provided on an inner wall surface of the window portion, and the step portion is provided.
The radiator is provided in a housing portion formed by the upper surface of the window and the inner wall surface of the window.
2. The semiconductor package according to claim 1, wherein
Package.