JP3506788B2 - Semiconductor package - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package.

[0002]

2. Description of the Related Art Generally, an electric connection between an IC chip or an LSI chip and a printed wiring board which is a mother board is made through a semiconductor package. In recent years, resin-encapsulated semiconductor packages (so-called plastic packages) have become the mainstream. When manufacturing a plastic package, it is necessary to surely dissipate the heat generated by the LSI chip in order to prevent malfunction and thermal destruction of the LSI chip. Therefore, in the conventional plastic package, for example, a measure is taken to dispose a radiator, which is a plate material made of a high thermal conductive material such as Cu-W, on the back surface side of the chip mounting portion.

However, if an attempt is made to secure a large heat radiation area in the package by using a large heat radiator, the area where the wiring cannot be formed (dead area) is increased by the area of the heat radiation area. For this reason,
The size of the entire package has to be increased, resulting in deterioration of electrical characteristics such as a decrease in signal propagation speed. On the contrary, if the dead area is made as small as possible to maintain the current state of the package size, the heat radiator must be made small, and as a result, a sufficient heat radiation area cannot be secured.

As a means for solving such a problem,
2. Description of the Related Art There has conventionally been proposed a semiconductor package in which a radiator formed by forming a high-density wiring layer on one side surface of a plate material made of a high thermal conductive material is mounted in a window portion of a base unit having input / output terminals. In the case of this semiconductor package, an LSI chip or the like is mounted in the electronic component mounting area in the high-density wiring layer. A plurality of bonding pads are arranged on the outer edge of the electronic component mounting area. Further, a plurality of connection pads are arranged around the window of the base unit so as to correspond to the pads. These pads are electrically connected to each other via bonding wires. Therefore,
The semiconductor package described above is excellent in both heat dissipation and compactness.

Further, in this type of package, it is desirable that the electrical connection portion such as a bonding wire is covered and protected by some means. Therefore, from the viewpoint of improving reliability, resin sealing may be performed by the potting method.

[0006]

However, since the sealing resin used in the potting method has fluidity, it is difficult to accurately apply the sealing resin at a predetermined position. Therefore, as shown in FIGS. 6A and 6B, a portion where the sealing resin 70 spreads beyond the bonding pad formation region R1 to the input / output terminal formation region R2 is likely to be partially formed. In this case, a difference occurs in the electric resistance value between the portion where the sealing resin 70 reaches the input / output terminal 71 and the portion where the sealing resin 70 does not reach the input / output terminal 71, and the electrical characteristics of the semiconductor package 72 deteriorate.

Further, the appearance of the semiconductor package 72 as a whole is impaired because the outline of the sealing resin 70 becomes indefinite. Furthermore, if the encapsulating resin 70 is attached to the input / output terminals 71, it becomes difficult to insert the encapsulating resin 70 into the plated through holes, and a problem is likely to occur during mounting. And
When such a flow of the sealing resin 70 occurs, the amount of resin must be increased in order to avoid exposing the bonding wire 73. As a result, the spread of the sealing resin 70 is further expanded.

In order to prevent the sealing resin 70 from adhering to the input / output terminal 71, for example, the input / output terminal forming region R2
It goes without saying that the width of the region R3 between the bonding pad forming region R1 and the bonding pad forming region R1 may be secured to a certain extent. However, this method runs counter to the downsizing requirements.

The present invention has been made to solve the above problems, and an object thereof is to prevent deterioration of electrical characteristics and deterioration of appearance due to the flow of a sealing resin without increasing the size of the outer shape. It is to provide a semiconductor package that can be reliably avoided.

[0010]

In order to solve the above-mentioned problems, according to the invention described in claim 1, one side surface of a plate material made of a highly heat-conductive material serves as a heat dissipation area and the other side surface thereof has a high-density wiring. An electronic component mounting area including a layer, an electronic component mounting portion is provided on the high density wiring layer, and a plurality of connection terminals electrically connected to the electronic component side through the high density wiring layer are mounted on the electronic component. A heat dissipating member disposed at the outer edge of the area and a window portion for exposing the heat dissipating area of the heat dissipating member to the outside are provided in substantially the center of the printed wiring board, and one side surface of the printed wiring board and the window are provided. And a plurality of bonding pads are arranged around the portion, and a plurality of input / output terminals are arranged in a region outside the bonding pad formation region, and a base unit for mounting a radiator is provided. Bonn And Ingupaddo said connection terminal is electrically connected via a bonding wire, a further semiconductor package that connection portion is sealed with a resin, high-density wiring layers of the heat radiating body distribution and the insulating layer
Build-up having a structure in which line patterns are alternately laminated.
And a step portion having an upper surface lower than the surface forming the input / output terminals of the printed wiring board is formed on the inner wall surface of the window portion of the printed wiring board that constitutes the base unit . The gist of the invention is a semiconductor package having the bonding pad formed on the upper surface.

According to a second aspect of the present invention, in the first aspect, the step portion formed on the inner wall surface of the window has two steps and is stepwise, and the step portion has a relatively high upper surface. One having a bonding pad is used, and one having a relatively low upper surface is used as a step supporting the outer edge of the radiator.

According to a third aspect of the present invention, in the first or second aspect, the printed wiring board is a multi-layer board formed by a subtractive process, and the bonding pad is formed in a part of the inner layer conductor circuit. I am trying to

[0013]

According to the present invention, the surface on which the bonding pad is formed is relatively lower than the surface on which the input / output terminals of the printed wiring board are formed. The flow of the sealing resin to the terminal formation region is prevented.

According to the second aspect of the present invention, the stepped portion having the relatively lower upper surface reliably and horizontally supports the radiator from the lower surface side, so that the accuracy of wire bonding is improved.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor package according to an embodiment of the present invention will be described in detail below with reference to FIGS.

The semiconductor package 11 of this embodiment is shown in FIG.
As shown in FIG. 1 and the like, it is basically composed of a PGA type base unit 25 and a build-up multilayer thin film wiring board 12 which is a radiator.

The build-up multilayer thin film wiring board 12 is shown in FIG.
As shown in, the main material is a phosphor bronze plate 13 as a plate material made of a high thermal conductivity material. The entire one side surface of the phosphor bronze plate 13 is a heat dissipation area,
In addition, the entire opposite side surface is an electronic component mounting area. A buildup layer B as a high-density wiring layer is formed in the entire electronic component mounting area. In this embodiment, the buildup layer B has a structure in which the insulating layers 14 and the extremely fine wiring patterns 15 are alternately laminated.
The wiring patterns 15 of the respective layers are connected to each other by via holes 16 formed in the insulating layer 14.

As shown in FIG. 3, build-up layer B
A plurality of die pads 17 as electronic component mounting portions are provided on the top. LSI chips 18 and 19 as electronic components are mounted on the die pad 17. LS
The I chips 18 and 19 and the bonding pad 20 on the buildup layer B are electrically connected via a bonding wire 21. On the outer edge of the buildup layer B, a large number of connection pads 22 as connection terminals are regularly arranged. The LSI chips 18 and 19 and the connection pads 22 are electrically connected to each other through the wiring pattern 15 on the inner layer or the outer layer of the buildup layer B.

The base unit 25 is manufactured by using a printed wiring board 40 whose main material is a plastic plate material (in this embodiment, a copper clad laminated board made of BT resin).
This is because this type of plate material has an advantage that it is basically easy to perform drilling and the like. The printed wiring board 40 that constitutes the base unit 25 of this embodiment is a so-called four-layer board including four conductor layers. In FIG. 3, the first conductor layer formed on the pin protruding surface S1 (upper surface in the figure) of the printed wiring board 40 is the through hole 2
8 is a land 31 and a substantially square-shaped sealing pattern 32. Inner layer conductor circuits 42 and 43 as second and third conductor layers are formed on both surfaces of an inner layer board 41 which is a core of the printed wiring board 40. The fourth conductor layer formed on the pin non-projecting surface S2 of the printed wiring board 40 is the land 31 of the through hole 28 and the ground pattern 44 of a predetermined shape. This pin non-projecting surface S2
Are almost entirely covered with the solder resist 34. In the case of this printed wiring board 40, the second conductor layer is the signal layer, the third conductor layer is the power layer,
The fourth conductor layer plays a role as a ground layer. The printed wiring board 40 of this embodiment is manufactured by a normal subtractive process.

As shown in FIGS. 1 and 2, a window portion 26 having an outer shape that is substantially the same as the outer shape of the build-up multilayer thin film wiring board 12 is provided at a substantially central portion of the printed wiring board 40. . Around the window portion 26, a number of through holes 28 penetrating the front and back are formed. The through holes 28 electrically connect the conductor layers. A metal pin 29 as an input / output terminal is inserted into each through hole 28. The strip-shaped region of the base unit 25 in which the pins 29 are provided is referred to as an input / output terminal forming region R2 for convenience of description.

As shown in FIGS. 1 and 3, on the inner wall surface of the window portion 26, a pad step portion 27a and a support step portion 27b are provided.
Are provided in a staircase. Pad step 27a
The height of the upper surface of the pin is lower than the height of the pin protruding surface S1 of the printed wiring board 40. A rectangular bonding pad 30 is provided on the upper surface of the pad step portion 27a so as to entirely surround the window portion 26. The respective bonding pads 30 and the through holes 28 are electrically connected via the inner layer conductor circuit 42. In addition,
In this base unit 25, the bonding pad 3
The substantially square-shaped strip-shaped region where 0 is provided is referred to as a bonding pad formation region R1 for convenience of description. The substantially square-shaped band-shaped region existing between the input / output terminal formation region R2 and the bonding pad formation region R1 will be referred to as a blank region R3. In the case of this embodiment,
The width of this blank area R3 is about 1 mm to 5 mm.

Here, the pin protruding surface S1 and the pad step portion 2
The difference from the height of the upper surface of 7a is at least 0.3 mm,
It is preferably 0.5 mm to 1.0 mm. If this difference is too small, it may not be possible to reliably prevent the flow of the sealing resin 36. On the other hand, if this difference is too large, it is convenient for enhancing the above-mentioned flow blocking action, but on the other hand, the semiconductor package 11 may be thickened as a whole. In this embodiment, this difference is set to 0.5 mm in consideration of this point.

A supporting step portion 27b is arranged inside the pad step portion 27a. The upper surface of the supporting step portion 27b is relatively lower than the upper surface of the pad step portion 27a. In this embodiment, specifically, the difference is approximately equal to the thickness of the build-up multilayer thin film wiring board 12 and is about 1.1.
mm. Build-up multilayer thin film wiring board 12 with window 26
, The outer edge of the back surface of the build-up multilayer thin film wiring board 12 is supported by the upper surface of the supporting step portion 27b.

As shown in FIG. 3, the base unit 2
The bonding pad 30 on the No. 5 side and the connection pad 22 of the build-up multilayer thin film wiring board 12 are electrically connected via a bonding wire 33. And LS
I chip 18, 19 side and build-up multilayer thin film wiring board 1
The electrical connection portion with the second side and the electrical connection portion with the buildup multilayer thin film wiring board 12 side and the base unit 25 side are entirely sealed with a sealing resin 36. In this embodiment, the sealing resin 36 has a viscosity of 500 cps to 1000.
cps epoxy resin (Kyushu Matsushita, trade name: CCN20
01-23P) is used. LSI chip 18,
The electrical connection portion between the 19 side and the buildup multilayer thin film wiring board 12 side is specifically the bonding pad 20, LS.
Bonding pads (not shown) on the upper surfaces of the I-chips 18 and 19 and bonding wires 21 connecting them.
Refers to. The electrical connection portion between the buildup multilayer thin film wiring board 12 side and the base unit 25 side refers to the bonding pad 30, the connection pad 22 and the bonding wire 33 connecting them.

As shown in FIGS. 1 and 3, the sealing pattern 32 formed around the window 26 on the pin projecting surface S1 is sealed with a metal material such as Kovar having excellent conductivity. The stop cap 45 is soldered. The resin sealing portion is entirely covered by the sealing cap 45.

As shown in FIG. 3, the base unit 2
When the build-up multilayer thin-film wiring board 12 is mounted on No. 5, the heat radiation area of the build-up multilayer thin-film wiring board 12 is exposed from the window 26 to the outside. The semiconductor package 11 of this embodiment is mounted face down on a motherboard (not shown) by the pins 29. That is, the heat dissipation area faces upward (outward) and the electronic component mounting area faces downward (inward) during mounting. The area of the heat dissipation area, more specifically, the area of the portion of the heat dissipation area exposed from the window 26 is the actual heat dissipation area of the semiconductor package 11.

Next, the procedure for producing the semiconductor package 11 will be described with reference to FIG. Semiconductor package 11
The build-up multi-layered thin film wiring board 12 constituting the above is manufactured as follows. First, the starting material is phosphor bronze plate 1
One side of 3 is blackened, and a photosensitive epoxy resin is applied thereon. Then, by exposing and developing, a thickness of 15 μm having a via hole forming hole having an inner diameter of 40 μm
The insulating layer 14 is formed. A 0.1 μm thick Cr thin layer is formed on the insulating layer 14 by sputtering, and a 0.2 μm thick Cu thin layer is further formed on the Cr thin layer. L / S = 25 μm /
A plating resist for forming the wiring pattern 15 of 25 μm is arranged on the Cu thin layer. In this state, electrolytic Cu plating and electrolytic Ni plating are sequentially performed to obtain a thickness of 6
A Cu plating layer having a thickness of μm and a Ni plating layer having a thickness of 1 μm are respectively formed. After removing the plating resist, the Cu thin layer and the Cr thin layer in the non-plated portion are etched using a cupric chloride solution and a 20% hydrochloric acid aqueous solution. Then, the insulating layer 14 is formed by repeating the above steps as needed.
And the wiring patterns 15 made of a plurality of kinds of metals are alternately formed. As a result, a build-up multilayer thin-film wiring board (35 mm square, 1.0 mm thick) 12 having 5 layers of wiring patterns 15
Is created. After this, an open / short test is conducted.

On the other hand, the base unit 25 is manufactured as follows. First, a copper-clad laminate made of BT resin (50 mm
(Square, 1.7 mm thick) Around the central part, a counterbore is processed into a substantially square shape (31 mm square). Through this process, a through hole is formed in that portion. Electrolytic Cu plating is performed in a state where a plating resist is arranged on a predetermined portion, to deposit Cu on a necessary portion. After removing the plating resist, unnecessary Cu is etched. By this etching,
The inner layer conductor circuits 42 and 43 and the bonding pad 30 are formed. The same BT was formed on both sides of the obtained inner layer board 41.
A resin prepreg 46 is laminated (see FIG. 4 (a)). This prepreg 46 is on a so-called B stage, and a copper foil is attached to one surface thereof. A hole for forming a through hole for inserting a pin is formed by punching a laminated body obtained by laminating.

Electrolytic Cu plating is performed in a state where a plating resist is placed on a predetermined portion to deposit Cu on a required portion. After removing the plating resist, unnecessary Cu
To etch. By this etching, land 3
1, the sealing pattern 32 and the ground pattern 44 are formed (see FIG. 4B). After this, the pin non-projecting surface S
After forming the solder resist 34 on the second side, the pin 29 is inserted into the through hole 28. Furthermore, the pin protruding surface S
By machining the prepreg 46 on the 1 side,
The bonding pad 30 is exposed while forming the pad step portion 27a. Further, the prepreg 46 on the pin non-projecting surface S2 side is counterbored to form the supporting stepped portion 27b and penetrate the window portion 26. Finally, the counterbore surface is diced (see Fig. 4 (c)). After this, an open / short test is conducted.

Next, the build-up multilayer thin film wiring board 12 and the base unit 2 which have passed the open / short test.
And 5 are adhesive seals (Mitsubishi Yuka, trade name: YEF-040) 35 arranged on the supporting step 27b of the copper clad laminate.
Temporarily bond with. In this embodiment, the pressure for temporary adhesion is 2
Was 5 kgf / cm ^2, temperature of 220 ° C., the time is 2 minutes. Then, the adhesive seal 35 is completely cured by performing curing at 150 ° C. for 60 minutes.

Next, using the die bonder, the tested LSI chip 18 for the CPU is mounted on the die pad 17.
6 and memory LSI chips 19 are mounted. Here, a wire bonding device (made by Kyushu Matsushita, trade name: H
W-2200) is used to wire-bond the LSI chips 18 and 19. At this time, wire bonding is also performed between the bonding pad 30 and the connection pad 22 using the same device.

Then, resin encapsulation is performed by the potting method to electrically connect the LSI chips 18 and 19 to each other.
Build-up multilayer thin film wiring board 12 side and base unit 2
The portion electrically connected to the 5 side is entirely sealed with the sealing resin 36 (see FIG. 4 (d)). Finally, the sealing cap 45
Are soldered to the sealing pattern 32. The semiconductor package 11 is manufactured through the above procedure.

According to the semiconductor package 11 of this embodiment, the build-up layer B, which is a high-density wiring layer, is formed on one side of the phosphor bronze plate 13 that constitutes the build-up multilayer thin film wiring board 12. . Therefore, even when the semiconductor package 11 is formed together with the base unit 25, a dead area corresponding to the area of the buildup multilayer thin film wiring board 12 does not occur on the surface of the semiconductor package 11. Therefore, the semiconductor package 11
It is possible to secure a sufficient heat dissipation area without making the whole large. In addition, electrical characteristics are improved, such as an increase in signal propagation speed due to avoiding an increase in size. As the heat dissipation of the semiconductor package 11 is improved as described above, malfunctions and thermal destruction of the LSI chips 18 and 19 are extremely reduced as compared with the conventional case.

When the build-up multilayer thin film wiring board 12 is mounted in the accommodating portion of the base unit 25, the heat radiation area, which is one side surface of the phosphor bronze plate 13, is largely exposed from the window portion 26. Therefore, the heat conducted from the electronic component mounting area to the heat radiation area through the buildup layer B and the phosphor bronze plate 13 is efficiently dissipated to the atmosphere through the window 26.

Then, the semiconductor package 11 of the present embodiment.
In the above, two steps of the pad step portion 27a and the support step portion 27b are provided in a stepped manner on the inner wall surface of the window portion 26, and the bonding pad 30 is disposed on the upper surface of the pad step portion 27a. Therefore, the surface on which the bonding pad 30 is formed is relatively lower than the pin protruding surface S1 of the printed wiring board 40. Therefore, when the sealing resin 36 supplied by potting is about to spread in the direction of the input / output terminal forming region R2, the inner wall surface of the window portion 26 prevents the sealing resin 36 from flowing. As a result, the outline of the sealing resin 36 becomes linear by following the window 26. Therefore, the appearance of the entire semiconductor package 11 is surely improved as compared with the conventional one in which the outline is likely to be indefinite.

Further, as a result of eliminating the non-uniform flow of the sealing resin 36, variations in the electric resistance value are eliminated at the same time,
The electrical characteristics of the semiconductor package 11 are surely improved.
Of course, since the uneven flow of the sealing resin 36 is eliminated, the problem at the time of pin mounting is also eliminated. In addition, the work of supplying the sealing resin 36 at the time of potting becomes extremely easy.

Furthermore, in this semiconductor package 11,
Since no measure is taken to increase the width of the existing blank region R3 to some extent, the external size is not increased. Therefore, the demand for downsizing is not violated.

When the buildup multilayer thin film wiring board 12 is mounted on the base unit 25, the outer peripheral edge of the lower surface of the buildup multilayer thin film wiring board 12 is reliably and horizontally supported by the upper surface of the supporting step 27b. At this time, the height of the upper surface of the pad step portion 27a and the height of the upper surface of the build-up multilayer thin film wiring board 12 become substantially equal. Therefore, wire bonding between the bonding pad 30 and the connection pad 22 is facilitated and the accuracy of wire bonding is also improved as compared with the case where the heights of the both are uneven.

Then, the base unit 25 of this embodiment
Is a four-layer plate that is basically manufactured by the subtractive process as described above, and thus can be manufactured relatively easily and inexpensively. Therefore, it is convenient for cost reduction of the semiconductor package 11. Further, since the base unit 25 described above includes the conductor layers that serve as the signal layer, the power source layer, and the ground layer, it is also extremely excellent in electrical characteristics.

The present invention can be modified as follows, for example. (1) You may employ | adopt the structure like the semiconductor package 50 of the example 1 shown in FIG. The printed wiring board 52 that constitutes the base unit 51 is a so-called five-layer board.
On the inner wall surface of the window portion 26 of the printed wiring board 52, step portions 53a, 53b, 53c are provided in three steps and in a stepwise manner. Of these stepped portions 53a to 53c, two pad stepped portions 53a, 53 excluding the innermost supporting stepped portion 53c.
A plurality of bonding pads 30 are provided on the upper surface of b.
Are formed. That is, this semiconductor package 50
Has a so-called two-tier structure. Of course, it is also possible to form the three-tiered structure by forming the step portions 53a, 53b, and 53c in four steps, or by forming the four-tiered structure in five steps. Even when the above-mentioned configuration is adopted, the same operational effect as that of the above-described embodiment is obtained.

(2) The supporting step portion 27b does not necessarily have to extend over the entire circumference of the window portion 26, and may be two or three of the four sides of the window portion 26. (3) As a method of forming a printed wiring board which is a multilayer board, not only the subtractive process as in the embodiment but also the partially additive process can be applied.

(4) It is of course possible to manufacture the semiconductor package 11 by a procedure other than the manufacturing procedure shown in the embodiment. For example, in the manufacture of the base unit 25, a predetermined portion of each prepreg 46 may be counterbored before laminating the prepreg 46 on the inner layer plate 41.

(5) The forming material of the sealing resin 36 is not limited to the epoxy resin as in the embodiment, and
Other plastic materials such as BT resin, polyimide resin, silicone resin, fluororesin, etc. may be used. Printed wiring board 25 constituting base unit 25
It is also possible to change the main forming material of a to epoxy resin or polyimide resin.

(6) The pin 29 of the base unit 25 is not limited to the type inserted into the through hole. For example, the base unit 25 may be of a type that is directly joined to a pad or the like provided on the surface without forming a through hole. Also, instead of the pin 29 as the input / output terminal, a straight wall-shaped bump or the like may be formed.

(7) When the build-up multi-layered thin film wiring board 12 which is a radiator is manufactured, a metal plate such as an aluminum plate or an alumite plate should be used in addition to the phosphor bronze plate 13 used in the embodiment. Of course, it is possible. Further, it is not limited only to the metal plate, for example, an alumina plate,
It is also possible to use a ceramic substrate such as a mullite plate, a silicon nitride plate or a boron nitride plate. The plate material forming the heat radiator does not necessarily have to be a plate shape, and for example, the surface on the heat dissipation area side may have some irregularities.

Here, in addition to the technical ideas described in the claims, the technical ideas grasped by the above-described embodiments and other examples will be listed below together with their effects. (1) A window portion for exposing the heat radiation area of the heat radiator to the outside is provided at substantially the center of the printed wiring board, and a plurality of bonding pads are provided on one side surface of the printed wiring board and around the window portion. A base unit having a plurality of input / output terminals arranged in an area outside the bonding pad forming area, the upper surface being lower than the input / output terminal forming surface of the printed wiring board on the inner wall surface of the window portion. A base unit for mounting a radiator, in which a step portion having is formed, and the bonding pad is formed on an upper surface of the step portion.

The technical terms used in this specification are defined as follows. “High thermal conductivity material: A material having a higher thermal conductivity than a plastic material, for example, a ceramic material such as aluminum nitride, alumina, or mullite, or a metal material such as copper, copper alloy, or aluminum.”

[0048]

As described above in detail, according to the inventions of claims 1 to 3, wherein the bonding pad is formed in a portion lower than the input / output terminal forming surface, the sealing is achieved without increasing the outer size. It is possible to reliably avoid the deterioration of the electrical characteristics and the deterioration of the appearance due to the flow of the stopping resin. In particular, according to the invention as set forth in claim 2, since the radiator is reliably supported from the lower surface side, the accuracy of wire bonding can be improved. According to the invention described in claim 3, it is possible to provide a semiconductor package which is easy to manufacture and is relatively inexpensive.

[Brief description of drawings]

FIG. 1 is a bottom view showing a base unit according to an embodiment.

FIG. 2 is a plan view of the base unit shown in FIG.

FIG. 3 is an enlarged cross-sectional view of essential parts showing a semiconductor package of an example.

4A to 4D are schematic cross-sectional views showing the same manufacturing procedure.

FIG. 5 is a schematic cross-sectional view showing a semiconductor package of another example 1.

FIG. 6A is an enlarged bottom view of an essential part for explaining a problem in a conventional semiconductor package, and FIG. 6B is an enlarged sectional view of the same part.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Semiconductor package, 12 ... Build-up multilayer thin film wiring board as a heat radiator, 13 ... Plate material made of high thermal conductive material, 17 ... Die pad as electronic component mounting portion, 1
8, 19 ... LSI chips as electronic parts, 22 ... Connection pads as connection terminals, 25, 51, 56, 61 ... Base unit, 26 ... Window portions, 27a, 53a, 53b,
58a ... Pad step, 27b, 53c, 63b ... Support step, 29 ... Pins as input / output terminals, 30 ... Bonding pad, 33 ... Bonding wire, 36 ... Sealing resin, 40, 52, 57, 62 … Printed wiring board, 42
... inner layer conductor circuit, B ... high-density wiring layer, R1 ... bonding pad formation region, R2 ... input / output terminal formation region.

Claims (3)

(57) [Claims] 1. A plate material made of a high thermal conductive material has one side surface as a heat radiation area and the other side surface as an electronic component mounting area having a high density wiring layer, and the electronic component mounting portion is provided on the high density wiring layer. A heat radiator having a plurality of connection terminals electrically connected to the electronic component side via the high-density wiring layer at an outer edge portion of the electronic component mounting area; and a heat radiation area of the heat radiator outside. A window portion for exposing the printed wiring board is provided substantially at the center of the printed wiring board, and a plurality of bonding pads are arranged on one side of the printed wiring board and around the window portion. A base unit for mounting a heat radiator in which a plurality of input / output terminals are arranged in a region, and the bonding pad and the connection terminal are electrically connected via a bonding wire. It is, a further semiconductor package that connection portion is sealed with a resin, high-density wiring layers of the heat radiating body and the wiring pattern and the insulating layer
A buildup layer having a structure in which layers are alternately laminated, and which constitutes the base unit .
Stepped portion having a top surface lower than the surface to form <br/> formed input and output terminals of the printed circuit board on the inner wall surface of the window portion is formed, the bonding pad is formed on the upper surface of the step portion Semiconductor package. 2. The step portion formed on the inner wall surface of the window has two steps and is stepwise, and the step portion having a relatively high upper surface is defined as the step portion having the bonding pad. The semiconductor package according to claim 1, wherein the one having an upper surface that is relatively low is a step portion that supports an outer edge portion of the heat radiator. 3. The semiconductor package according to claim 1, wherein the printed wiring board is a multi-layer board formed by a subtractive process, and the bonding pad is formed on a part of the inner layer conductor circuit.