JPH09305480A - Memory device and method for accessing memory for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently perform memory access from both a CPU and a DSP (digital signal processor) by translating any one of two addresses from the other set address through a memory control part for controlling access to two memories. SOLUTION: In the case of reading data stored at an address 0003h of a memory 160 while a CPU 110 reads data stored at an address 0002h of a memory 150, a control part 118 outputs a control signal 117 instructing reading to a memory control part 140. An address generating part 116 outputs an address 114 having a value 0403h to the memory control part 140. Since the address 114 has a value after 0400h at such a time, the memory control part 140 outputs the value 003h, for which a prescribed value 0400h is subtracted from the address value 0403h, to the memory 160 as an address 162 and outputs a signal 164 instructing reading to the memory 160. As a result, data are read from the respective addresses of memories 150 and 160 and inputted through a data bus 105 to an arithmetic part 112.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device and a method for accessing a memory of the memory device.

[0002]

2. Description of the Related Art Conventionally, with the expansion of the field of digital signal processing, LSIs called DSPs (digital signal processors) are mounted in various devices. Since the DSP executes numerical operations on digital signals with high efficiency,
It is common to have a mechanism for reading a plurality of words (mostly two words) of data from a memory in a machine cycle. On the other hand, a CPU (Central Processing Unit) is mounted on a device together with a DSP and controls various peripheral circuits including the DSP. Since the CPU mainly makes various condition judgments and logical operations, the data read from the memory is generally one word in one machine cycle.

The operation of the DSP reading data from the memory will be described below with reference to FIG.

A command (not shown) is input to the control unit 301. The command input to the control unit 301 has two memories 3
When instructing to read data from 10, 320, the control unit 301 controls the address generation unit 315.
2 systems of addresses 317 and 327 are stored in the memories 310 and 3
Instruct to output to 20. Address 317 defines the location of the data to be read in memory 310. Address 327 defines the location of the data to be read in memory 320.

The address generator 315 is configured to address the address 317.
Is output to the memory 310, and the address 327 is output to the memory 32.
Output to 0. The address 317 has a value of 0002, for example.
have h. The address 327 has a value of 0003h, for example.
Having. Here, “h” represents that the value of the address is written in hexadecimal.

The values of the addresses 317 and 327 output by the address generator 315 are within the range from the address 0000h to the maximum address determined depending on the storage capacity of the memories 310 and 320. For example, when the storage capacity of the memory 310 is 1K words, the address generation unit 315
Outputs an address 317 within the range from address 0000h to address 03FFh to the memory 310.

The control unit 301 activates the read signal 311 of the memory 310 and activates the read signal 321 of the memory 320.

When the read signal 311 is active, the memory 310 outputs the data 318 stored in the position designated by the address 317 (for example, address 0002h) to the arithmetic unit 330. Similarly,
When the read signal 321 is active, the memory 320 stores the data 328 stored in the position specified by the address 327 (for example, address 0003h).
Is output to the calculation unit 330.

The calculation unit 330 executes a calculation on the data 318 and the data 328. Such memory access by the DSP is described in, for example, "MN 1920 Series LSI Manual" pages 5-24 to 5-29, published by Matsushita Electronics Industrial.

On the other hand, the memory access by the CPU is generally one word per one machine cycle as described above. How to specify memory address by CPU
This is different from the method of specifying the memory address by the DSP.
That is, the CPU uses one system address to specify the address of the memory to be accessed. Such memory access by the CPU is described, for example, in "MN10200 Series LSI Manual", page 57, published by Matsushita Electronics Industrial.

Further, the LSI microfabrication technology has made remarkable progress, and as described above, it is possible to integrate a CPU and a DSP having different memory address designating methods on one chip.

[0012]

However, as described above, the DSP and the CPU differ in the method of specifying the memory address.
Considering that both the DSP and the CPU access the memories 310 and 320 by integrating
There is a problem that one of the two memories 310 and 320 accessible by P cannot be accessed by the CPU. 00 is stored in the memories 310 and 320.
Since the address is assigned from address 00h, C
This is because the memory whose address can be specified by the PU is limited to one of the memories 310 and 320.

Further, when the CPU writes the two data in the memory (for example, the memory 310) and then the DSP processes the two data written in the memory, the DSP outputs the two data out of the two data. One needs to be transferred to another memory (eg, memory 320). There is a problem that the performance of the DSP may be impaired by executing the processing unrelated to the arithmetic processing.

The present invention has been made in view of the above problems, in which the CPU generates an address of one system, and
When the DSP generates two systems of addresses, C
An object of the present invention is to provide a memory device and a method for accessing the memory device, which realizes efficient memory access from both the PU and the DSP.

Another object of the present invention is to provide a memory device and a method for accessing the memory of the memory device, which realizes efficient memory access when the processor generates one system address and two system addresses. The purpose is to provide.

[0016]

A memory device according to the present invention comprises:
A first memory, a second memory, a first address that defines an access position in the first memory, and a first address that generates a second address that defines the access position in the second memory; and a third address A second processor for generating a memory, and a memory control unit for controlling access to the first memory and controlling access to the second memory, and representing either one of the first address and the second address. And a memory control section including an address conversion section for converting the third address, thereby achieving the above object.

The address conversion unit converts the third address so as to represent either the first address or the second address by subtracting a predetermined value from the value of the third address. Good.

The address converter sets the first address or the second address by setting a predetermined bit of the third address to "1" or resetting it to "0".
The third address may be converted to represent either one of the addresses.

The first processor, the second processor, and the controller may be formed on a single semiconductor chip.

Each of the first memory and the second memory may be a single port memory.

Another memory device of the present invention is a first memory, a second memory, a first address defining an access position in the first memory, and a second address defining an access position in the second memory. And a processor for generating a third address, and a memory control unit for controlling access to the first memory and controlling access to the second memory, which is either the first address or the second address. And a memory control unit including an address conversion unit for converting the third address so as to represent one of them, thereby achieving the above object.

The method of the present invention is a first memory device.
A method of accessing a memory and a second memory, the method comprising: generating a first address defining an access position in the first memory and a second address defining an access position in the second memory; A step of generating three addresses and a step of controlling access to the first memory and access to the second memory, the third address so as to represent either the first address or the second address. And a step of translating an address to achieve the above object.

The converting step may include a step of subtracting a predetermined value from the value of the third address.

The converting step may include a step of setting a predetermined bit of the third address to "1" or resetting to "0".

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a configuration of a memory device 1 according to a first embodiment of the present invention. The memory device 1 is
It has a memory 150 and a memory 160. Memory 1
Each of 50 and memory 160 is a single port memory.

The memory device 1 includes a CPU 110 and a DSP 1.
20 and a memory control unit 140.

The CPU 110 is connected to the memories 150 and 160 via the data bus 105.

The CPU 110 has a calculation unit 112, an address generation unit 116, and a control unit 118.

The arithmetic unit 112 processes data input via the data bus 105.

The address generator 116 is configured to send the address 114
Generate Address 114 defines the location to be accessed in memory 150 or the location in memory 160. The address 114 is, for example,
It is represented by 16 bits.

The control unit 118 outputs a control signal 117 instructing read or write to the memory control unit 140. The control unit 118 also controls the arithmetic unit 112 and the address generation unit 116.

The DSP 120 is connected to the memory 150 via the data bus 105, and is connected to the memory 160 via the data bus 106.

The DSP 120 has a calculation unit 122, an address generation unit 126, and a control unit 128.

The arithmetic unit 122 is provided with the data buses 105, 10
Process the data entered via 6.

The address generator 126 generates two independent addresses 124 and 125. Address 124
Defines the location in memory 150 to be accessed. Address 125 defines the location in memory 160 to be accessed. Each of the addresses 124 and 125 is represented by 16 bits, for example.

The control unit 128 outputs to the memory control unit 140 two independent control signals 134 and 135 for instructing reading or writing. In addition, the control unit 128
Controls the calculation unit 122 and the address generation unit 126.

The memory control section 140 controls access to the memory 150 and controls access to the memory 160. The memory control unit 140 receives the address 114 and the control signal 117 from the CPU 110, and receives the addresses 124 and 125 and the control signals 134 and 135 from the DSP.
Received from 120, address 152 and control signal 154
Are output to the memory 150, and the address 162 and the control signal 164 are output to the memory 160.

When the CPU 110 instructs reading or writing, the control unit 118 of the CPU 110 activates the control signal 117.

When the control signal 117 is active, the memory control unit 140 converts the address 114 into the address 152 or the address 162 according to a predetermined conversion format.

FIG. 2 shows an example of a predetermined conversion format. In this example, it is assumed that memory 150 has a storage capacity of 1K words and memory 160 has a storage capacity of 2K words. Addresses are sequentially assigned to the memories 150 and 160 starting from the address 0.

As shown in FIG. 2, when the value of the address 114 is in the range of 0000h to 03FFh,
The memory control unit 140 activates the control signal 154 and outputs the address 114 as the address 152 to the memory 150. Where "h" at the end of the address
Indicates that the address is written in hexadecimal.

On the other hand, when the value of the address 114 is a value after 0400h, the memory control unit 140 activates the control signal 164 and obtains it by subtracting a predetermined value 0400h from the value of the address 114. The output value is output to the memory 160 as the address 162.

When the DSP 120 instructs reading or writing, the control unit 128 of the DSP 120 activates the control signal 134 or the control signal 135.

When the control signal 134 is active, the memory control section 140 activates the control signal 154 and outputs the address 124 as the address 152 to the memory 150.

When the control signal 135 is active, the memory control section 140 activates the control signal 164 and outputs the address 125 as the address 162 to the memory 160.

FIG. 3 shows the configuration of the memory controller 140. The memory controller 140 shown in FIG.
It has a function of preferentially accepting an access request from the CPU 110 over an access request from 0.

The memory control section 140 includes an address conversion circuit 600 and selection circuits 610 to 640.

The control signal 117 is sent to the address conversion circuit 60.
0 and the selection circuits 610 to 640.

When the control signal 117 is active, the address conversion circuit 600 checks the value of the address 114. As a result, the value of the address 114 is 0000h-
If it is within the range of 03FFh, the address conversion circuit 600 activates the control signal 601 and outputs the address 114 as the address 603 to the selection circuits 610 and 620. The value of address 114 is 0
If the value is 400h or later, the address conversion circuit 6
00 selects a value obtained by activating the control signal 602 and subtracting a predetermined value 0400h from the value of the address 114, as the address 603.
10 and the selection circuit 620.

Select circuit 610 selectively outputs address 603 when control signal 117 is active, and selectively outputs address 124 when control signal 117 is not active. The output of the selection circuit 610 is output to the memory 150 as the address 152.

Select circuit 620 selectively outputs address 603 when control signal 117 is active, and selectively outputs address 125 when control signal 117 is not active. The output of the selection circuit 620 is output to the memory 160 as the address 162.

Select circuit 630 selectively outputs control signal 601 when control signal 117 is active, and selectively outputs control signal 134 otherwise. The output of the selection circuit 630 is output to the memory 150 as the control signal 154.

Select circuit 640 selectively outputs control signal 602 when control signal 117 is active, and selectively outputs control signal 135 otherwise. The output of the selection circuit 640 is output to the memory 160 as the control signal 164.

FIG. 4 shows the configuration of the memory controller 140a. The memory controller 140a may be replaced with the memory controller 140 shown in FIG. Further, an arbitration circuit 700 for arbitrating an access request from the CPU 110 and an access request from the DSP 120 is provided.

The arbitration circuit 700 includes control signals 117 and 13
The control signal 717 is output according to 4 and 135.
When giving priority to the access request from the CPU 110,
The arbitration circuit 700 activates the control signal 717.
When giving priority to the access request from the DSP 120,
The arbitration circuit 700 does not activate the control signal 717.

In the configuration of the memory control section 140a, instead of the control signal 117, the control signal 717 is selected by the selection circuits 610-6.
The configuration is the same as that of the memory control unit 140 except that it is input to the memory controller 40. Therefore, the same components are denoted by the same reference numerals, and description thereof will be omitted.

The operation of the memory device 1 will be described below.

(1) The DSP 120 stores 00 in the memory 150.
Data stored at address 02h and 000 in memory 160
The operation of reading the data stored at the address 3h is as follows.

Step 1: The control unit 128 outputs active control signals 134 and 135 instructing the reading to the memory control unit 140. The address generator 126 assigns the address 124 having the value 0002h to the memory controller 14
The address 125 having the value 0003h is output to the memory control unit 140.

Step 2: Since the control signals 134 and 135 are both active, the memory control section 140 is
The address 124 is output to the memory 150 as the address 152, and the address 125 is output to the memory 160 as the address 162. In addition, the memory control unit 140 outputs an active control signal 154 for instructing reading to the memory 1.
50 and outputs an active control signal 164 for instructing reading to the memory 160. As a result, the data is read from the address 0002h of the memory 150 and the data is read from the address 0003h of the memory 160.
The data read from the address 0002h of the memory 150 is input to the arithmetic unit 122 via the data bus 105. The data read from the address 0003h of the memory 160 is input to the arithmetic unit 122 via the data bus 106.

(2) The CPU 110 sets 00 in the memory 150.
The operation of reading the data stored at the address 02h is as follows.

Step 1: The control unit 118 sends an active control signal 117 for instructing reading out to the memory control unit 1.
Output to 40. The address generator 116 outputs the value 0002
The address 114 having h is output to the memory control unit 140.

Step 2: The memory control section 140 determines that the control signal 117 is active and the address 114
Is in the range of 0000h to 03FFFh, the address 114 is output as the address 152 to the memory 150, and the active control signal 154 instructing the reading is output to the memory 150. As a result, 0 in the memory 150
The data is read from the address 002h. Memory 150
The data read from the address 0002h is input to the arithmetic unit 112 via the data bus 105.

(3) The CPU 110 sets 00 in the memory 160.
The operation of reading the data stored at address 03h is as follows.

Step 1: The control unit 118 sends an active control signal 117 for instructing reading out to the memory control unit 1.
Output to 40. The address generator 116 outputs the value 0403.
The address 114 having h is output to the memory control unit 140.

Step 2: The memory control section 140 determines that the control signal 117 is active and the address 114
Is a value after 0400h, the value 0003h obtained by subtracting the predetermined value 0400h from the value 0403h of the address 114 is output to the memory 160 as the address 162, and the active control signal 164 for instructing reading is output. Output to. As a result, the data is read from the address 0003h of the memory 160. The data read from the address 0003h of the memory 160 is input to the arithmetic unit 112 via the data bus 105.

As described above, the memory control unit 140 depends on whether or not the value of the address 114 generated by the address generation unit 116 of the CPU 110 is within a specific range.
Address 114 to address 152 or address 1
62, and one of the control signals 154, 164 is activated. As a result, it becomes possible to access the two systems of memories 150 and 160 using the one system of address 114.

(Second Embodiment) FIG. 5 shows a configuration of a memory device 2 according to a second embodiment of the present invention. The memory device 2 is
It has a memory 550 and a memory 560. Memory 5
50 and memory 560 are each dual port memories.

The memory device 2 includes a CPU 110 and a DSP 1.
20 and a memory control unit 140b.

The configurations of the CPU 110 and the DSP 120 are the same as those shown in FIG. CPU110
Is connected to the memory 550 and the memory 5 via the data bus 505.
And 60. The DSP 120 is connected to the memory 550 via the data bus 105, and is connected to the memory 560 via the data bus 106.

When the CPU 110 instructs reading or writing, the control unit 118 of the CPU 110 activates the control signal 117.

When the control signal 117 is active, the memory controller 140b converts the address 114 into the address 552 or the address 562 according to a predetermined conversion format.
Convert to The predetermined conversion format is shown in FIG. 2, for example.

The value of the address 114 is 0000h to 03F
If it is within the range of Fh, the memory control unit 140b
Activates the control signal 554 and outputs the address 114 as the address 552 to the memory 550.

When the control signal 554 is active, the memory 550 inputs / outputs data to / from the position specified by the address 552 via the data bus 505.

On the other hand, when the value of the address 114 is 0400h or later, the memory controller 140b activates the control signal 564 and subtracts a predetermined value 0400h from the value of the address 114. The value to be output is output to the memory 560 as the address 562.

When the control signal 564 is active, the memory 560 inputs / outputs data to / from the position specified by the address 562 via the data bus 505.

When the control signal 117 is not active, the memory control section 140b does not activate the control signal 554 and does not activate the control signal 564.

When the DSP 120 instructs reading or writing, the control unit 128 of the DSP 120 activates the control signal 134 or the control signal 135.

When the control signal 134 is active, the memory 550 inputs / outputs data to / from the position designated by the address 124 via the data bus 105.

When the control signal 135 is active, the memory 560 inputs / outputs data to / from the position designated by the address 125 via the data bus 106.

As described above, the memory control unit 140b depends on whether or not the value of the address 114 generated by the address generation unit 116 of the CPU 110 is within a specific range.
Address 114 to address 552 or address 5
62 and activate one of the control signals 554, 564. This makes it possible to access the two systems of memories 550 and 560 using the one system of address 114.

(Third Embodiment) FIG. 6 shows a configuration of a memory device 3 according to a third embodiment of the present invention. The memory device 3 is
It has a memory 150 and a memory 160. Memory 1
Each of 50 and memory 160 is a single port memory.

The memory device 3 further has a processor 820 and a memory controller 840. Processor 82
0 is connected to the memories 150 and 160 via the data bus 805. Also, the processor 820
Are connected to the memory 150 via the data bus 105 and to the memory 160 via the data bus 106.

The processor 820 has a calculation unit 822, an address generation unit 826, and a control unit 828.

The arithmetic unit 822 is connected to the data buses 105, 10
Process the data entered via 6.

The address generation unit 826 uses the address 814
Generate Address 814 defines the location in memory 150 to access or in memory 160 to access. Also, the address generator 826
Generates addresses 124 and 125. Address 12
4 defines the position to be accessed in the memory 150. Address 125 defines the location in memory 160 to be accessed.

The control unit 828 controls the control signals 817, 13
4 and 135 are output to the memory control unit 840. Further, the control unit 828 controls the calculation unit 822 and the address generation unit 826.

The memory control section 840 has a control signal 1
The control signal 817 is input instead of 17, and the address 1
The configuration is the same as that of the memory control unit 140 shown in FIG. 1 except that an address 814 is input instead of 14.

When the data read from the memories 150 and 160 is input to the control unit 828 via the data bus 805, the control unit 828 activates the control signal 817 and the address generation unit 826 outputs the address. 81
The address generation unit 826 is controlled so as to generate 4.

When the control signal 817 is active, the memory control unit 840 converts the address 814 into the address 152 or the address 162 according to a predetermined conversion format. The predetermined conversion format is shown in FIG. 2, for example.

The value of the address 814 is 0000h to 03F
If it is within the range of Fh, the memory control unit 840
Control signal 154 is activated and address 81
4 is output to the memory 150 as the address 152. On the other hand, when the value of the address 814 is 0400h or later, the memory control unit 840 activates the control signal 164, and the value of the address 814 is set to a predetermined value 0.
The value obtained by subtracting 400h is output to the memory 160 as the address 162.

The control unit 828 decodes the data read from the memories 150 and 160 as an instruction.

The data read from the memories 150 and 160 is processed by the arithmetic unit 822 via the data buses 105 and 106.
Input to the memory 15 or data output from the arithmetic unit 822 via the data buses 105 and 106.
When writing to 0 or 160, the control unit 828 activates the control signal 134 or the control signal 135, and controls the address generation unit 826 so that the address generation unit 826 generates the address 124 or the address 125.

When the control signal 134 is active, the memory control section 840 activates the control signal 154 and outputs the address 124 as the address 152 to the memory 150.

When the control signal 135 is active, the memory control section 840 activates the control signal 164 and outputs the address 125 as the address 162 to the memory 160.

As described above, the memory control unit 840 determines whether the value of the address 814 generated by the address generation unit 826 is within the specific range.
4 is converted to address 152 or address 162, and one of the control signals 154 and 164 is activated. This makes it possible to access the two systems of memories 150 and 160 using the one system of address 814.

In the first to third embodiments described above, the address conversion is performed by using the address 114 (or the address 81).
It is performed by subtracting a predetermined value 0400h from the value of 4). However, this predetermined value is not limited to 0400h. This predetermined value is the memory 150 (or the memory 550) or the memory 160 (or the memory 560).
It can take any value as long as it is equal to or larger than the storage capacity of.

Address conversion is performed by using the address 114
It can also be achieved by an operation other than the operation of subtracting a predetermined value from the value of (or address 814). For example, when the value of the address 114 (or the address 814) is within the predetermined range, the address 114
A specific bit (or address 814) may be set to "1" or reset to "0".
For example, if address 114 (or address 814) has the value 0403h, resetting bit 10 of address 114 (or address 814) causes the value of address 114 (or address 814) to be 0.
It can be converted to 003h.

Further, the address 114 (or the address 8
14), address 124, address 125, address 1
It goes without saying that the bit widths of 52 (or address 552) and address 162 (or address 562) are not limited to those in the above-described embodiment.

[0101]

According to the memory device of the present invention, the first processor generates the first address defining the access position in the first memory and the second address defining the access position in the second memory. The first memory is accessed based on the first address and the second memory is accessed based on the second address. Further, the third address is generated by the second processor. The third address is translated by the address translation unit. The first memory or the second memory is accessed based on the converted third address.

As described above, the first memory or the second memory is accessed based on the addresses of the two systems (the first address and the second address), and the first memory is accessed based on the addresses of the one system (the third address). It becomes possible to access the memory or the second memory. This enables efficient memory access from both the first processor and the second processor.

Furthermore, according to another memory device of the present invention, two systems of addresses (first address and second address) and one system of address (third address) are generated by the same processor. This enables efficient memory access.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a memory device 1 according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a predetermined conversion format used for converting an address 114.

FIG. 3 is a diagram showing a configuration of a memory control unit 140.

FIG. 4 is a diagram showing a configuration of a memory control unit 140a.

FIG. 5 is a diagram showing a configuration of a memory device 2 according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a memory device 3 according to a third embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a conventional DSP.

[Explanation of symbols]

105, 106 Data bus 110 CPU 120 DSP 112, 122 Arithmetic unit 116, 126 Address generation unit 118, 128 Control unit 114, 124, 125, 152, 154, 552, 5
62 addresses 117, 134, 135, 162, 164, 554, 5
64 control signal 140, 140a, 140b, 840 memory control unit 150, 160, 550, 560 memory

Claims (9)

[Claims] 1. A first processor for generating a first memory, a second memory, a first address defining an access position in the first memory, and a second address defining an access position in the second memory. A second processor for generating a third address, and a memory control unit for controlling access to the first memory and controlling access to the second memory, which is either the first address or the second address. And a memory control unit including an address conversion unit that converts the third address so as to represent one of the two. 2. The address translation unit subtracts a predetermined value from the value of the third address to obtain the first address.
The memory device of claim 1, wherein the third address is translated to represent either the address or the second address. 3. The address conversion unit represents either the first address or the second address by setting a predetermined bit of the third address to “1” or resetting to “0”. The memory device according to claim 1, wherein the third address is translated as described above. 4. The memory device according to claim 1, wherein the first processor, the second processor, and the controller are formed on a single semiconductor chip. 5. The memory device according to claim 1, wherein each of the first memory and the second memory is a single port memory. 6. A first memory, a second memory, a first address defining an access position in the first memory, a second address defining an access position in the second memory, and a third address. A processor for generating and a memory control unit for controlling access to the first memory and controlling access to the second memory, wherein the memory control unit represents either the first address or the second address. A memory device including a memory control unit including an address conversion unit that converts three addresses. 7. A method of accessing a first memory and a second memory in a memory device, comprising: a first address defining an access position in the first memory and a first address defining an access position in the second memory. 2 addresses, a third address, a step of controlling an access to the first memory and an access to the second memory, wherein the first address or the second address Translating the third address to represent either one. 8. The converting step includes the step of subtracting a predetermined value from the value of the third address,
The method according to claim 7. 9. The method according to claim 7, wherein the converting step includes the step of setting a predetermined bit of the third address to “1” or resetting to “0”.