JPH0338612B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a register indirect specification memory address control device for a microcomputer.

Conventional configurations and their problems In recent years, the spread of microcomputers in the industrial world has been remarkable. Such microcomputers are operated and controlled by various instructions.

In general, an arithmetic instruction consists of an operation part that determines the content of the execution operation and an operand part that specifies data to be processed. Here, if the operand exists in memory, it is necessary to specify and control the memory address.

The conventional memory address mode will be explained below with reference to FIG.

(a) shows the configuration of the address register. It is assumed that address registers R ₀ and R ₁ each have 16 bits. That is, the maximum memory capacity is 65K words.

(b) shows the structure of the command word. For example, if the operation section is an addition instruction, the data specified by the operand section is added to the acumulator of the microcomputer, and the addition result is stored in the accumulator.

(c) shows the contents of the operand part, and O
Then the operand address is R ₀ , and if it is 1 then R ₁
Indicates that it is specified by .

However, if a one-chip microcomputer in which the data RAM and the processor section are configured on the same LSI has the above address mode, the following problem will occur.

One-chip microcomputers cannot incorporate large amounts of RAM due to density constraints. Generally, it is often used with only built-in RAM, but for system expansion, it is also required to have an external memory expansion function. In other words, it is necessary to efficiently access a relatively small-capacity built-in RAM and also to access a large-capacity address space. On the other hand, if there are a large number of address registers, efficient programming is possible, but it is generally difficult to incorporate many address registers due to restrictions on the degree of integration of LSIs. That is, it is important to efficiently utilize the built-in address registers. For example, set the internal RAM capacity to 256
If the address register is a word, the upper 8 bits of the address register will not be used, resulting in poor use efficiency of the address register.

Purpose of the invention The present invention solves the above-mentioned conventional problems.
An object of the present invention is to provide a memory address control device with an increased number of operand address modes in order to efficiently utilize each address register.

Structure of the Invention The present invention has two address registers, an upper part and a lower part.
A circuit that separates the registers into groups and selects a single register from each register group, a means for connecting the registers obtained by each selection circuit to form a memory address, and a means for setting the upper memory address as a specific address and the lower memory address as the lower memory address. By having a means to select from a group of registers, small capacity can be achieved.
This allows RAM to be efficiently addressed.

DESCRIPTION OF EMBODIMENTS FIG. 2 is a diagram for explaining a memory address mode in an embodiment of the present invention. In figure a, the address registers are in the first register group r ₁ , r ₃ ,
It shows that it is composed of a second register group r ₁ and r ₂ . It is assumed that the word length of each register is 8 bits. Figure b shows the structure of the command word. Similar to FIG. 1b, if the operation section is an addition instruction, the data specified by the operand section and the accumulator are added, and the addition result is stored in the accumulator. c indicates the contents of the operand section. If the MSB of the operand part is o, the upper 8 bits of the operand address are automatically set to zero, and the lower 8 bits are r ₀ , r ₁ , r ₂ ,
r Specified by one of ₃ . On the other hand, MSB
When is 1, the operand address is specified by (r ₁ r ₀ ), (r ₃ r ₀ ), (r ₁ r ₂ )(r ₃ r ₂ ).

FIG. 3 shows an embodiment of a memory address control circuit that executes the address mode shown in FIG. 2.

1 is the first address group consisting of r ₁ and r ₃ , 2 is the first selection circuit, 3 is the second register group consisting of r ₀ and r ₂ , 4 is the second selection circuit, and 5 is the AND gate. ,
6 is a selection circuit which receives the outputs of the first and second register groups 1 and 3; 7 is an upper memory address signal;
8 is a lower memory address signal, 9 is a control signal for the first selection circuit 2, 10 is a control signal for the second selection circuit 4, 11 is a gate signal for the AND gate 5, 12
is a control signal for the selection circuit 6.

The operation of the memory address control device of this embodiment configured as described above will be described below.

Control signals 9, 10, 11, 12 in FIG.
is output from the instruction decoder of the microcomputer. The control mode of each control signal is shown below.

When 9:0, the first selection circuit 2 outputs r ₁ When 1, the first selection circuit 2 outputs r 3 10: When 0, the second selection circuit 4 outputs r _{0 When 1, the first selection circuit 2 outputs r 3 .} When the second selection circuit 4 outputs r ₂ 11:0, the AND gate 5 outputs 0. When 1, the AND gate 5 outputs the output of the first selection circuit 2. When 12:0, the selection circuit 6 outputs the second When the output of the selection circuit 4 is 1, the selection circuit 6 outputs the output of the first selection circuit 2. Control signals 9, 10, 1 defined as above
FIG. 4 shows the correspondence between states 1 and 12 and operand addresses.

In FIG. 4, for example, in operand address mode 0, each control signal 9, 10, 11, 12
By setting (X, 0, 0, 0), it is shown that the operand address (Or ₀ ) is output from the upper address signal 7 and the lower address signal 8 in FIG.

However, X indicates redundancy. The same applies to modes 1 and below, so the explanation will be omitted.

From the above, it can be seen that the memory address control circuit of FIG. 3 realizes the address mode shown in FIG. 2c.

In this embodiment, the specific address is set to 0, but it can easily be set to any value.

Effects of the Invention The memory address control device of the present invention connects or connects an address register consisting of a first register group and a second register group, a selection circuit of each register group, and outputs of the first and second selection circuits. The address is a specific address, and the lower address is the first address.
Alternatively, by providing a means for outputting the second selection circuit, the relatively small capacity RAM built into a one-chip microcomputer can be efficiently addressed, reducing the program size, and at the same time, increasing the capacity when external RAM is expanded. Address access can also be made possible, which has great practical effects.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the conventional memory address mode, where a is a structural diagram of an address register,
b is a diagram of the structure of an instruction word, c is a diagram of contents corresponding to the operand part, FIG. Word structure diagram, c
3 is a block diagram of a memory address control circuit in an embodiment of the present invention, and FIG. 4 is a diagram of the correspondence between control signals and operand addresses in the memory address control circuit of FIG. 3. be. 1...First register group, 2...First selection circuit, 3...Second register group, 4...Second selection circuit, 5...AND gate, 6...Selection circuit.

Claims (1)

[Claims] 1 a first register group, a second register group,
first and second selection means for selecting a single register from the first and second register groups, means for concatenating the registers obtained by the first and second selection circuits to form a memory address; It has means for determining the memory address as a specific address and the lower memory address by a register obtained from the first or second selection circuit, and each of the four means is selectively controlled by the operand part of the instruction. A memory address control device characterized by: