JPH09251774A - Semiconductor memory device - Google Patents

Abstract

Kind Code: A1 An operation margin of a synchronous DRAM or the like having a latency mode is increased and its operation is stabilized without sacrificing an access time in a read mode of the latency 3. SOLUTION: The output latches OL10 to OL1F and OL20 have a two-stage structure and have a latency mode in which the number of delay cycles can be selectively designated and are connected in series.
~ In a synchronous DRAM or the like equipped with OL2F,
1st stage output latch O in latency 2 read mode
L10-OL1F are latched, second-stage output latches OL20-OL2F are turned-through, and
The generation timing of the output latch control signal OL1 supplied to the stage output latch is switched for each latency. As a result, the generation timing of the output latch control signal OL2 supplied to the second stage output latches OL20 to OL2F is fixed in the shortest state, while the first stage output latches OL10 to OL0.
The generation timing of the output latch control signal OL1 supplied to L1F is optimized according to the number of delay cycles.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a synchronous DRAM (dynamic random access memory) having a latency mode.
In addition, the present invention relates to a technique that is particularly effective when used for stabilizing its operation.

[0002]

2. Description of the Related Art There is a so-called synchronous DRAM which operates synchronously according to a predetermined clock signal. In the synchronous DRAM, when the read (read) command is input, the time from when the column address strobe signal is set to the effective level to when the first read data is output is selected, for example, for 1 to 3 cycles of the clock signal. Many have a so-called latency mode that can be delayed.

[0003]

Prior to the present invention, the inventors of the present invention developed a synchronous DRAM having a latency mode, and provided two output latches connected in series to its data input / output circuit. A method is adopted in which the number of delay cycles in the latency mode is selectively switched by selectively switching the operation mode of the output latch. That is, in the so-called latency 1 read mode in which the number of delay cycles from the column address strobe signal is 1, both output latches are constantly in the through state and the so-called through operation is performed, and output from the main amplifier. The read data passes through the two output latches as it is. On the other hand, in the latency 2 read mode in which the number of delay cycles from the column address strobe signal is 2, the first stage output latch operates through, but the second stage output latch operates according to the corresponding output latch control signal. And the total read data is 2
Delayed by a cycle. Furthermore, in the latency 3 read mode in which the number of delay cycles from the column address strobe signal is 3, two output latches are latched together, and the read data is delayed by a total of 3 cycles.

However, the inventors of the present application faced the following problems in an attempt to further increase the speed of the synchronous DRAM. That is, the above-mentioned synchronous DRA
In M, as described above, both the first-stage and second-stage output latches provided in the data input / output circuit in the latencies 2 and 3 are latched, and the operation is controlled by the common output latch control signal. On the other hand, in the read mode of the latency 3 in which the frequency of the clock signal is the highest, the access time to the clock signal of the synchronous DRAM is regulated by the operation of the second stage output latch, that is, the generation timing of the output latch control signal for controlling it. Therefore, the generation timing of the output latch control signal needs to be fixed irrespective of the latency and formed in the shortest path to minimize the delay time. However, the generation timing of this output latch control signal is not necessarily optimum in view of the latency 2 read mode in which the frequency of the clock signal is an intermediate value, and in some cases, the read data is not captured by the second-stage output latch. Unstable, synchronous DRA
The operating margin of M decreases. Further, in order to cope with this, when the generation timing of the output latch control signal is switched for each latency, the number of logic stages of the related circuit of the timing generation circuit increases, and the access time of the synchronous DRAM in the latency 3 read mode is increased. Sacrificed.

An object of the present invention is to provide a synchronous DR having a latency mode without sacrificing the access time of the latency 3 in the read mode.
The purpose is to increase the operation margin of AM or the like and stabilize the operation.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, the time from when the column address strobe signal is set to the effective level to when the first read data is output is, for example, 1 to 3 of the clock signal.
In a synchronous DRAM or the like, which has a latency mode in which it can be selectively delayed by a cycle, and which has a serially coupled two-stage output latch, the first-stage output latch is latched in the latency-2 read mode, The through operation of the second stage output latch is performed, and the generation timing of the output latch control signal supplied to the first stage output latch is switched for each latency.

According to the above-mentioned means, the output latch control signal supplied to the first stage output latch is generated while the generation timing of the output latch control signal supplied to the second stage output latch is fixed in the shortest state. The timing can be optimized depending on the number of delay cycles. As a result, the operation margin of the synchronous DRAM or the like having the latency mode can be increased and its operation can be stabilized without sacrificing the access time in the read mode of the latency 3.

[0009]

FIG. 1 is a block diagram showing an embodiment of a synchronous DRAM (semiconductor memory device) to which the present invention is applied. First, an outline of the configuration and operation of the synchronous DRAM of this embodiment will be described with reference to FIG. The circuit elements forming each block in FIG. 1 are not particularly limited, but known MOSFETs (metal oxide semiconductor field effect transistors. In this specification, MOSFETs are generically called insulated gate field effect transistors. It is formed on one semiconductor substrate such as single crystal silicon by the manufacturing technology of integrated circuits.

In FIG. 1, the synchronous DRAM of this embodiment includes a pair of banks BNK0 and BNK1,
Each of these banks includes a memory array MARY arranged to occupy most of its layout area, a row address decoder RD serving as a direct peripheral circuit, a sense amplifier SA and a column address decoder CD, a write amplifier and a read amplifier, respectively. And a main amplifier MA including.

The memory array MARY forming the banks BNK0 and BNK1 has a predetermined number of word lines arranged in parallel in the vertical direction and a predetermined set of complementary bit lines arranged in parallel in the horizontal direction. Include each. At the intersections of these word lines and complementary bit lines, a large number of dynamic memory cells composed of information storage capacitors and address selection MOSFETs are arranged in a grid.

The word lines forming the memory array MARY of the banks BNK0 and BNK1 are coupled to the corresponding row address decoder RD, and each of them is selectively selected. To these row address decoders RD, i-bit internal address signals X0 to Xi-1 excluding the most significant bit are commonly supplied from the row address buffer RB, and an internal control signal RG is commonly supplied from the timing generation circuit TG. Supplied. The row address buffer RB is supplied with the X address signals AX0 to AXi in a time division manner via the address input terminals A0 to Ai, and the timing control circuit TG supplies the internal control signal RL.

The row address buffer RB has an X address signal A input via address input terminals A0 to Ai.
X0 to AXi are fetched and held according to internal control signal RL, and internal address signals X0 to Xi are formed based on these X address signals. Of these, the internal address signal Xi of the most significant bit is the bank selection circuit BS.
And other internal address signals X0 to Xi-1
Are commonly supplied to the row address decoders RD of the banks BNK0 and BNK1.

The bank selection circuit BS decodes the internal address signal Xi of the most significant bit supplied from the row address buffer RB and outputs the corresponding bank selection signal BS0.
Alternatively, BS1 is selectively set to the high level. These bank selection signals BS0 and BS1 correspond to the corresponding bank BNK.
0 and BNK1, respectively, which are peripheral circuits such as a row address decoder RD and a column address decoder C.
It serves as a selection control signal for selectively setting the D and the sense amplifier SA in the operating state.

The row address decoders RD of the banks BNK0 and BNK1 are selectively activated by setting the internal control signal RG to high level and the corresponding bank selection signal BS0 or BS1 to high level, respectively. The internal address signals X0 to Xi-1 supplied from the address buffer are decoded to selectively set the designated word line of the corresponding memory array MARY to the selection level.

Next, the complementary bit lines forming the memory array MARY of the banks BNK0 and BNK1 are coupled to the corresponding sense amplifier SA. A bit line selection signal of a predetermined bit is supplied from the corresponding column address decoder CD to each of these sense amplifiers SA, and an internal control signal PA is commonly supplied from the timing generation circuit TG. In addition, the column address decoders CB to i + are added to the column address decoder CD of each bank.
The 1-bit internal address signals Y0 to Yi are commonly supplied, and the timing control circuit TG commonly supplies the internal control signal CG. Further, the Y address signals AY0 to AYi are supplied to the column address buffer CB in a time division manner via the address input terminals A0 to Ai.
The internal control signal CL is supplied from the timing generation circuit TG.

The column address buffer CB fetches the Y address signals AY0 to AYi supplied via the address input terminals A0 to Ai in accordance with the internal control signal CL,
The internal address signals Y0 to Yi are formed based on these Y address signals while being held and supplied to the column address decoder CD of each bank. Further, the column address decoder CD of each bank is selectively activated by setting the internal control signal CG to the high level and the corresponding bank selection signal BS0 or BS1 to the high level, and the internal address signals Y0 to Y0. Yi is decoded and the corresponding bit line selection signals are alternately set to the high level.

On the other hand, the sense amplifier SA of each bank includes a predetermined number of unit circuits provided corresponding to the complementary bit lines of the corresponding memory array MARY, and each of these unit circuits has a pair of CMOS inverters. And a pair of switch MOSFETs of N-channel type. Among these, in the unit amplifier circuit of each unit circuit, the internal control signal PA is set to the high level and the corresponding bank selection signal BS0 or BS1.
Are set to a high level to be selectively and simultaneously activated, and output from a predetermined number of memory cells coupled to the selected word line of the corresponding memory array MARY through the corresponding complementary bit lines. Each minute read signal is amplified to be a high level or low level binary read signal. In addition, the switch MOSF of each unit circuit
Upon receiving the high level of the corresponding bit line selection signal, ET is selectively turned on by 16 pairs, and the memory array M
16 sets of complementary bit lines corresponding to ARY and complementary common data lines CD0 * to CDF * (where complementary signal lines consisting of non-inverted and inverted signals are indicated by adding * to the end of their names. The same) is selectively connected.

The complementary common data lines CD0 * to CDF * are
Coupled to corresponding main amplifier MA. These main amplifiers MA have complementary common data lines CD0 * to CDF *.
16 write amplifiers and read amplifiers provided corresponding to the above. Of these, the input terminals of each write amplifier are coupled to the corresponding internal data buses DBUS0 to DBUSF, and the output terminals are coupled to the corresponding complementary common data lines CD0 * to CDF *. The input terminal of each read amplifier has a corresponding complementary common data line CD0 * to
It is coupled to CDF * and its output terminal is coupled to the corresponding internal data buses DBUS0 to DBUSF. The internal control signals RP and WP are commonly supplied from the timing generation circuit TG to the main amplifier MA of each bank.

On the other hand, internal data buses DBUS0 to DBU
SF is a corresponding input latch I of the data input / output circuit IO.
It is coupled to the output terminals of L0 to ILF and to the input terminals of the corresponding first stage output latches OL10 to OL1F. Here, the data input / output circuit IO includes 16 data input buffers D each provided corresponding to the internal data buses DBUS0 to DBUSF, as described later.
IB0 to DIBF, input latches IL0 to ILF, first stage output latches OL10 to OL1F, second stage output latch OL
20 to OL2F and data output buffers DOB0 to
It has a DOBF. Of these, the data input buffer DI
The input terminals of B0 to DIBF are coupled to the corresponding data input / output terminals D0 to DF, and the output terminals thereof are coupled to the input terminals of the corresponding input latches IL0 to ILF. The output terminals of these input latches are respectively coupled to the corresponding internal data buses DBUS0 to DBUSF. on the other hand,
The input terminals of the first stage output latches OL10 to OL1F are coupled to the corresponding internal data buses DBUS0 to DBUSF, and the output terminals thereof are corresponding to the second stage output latches OL20.
~ Coupled to the input terminal of OL2F. The output terminals of the second stage output latches OL20-OL2F are coupled to the input terminals of the corresponding data output buffer OB, and the output terminals of these data output buffers are coupled to the corresponding data input / output terminals D0-DF. It The data input / output circuit IO includes internal control signals IL, O from the timing generation circuit TG.
L1 (first output latch control signal), OL2 (second output latch control signal) and output control signal DOC are supplied.

The data input buffers DIB0 to DIBF of the data input / output circuit IO correspond to the corresponding data input / output terminals D0 when the synchronous DRAM is in the write mode.
~ Capture write data input via DF,
It transmits to the corresponding input latches IL0-ILF. These input latches correspond to the corresponding data input buffer DIB0.
To DIBF are taken in and held according to the internal control signal IL, and the main amplifier MA is supplied via the internal data buses DBUS0 to DBUSF.
To the corresponding write amplifier. At this time, each write amplifier of the main amplifier MA is selectively brought into an operating state by setting the internal control signal WP to the high level and the corresponding bank selection signal BS0 or BS1 to the high level, and the data input / output circuit. IO corresponding input latch IL
0 to ILF to internal data bus DBUS0 to DBUSF
After the write data transmitted via the above is converted into a predetermined write signal, it is written into the selected 16 memory cells of the corresponding memory array MARY via the complementary common data lines CD0 * to CDF *.

On the other hand, in the read amplifiers constituting the main amplifiers MA of the banks BNK0 and BNK1, the internal control signal RP is at the high level and the corresponding bank selection signal B is set.
When S0 or BS1 is set to the high level, it is selectively brought into an operating state, and the complementary common data line CD0 * is selected from the 16 memory cells selected in the corresponding memory array MARY.
Amplifies the read signal output via -CDF * and outputs it to internal data buses DBUS0-DBUSF. At this time, the first-stage output latches OL10 to OL1F of the data input / output circuit IO are selectively brought into the through state when the internal control signal OL1 is set to the high level, and the internal control signal OL1 is set to the low level. It selectively enters the latched state, and the read data supplied from the corresponding read amplifier of the main amplifier MA of the bank BNK0 or BNK1 via the internal data buses DBUS0 to DBUSF to the corresponding second stage output latches OL20 to OL2.
Transmit to F respectively. Similarly, the data input / output circuit IO
The second-stage output latches OL20 to OL2F are selectively brought into the through state when the internal control signal OL2 is at the high level, and are selectively brought into the latch state when the internal control signal OL2 is at the low level. , The read data supplied from the corresponding first stage output latches OL10 to OL1F are converted into the corresponding data output buffers DOB0 to DOB.
Transmit to F respectively. Furthermore, the data output buffer D
OB0 to DOBF are selectively activated by receiving the high level of the output control signal DOC, and read data transmitted from the corresponding second stage output latches OL20 to OL2F via the data input / output terminals D0 to DF. Output to external device. The specific configuration and operation of the data input / output circuit IO and its characteristics will be described later in detail.

The timing generation circuit TG includes a clock signal CLK supplied from the outside and a chip selection signal CSB serving as a start control signal (here, a so-called inversion signal which is selectively brought to a low level when it is enabled). Is indicated by adding B to the end of its name. The same applies hereinafter), row address strobe signal RASB, column address strobe signal CASB, and write enable signal WEB.
The various internal control signals and output control signals are selectively formed based on the above, and are supplied to each unit.

FIG. 2 shows a block diagram of an embodiment of the data input / output circuit IO included in the synchronous DRAM of FIG. Further, FIG. 3 shows a partial circuit diagram of one embodiment of the data input / output circuit IO of FIG. 2, and FIG. 4 shows one implementation of the timing generation circuit TG included in the synchronous DRAM of FIG. An example partial schematic is shown. Further, FIGS. 5, 6 and 7 show signal waveform diagrams of one embodiment in the read mode of the latency 1, latency 2 and latency 3 of the synchronous DRAM of FIG. 1, respectively, and FIG. The signal waveform diagram of the read mode of the latency 2 of the synchronous DRAM developed by the present inventors prior to the invention is shown. In addition, FIG. 9 shows the synchronous D of FIG. 1 and FIG.
A conceptual diagram for comparatively explaining the operation mode of the output latch included in the data input / output circuit of the RAM is shown. Based on these figures, the specific configuration and operation of the data input / output circuit IO and the timing generation circuit TG included in the synchronous DRAM of this embodiment and their characteristics will be described. In FIG. 3, the output latches OL10 and OL are
With 20 the output latches OL10-OL1F and O
L20 to OL2F will be described. Further, in the following circuit diagrams, a MOSFET having an arrow on its channel (back gate) portion is a P-channel MOSFET, and is shown separately from an N-channel MOSFET without an arrow.

First, referring to FIG. 2, the data input / output circuit I
As described above, O is 16 data input buffers DIB provided corresponding to the data input / output terminals D0 to DF, that is, the internal data buses DBUS0 to DBUSF.
0-DIBF and input latches IL0-ILF, first stage output latches OL10-OL1F, second stage output latches OL20-OL2F and data output buffer DOB
0 to DOBF. Of these, the input terminals of the data input buffers DIB0 to DIBF are coupled to the corresponding data input / output terminals D0 to DF, and the output terminals thereof are coupled to the input terminals of the corresponding input latches IL0 to ILF. The output terminals of these input latches IL0 to ILF are
It is coupled to corresponding internal data buses DBUS0-DBUSF. On the other hand, the input terminals of the first-stage output latches OL10-OL1F have corresponding internal data buses DBUS0-DBUS0-DB1.
It is coupled to the USF and its output terminal is coupled to the input terminal of the corresponding second stage output latch OL20-OL2F.
The output terminals of these output latches OL20 to OL2F are
The data output buffers DOB0 to DOBF are coupled to the corresponding input terminals of the data output buffers DOB0 to DOB.
The output terminal of F is the corresponding data input / output terminal D0 to DF.
Is combined with

The internal control signal IL is commonly supplied from the timing generation circuit TG to the input latches IL0 to ILF, and the output control signal DOC is supplied to the data output buffers DOB0 to DOBF. An internal control signal OL1 (first output latch control signal) is commonly supplied from the timing generation circuit TG to the first-stage output latches OL10 to OL1F, and the second-stage output latches OL20 to OL2F are internally controlled. Signal OL2 (second output latch control signal)
Are commonly supplied.

Here, the first-stage output latches OL10 to OL1F forming the data input / output circuit IO have a pair of clocked inverters whose output terminals are commonly coupled, as represented by the output latch OL10 in FIG. CV1 and CV
2 inclusive. In the following, taking the output latch OL10, the output latch OL20 and the data output buffer DOB0 as an example,
Stage output latches OL10 to OL1F, second stage output latch O
L20 to OL2F and data output buffer DOB0
-Proceed with a concrete explanation of DOBF.

In FIG. 3, the first stage output latch OL10 is shown.
The input terminal of the clocked inverter CV1 constituting
It is coupled as an input terminal of output latch OL10 to corresponding internal data bus DBUS0. Further, the output terminals of the clocked inverters CV1 and CV2 are coupled to the input terminal of the second-stage output latch OL20, that is, the input terminal of the clocked inverter CV3 that constitutes it, and
It is coupled to the input terminal of clocked inverter CV2 via inverter V1. The internal control signal OL1 is commonly supplied to the gate of the N-channel MOSFET that serves as the non-inverting control terminal of the clocked inverter CV1 and the gate of the P-channel MOSFET that serves as the inverting control terminal of the clocked inverter CV2. P-channel MOSFET used as an inversion control terminal
An inverted signal from the inverter V2 is commonly supplied to the gate of the N-channel MOSFET serving as the non-inversion control terminal of the clocked inverter CV2.

As a result, the clocked inverter CV1
The second stage output latch outputs the read data supplied from the corresponding read amplifier of the main amplifier MA via the internal data bus DBUS0 by selectively setting the output latch control signal OL1 to the high level. OL2
It acts to selectively invert and transmit to. Further, the clocked inverter CV2 is selectively brought into a transmission state by setting the output latch control signal OL1 to a low level, and constitutes a latch circuit together with the inverter V1 to set the level immediately before the output terminal of the clocked inverter CV1. It acts to hold. In other words, the first circuit
The stage output latch OL10 is in a so-called through state so as to logically invert read data supplied via the internal data bus DBUS0 and transmit the read data to the subsequent stage when the output latch control signal OL1 is set to a high level, and output. When the latch control signal OL1 is set to the low level, a so-called latch state is set in order to hold the logic level immediately before that.

Similarly, the input terminal of the clocked inverter CV3 forming the second stage output latch OL20 becomes the input terminal of the output latch OL20 and the first stage output latch OL.
10 output terminals. The output terminals of the clocked inverters CV3 and CV4 are connected to the output latch OL2.
A corresponding data output buffer DO as an output terminal of 0
The input terminal of B0, that is, the inverter V5 that constitutes it
Also, it is coupled to one input terminal of NOR gate NO2 and to the input terminal of clocked inverter CV4 via inverter V3. The gate of the N-channel MOSFET that serves as the non-inverting control terminal of the clocked inverter CV3 and the P-channel MOSFE that serves as the inverting control terminal of the clocked inverter CV4.
The internal control signal OL2 is commonly supplied to the gate of T, and the gate of the P-channel MOSFET that serves as the inverting control terminal of the clocked inverter CV3 and the gate of the N-channel MOSFET that serves as the non-inverting control terminal of the clocked inverter CV4. , And the inverted signal from the inverter V4 is commonly supplied.

As a result, the clocked inverter CV3
Is selectively brought into a transmission state by setting the output latch control signal OL2 to a high level, and the first stage output latch OL1
Output signal O1 of the corresponding data output buffer DOB0
It acts to selectively invert and transmit to. Further, the clocked inverter CV4 is selectively brought into a transmission state by setting the output latch control signal OL2 to a low level, and constitutes a latch circuit together with the inverter V3 to set the immediately preceding level at the output terminal of the clocked inverter CV3. It acts to hold. In other words, if you look at the entire circuit,
When the output latch control signal OL2 is at a high level, the stage output latch OL20 is brought into a through state so as to logically invert the output signal O1 of the first stage output latch OL10 and transmit it to the subsequent stage. When OL2 is set to the low level, it is set to the latch state to hold the logic level immediately before it.

Next, the data output buffer DOB0 has two N-channel type output MOSFETs N1 provided in a totem pole configuration between the power supply voltage and the ground potential of the circuit.
And N2. Of these, the output signal of the NOR gate NO1 is supplied to the gate of the output MOSFET N1, and the output signal of the NOR gate NO2 is supplied to the gate of the output MOSFET N2. The output signal O2 of the second stage output latch OL2 is supplied to one input terminal of the NOR gate NO2, and the inverted signal of the inverter V5 is supplied to one input terminal of the NOR gate NO1. An inverted signal of the output control signal DOC by the inverter V6 is commonly supplied to the other input terminals of the NOR gates NO1 and NO2. The commonly coupled sources and drains of the output MOSFETs N1 and N2 serve as the output terminals of the data output buffer DOB0 and are coupled to the corresponding data input / output terminal D0.

As a result, the output MOSFET N1 has a high level when the output signal of the NOR gate NO1 is high.
In other words, when the output control signal DOC is set to the high level and the output signal O2 of the second stage output latch OL20 is set to the high level, it is selectively turned on and is lower than the power supply voltage of the circuit by the threshold voltage. A high level output signal is output to the data input / output terminal D0. In addition, the output MOSFET N2 sets the output control signal DOC to the high level when the output signal of the NOR gate NO2 is set to the high level, that is, the second-stage output latch OL2.
When the output signal O2 of 0 is low level, it is selectively turned on, and a low level output signal such as the ground potential of the circuit is output to the data input / output terminal D0.

By the way, as shown in FIG. 4, the timing generation circuit TG includes an output latch control signal generation circuit OL1G for generating the output latch control signal OL1 and an output latch control signal generation for generating the output latch control signal OL2. And a circuit OL2G. Further, a clock buffer CLKB for transmitting the clock signal CLK as an internal clock signal CKB is further provided, and the internal clock signal CKB generated by this clock buffer is commonly supplied to the output latch control signal generation circuits OL1G and OL2G. The clock signal CLK is the synchronous DR.
When AM is used with a latency of 1, it is a pulse signal having a relatively long period such as 25 ns (nanosecond), as shown in FIG. Further, when the synchronous DRAM is used with a latency of 2, as shown in FIG. 6, it is made a pulse signal having a cycle having an intermediate length such as 15 ns.
When the RAM is used with the latency 3, as shown in FIG. 7, the pulse signal has a relatively short cycle such as 10 ns.

The output latch control signal generation circuit OL1G of the timing generation circuit TG includes a pair of clocked inverters CV5 and CV6 controlled by the internal control signal LE3, although not particularly limited thereto. Of these, the internal clock signal CKB is supplied to the input terminal of the clocked inverter CV5, and the clocked inverter CV5 is supplied.
The delay signal from the delay circuit DL1 is supplied to the input terminal of V6. The internal control signal LE3 is commonly supplied to the inversion control terminal of the clocked inverter CV5 and the non-inversion control terminal of the clocked inverter CV6, and the non-inversion control terminal of the clocked inverter CV5 and the inversion of the clocked inverter CV6 are inverted. An inversion signal from the inverter V7 is commonly supplied to the control terminal. The internal control signal LE3 is selectively set to a high level when the synchronous DRAM is set to the latency 3 read or write mode.

The output latch control signal generation circuit OL1G is
Further, the first input terminal and the output terminal include a pair of NAND gates NA3 and NA4 which are cross-coupled to each other. Among these, the output signal of the NAND gate NA1 is supplied to the second input terminal of the NAND gate NA3, and the inverted signal of the internal control signal LE1 by the inverter VA is supplied to the third input terminal thereof. Further, the NAND gate N4 has a second input terminal connected to the NAND gate N4.
The output signal of A2 is supplied to its third input terminal,
An inverted signal of the internal control signal RST by the inverter VB is supplied. The output signal of the clocked inverter CV5 is supplied to one input terminal of the NAND gate NA1, and the inverted delay signal by the inverter V8 and the delay circuit DL3 is supplied to the other input terminal. Further, a delay signal of the output signal of the clocked inverter CV6 by the delay circuit DL2 is supplied to one input terminal of the NAND gate NA2, and an inverted delay signal by the inverter V9 and the delay circuit DL4 is supplied to the other input terminal. Supplied. The output signal of the NAND gate NA3 is the output latch control signal OL1. The internal control signal LE1 is selectively set to a high level when the synchronous DRAM is set to the latency 1 read or write mode, and the internal control signal RST is set to the synchronous D.
It is selectively brought to a high level when the system including the RAM is brought into a reset state.

From these facts, the output latch control signal O
L1 is fixed to the high level as shown in FIG. 5 when the synchronous DRAM is set to the latency 1 read or write mode and the internal control signal LE1 is set to the high level. Further, when the synchronous DRAM is set to the latency 2 read or write mode, as shown in FIG. 6, it is temporarily delayed by a relatively short time tco1 from the rising edge of the clock signal CLK, that is, the internal clock signal CKB, and temporarily becomes high. When the synchronous DRAM is set to the level and the synchronous DRAM is set to the read or write mode of the latency 3, as shown in FIG. 7, the clock signal CLK, that is, the internal clock signal C
The signal is temporarily set to the high level with a delay of a relatively long time tco1 ′ corresponding to the delay time of the delay circuit DL1 from the rising edge of KB.

Thus, the synchronous D of this embodiment is
In the RAM, the output latch control signal OL for controlling the first stage output latches OL10 to OL1F of the data input / output circuit IO.
The generation timing of 1 is selectively switched according to the latency of the synchronous DRAM, whereby the level determination timing of the read data output from the selected memory cell of the memory array MARY via the internal data buses DBUS0 to DBUSF and Are matched. The output latch control signal generation circuit OL1G of the timing generation circuit TG requires a relatively deep logic circuit to selectively switch the generation timing of the output latch control signal OL1, but the generation timing of the output latch control signal OL1 is , Synchronous DRA
Since M does not affect the access time of the latency 3 operating with the clock signal CLK having the highest frequency,
This does not cause any problems. Needless to say, when the synchronous DRAM is set to the read or write mode with the latency of 1 and the output latch control signal OL1 is fixed to the high level, the first stage output latches OL10 to OL1F of the data input / output circuit IO constantly perform the through operation. To be done.

Next, the output latch control signal generation circuit OL2G of the timing generation circuit TG receives the internal clock signal CKB at one input terminal thereof, and the inverter VC of the internal clock signal CKB and the delay circuit DL5 at the other input terminal thereof. And an OR gate OG1 for receiving the inverted delay signal by The output signal of the OR gate OG1 is supplied to one input terminal of the NAND gate NA5, and the internal control signal LE3 is supplied to the other input terminal of the NAND gate NA5. The output signal of the NAND gate NA5 is the output latch control signal OL2.

As a result, the output latch control signal OL2
When the synchronous DRAM is set to the read or write mode of the latency 1 or 2 and the internal control signal LE3 is set to the low level, it is constantly fixed to the high level and the synchronous control is performed. DR
When the AM is set to the read or write mode of the latency 3, as shown in FIG. 7, it is temporarily set to the high level with a delay of a relatively short time tco2 from the rising edge of the clock signal CLK, that is, the internal clock signal CKB. Will be things. As is clear from FIG.
The output latch control signal generation circuit OL2G does not include a complicated logic circuit for switching the generation timing of the output latch control signal OL2 according to the latency, and the output latch control signal OL2 is significantly delayed from the rising edge of the clock signal CLK. Generated without. As a result,
The output latch control signal generation circuit OL1G switches the generation timing of the output latch control signal OL1 for each latency without sacrificing the access time in the read mode of the latency 3 of the synchronous DRAM to match the read data level determination timing. Can be made. When the synchronous DRAM is set to the read or write mode with the latency 1 or 2 and the output latch control signal OL2 is fixed to the high level, the second stage output latches OL20 to OL2F are constantly slewed.

When the synchronous DRAM is set to the read mode, the clock signal CLK is first set to the high level when the read command is input, and then the memory array M is provided to the internal data buses DBUS0 to DBUSF.
Read data (a) of the selected memory cell of ARY
The time taa until is output is constant irrespective of latency, which causes the generation timing of the output latch control signal OL1 to be switched for each latency. When the synchronous DRAM is set to the latency 1 read mode, the output latch control signals OL1 and OL2 are fixed to the high level as shown in FIG. 5, and the first stage output latches OL10 to OL10 of the data input / output circuit IO are fixed. The OL1F and the second-stage output latches OL20 to OL2F are all through-operated as shown in FIG. At this time, the read data (a) and the like output via the internal data buses DBUS0 to DBUSF are directly output to the first stage output latch OL10.
~ OL1F and second stage output latches OL20 to OL2
The output signal O1 or O2 passes through F and is output from the corresponding data input / output terminals D0 to DF upon receiving the high level of the output control signal DOC. Therefore, the access device of the synchronous DRAM is operated by the clock signal CLK.
The read data (a) or the like output via the data input / output terminals D0 to DF can be fetched at the next rising edge of, that is, at the rising edge of the clock signal CLK after one cycle.

On the other hand, when the synchronous DRAM is set to the latency 2 read mode, the output latch control signal OL1 has a relatively short time tco1 from the rising edge of the clock signal CLK as shown in FIG.
Generated with a delay, the output latch control signal OL2 is fixed to the high level. Therefore, the data input / output circuit I
The first-stage output latches OL10 to OL1F of O become the through state at an effective timing immediately after the read data (a) of the selected memory cell of the memory array MARY is established on the internal data buses DBUS0 to DBUSF. Read data (a) and the like are output latches OL20 to OL
The output latch control signal OL
After 1 is returned to the low level, it remains in the latched state and holds these read data, and the second stage output latch OL2
0 to OL2F continues to be transmitted. Further, the second-stage output latches OL20 to OL2F receive the high level of the output latch control signal OL2 and steadily perform the through operation, and the output signal O2 thereof receives the high level of the output control signal DOC to respond. It is output to the data input / output terminals D0 to DF.
As a result, the access device of the synchronous DRAM is
The read data (a) output through the data input / output terminals D0 to DF can be fetched at the rising edge of the clock signal CLK after two cycles.

Next, when the synchronous DRAM is set to the latency 3 read mode, the output latch control signal OL1 is, as shown in FIG. 7, a relatively long time tco from the rising edge of the clock signal CLK.
Generated with a delay of 1 ', and output latch control signal OL2
Is generated with a relatively short time tco2 delayed from the rising edge of the clock signal CLK as described above. Therefore, the first-stage output latches OL10 to OL1F of the data input / output circuit IO similarly have the memory array MARY.
The read data (a) or the like of the selected memory cell becomes a through state at an effective timing immediately after being established on the internal data buses DBUS0 to DBUSF, and starts transmitting the read data (a) and the like to the output latches OL20 to OL2F. At the same time, even after the output latch control signal OL1 is returned to the low level, it remains in the latched state and holds these read data, and continues to be transmitted to the second stage output latches OL20 to OL2F. In addition, the second stage output latches OL20 to OL
2F becomes a through state when the output signal O1 of the first stage output latches OL10 to OL1F is established, and the read data (a) and the like are output to the data output buffers DOB0 to DOB.
The data output buffers DOB0 to DOB are held in the latch state even after the output latch control signal OL2 is returned to the low level.
Continue to communicate to F. Second stage output latches OL20 to OL2
The output signal O2 of F is output to the corresponding data input / output terminals D0 to DF in response to the high level of the output control signal DOC. As a result, the access device for the synchronous DRAM can take in the read data (a) or the like output via the data input / output terminals D0 to DF at the rising edge of the clock signal CLK after three cycles.

FIG. 10 shows the synchronous DRAM of FIG.
A block diagram of an embodiment of a computer system to which is applied is shown. The outline of the application system of the synchronous DRAM of this embodiment and its features will be described with reference to FIG.

In FIG. 10, the computer system of this embodiment has a so-called stored program type central processing unit CPU as its basic constituent element. The central processing unit CPU has a random access memory RAM1 composed of a normal static RAM and a synchronous DRAM to which the present invention is applied, via a system bus SBUS.
And a random access memory RAM2 consisting of The system bus SBUS is further coupled to a read only memory ROM including a mask ROM and the like, a display control device DPYC and a peripheral device controller PERC. The display control device DPYC
Includes an image memory VRAM including a synchronous DRAM to which the present invention is applied. A display device DPY is coupled to the display control device DPYC, and a keyboard KB is connected to the peripheral device controller PERC.
D and the external storage device EXM are coupled.

The central processing unit CPU performs step operation according to a control program stored in advance in the read-only memory ROM, and controls / controls each unit of the computer system. The random access memory RAM1 is used, for example, as a cache memory, and the random access memory RAM2 is used, for example, as a read only memory R.
A control program, operation data, and the like transmitted from the OM to the central processing unit CPU are temporarily stored and used as a buffer memory for relaying. Further, the display control device DPYC is used for display control of the display device DPY, and the peripheral device controller PERC operates the keyboard K
It controls various peripheral devices such as a BD and an external storage device EXM. The computer system includes a power supply device POWS. The power supply device POWS forms a stable predetermined DC power supply voltage based on a predetermined AC input power supply voltage and supplies the DC power supply voltage to each unit of the computer system.

In this embodiment, in the synchronous DRAM constituting the random access memory RAM2 and the image memory VRAM of the display control device DPYC, the first read data after the column address strobe signal is set to the effective level as described above. The first stage output latch OL1 has a latency mode in which the time until output is selectively delayed by, for example, 1 to 3 cycles of the clock signal, and each is serially coupled.
0 to OL1F and second stage output latches OL20 to OL
A data input / output circuit IO including 2F is provided. Further, in this embodiment, the first stage output latch OL which constitutes the data input / output circuit IO in the latency 2 read mode is used.
10 to OL1F are latched, the second stage output latch is through-operated, and the generation timing of the output latch control signal supplied to the first stage output latch is switched for each latency. Therefore, while the generation timing of the output latch control signal supplied to the second stage output latch is fixed in the shortest state, the generation timing of the output latch control signal supplied to the first stage output latch depends on the number of delay cycles. This optimizes the operation margin of the synchronous DRAM or the like and stabilizes its operation without sacrificing the access time of the latency 3 in the read mode. As a result, the operation of the computer system is stabilized while maintaining the high speed of the machine cycle.

The effects obtained by the above-mentioned embodiment are as follows. That is, (1) it has a latency mode in which the time from when the column address strobe signal is set to the effective level to when the first read data is output can be selectively delayed by, for example, 1 to 3 cycles of the clock signal, Synchronous DRA with serially coupled two-stage output latch
In the read mode of latency 2 in M etc., the first
Supply the second-stage output latch by latching the second-stage output latch and by-passing the second-stage output latch, and by switching the generation timing of the output-latch control signal supplied to the first-stage output latch for each latency. It is possible to optimize the generation timing of the output latch control signal supplied to the first-stage output latch in accordance with the number of delay cycles while fixing the generation timing of the output latch control signal that is generated in the shortest state. can get. (2) According to the above item (1), the operation margin of the synchronous DRAM or the like can be increased and its operation can be stabilized without sacrificing the access time in the read mode of the latency 3. . (3) According to the above items (1) and (2), it is possible to stabilize the operation of the computer system including the synchronous DRAM while maintaining the high speed of the machine cycle.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the synchronous DRAM can have any bit configuration such as a x8 bit configuration or a x32 bit configuration, and can have an arbitrary number of banks.
Further, the internal data buses DBUS0 to DBUSF can be dedicated for writing or reading, and the data input / output terminals D0 to DF can also be separated as data input terminals and data output terminals according to their uses. The memory array MARY forming each bank can be divided into a plurality of mats including its direct peripheral circuits. Further, the block configuration of the synchronous DRAM, the names and combinations of the activation control signal and the internal control signal, their logic levels, etc. are not restricted by this embodiment.

In FIG. 2, the data input / output circuit IO is
An input protection circuit may be included corresponding to the data input / output terminals D0 to DF. In FIG. 3, first-stage output latches OL10-OL1F, which form the data input / output circuit IO,
The second stage output latches OL20 to OL2F and the data output buffers DOB0 to DOBF can adopt various embodiments, and the output latch control signal generation circuits OL1G and OL2 of the timing generation circuit TG of FIG. 4 can be adopted.
The same applies to G. 5 to 7, the effective levels of the internal control signals and the output control signals can take various embodiments as long as the necessary logical conditions are satisfied. In FIG. 10, the block configuration of the computer system can adopt various embodiments, and the application range of the synchronous DRAM is not limited to this embodiment.

In the above description, the case where the invention made by the present inventor is mainly applied to the synchronous DRAM and the computer system to which the invention is applied, which is the background field of the invention, has been described. However, the invention is not limited thereto. Instead, for example, the present invention can be applied to various memory integrated circuits which operate in synchronization with a clock signal and various digital systems including similar memory integrated circuits. INDUSTRIAL APPLICABILITY The present invention is widely applicable to a semiconductor memory device having a data input / output circuit having at least a latency function and including serially coupled two-stage output latches, and a device and a system including such a semiconductor memory device. .

[0052]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, it has a latency mode in which the time from when the column address strobe signal is set to the effective level until the first read data is output can be selectively delayed by, for example, 1 to 3 cycles of the clock signal, and the serial connection is performed. In a synchronous DRAM or the like having a two-stage output latch configured as described above, the first-stage output latch is latched in the latency 2 read mode, the second-stage output latch is slewed, and the first-stage output latch is supplied. By switching the generation timing of the output latch control signal for each latency, the generation timing of the output latch control signal supplied to the second stage output latch is fixed to the first stage output latch while being fixed in the shortest state. Output latch control signal generation timing is optimized according to the number of delay cycles It is possible. As a result, the operation margin of the synchronous DRAM or the like having the latency mode can be increased and its operation can be stabilized without sacrificing the access time in the read mode of the latency 3.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronous DRAM to which the present invention is applied.

2 is a block diagram showing an embodiment of a data input / output circuit included in the synchronous DRAM of FIG.

FIG. 3 is a partial circuit diagram showing an embodiment of the data input / output circuit of FIG.

4 is a partial circuit diagram showing an embodiment of a timing generation circuit included in the synchronous DRAM of FIG.

5 is a latency 1 of the synchronous DRAM of FIG.
3 is a signal waveform diagram showing an example of a read mode of FIG.

6 is a latency 2 of the synchronous DRAM of FIG.
3 is a signal waveform diagram showing an example of a read mode of FIG.

7 is a latency 3 of the synchronous DRAM of FIG.
3 is a signal waveform diagram showing an example of a read mode of FIG.

FIG. 8 is a signal waveform diagram showing an example of a read mode of a latency 2 of the synchronous DRAM developed by the inventors of the present application prior to the present invention.

FIG. 9 is a conceptual diagram for comparatively explaining operation modes of output latches included in the data input / output circuits of the synchronous DRAMs of FIGS. 1 and 8;

10 is a system configuration diagram showing an embodiment of a computer system to which the synchronous DRAM of FIG. 1 is applied.

[Explanation of symbols]

BNK0 to BNK1 ... bank, MARY ... memory array, RD ... row address decoder, SA ... sense amplifier, CD ... column address decoder, MA ... main amplifier, RB ... row address buffer, CB ...
Column address buffer, BS ... Bank selection circuit, I
O: data input / output circuit, TG: timing generation circuit. D0 to DF ... Data input / output terminals, DIB0 to DI
BF ... data input buffer, IL0-ILF ... input latch, DBUS0-DBUSF ... internal data bus,
OL10-OL1F ... 1st stage output latch, OL20-
OL2F ... Second stage output latch, DOB0 to DOBF ...
… Data output buffer. DOC ... Output control signal, OL
1 to OL2 ... Output latch control signal. CLK ... Clock signal, CLKB ... Clock buffer, OL1G to O
L2G ... Output latch control signal generation circuit. NO1 to NO
2 ... NOR gate, NA1 to NA5 ... NAND gate, OG1 ... OR gate, CV1 to CV6 ... Clocked inverter, V1
VC ... CMOS inverter, N1-N2 ... N-channel MOSFET, DL1-DL5 ... Delay circuit. Y0
~ Yi ... internal address signal, O1 ... first stage output latch output signal, O2 ... second stage output latch output signal. CP
U: Central processing unit, SBUS: System bus, RA
M1-RAM2 ... Random access memory, ROM ...
... Read-only memory, DPYC ... Display control device, VRAM ... Image memory, DPY ... Display device, PERC ... Peripheral device controller, KBD
...... Keyboard, EXM ... External storage device, POWS ...
… Power supply.

Claims (3)

[Claims] 1. A first latency mode to a third latency mode, which operate synchronously according to a predetermined clock signal and delay the output of read data by 1 to 3 cycles of the clock signal with respect to a predetermined activation control signal. A first-stage output latch that operates according to a first output latch control signal, performs a through operation in the first latency mode, and performs a latch operation in a second or third latency mode; Two
In accordance with the output latch control signal of No. 3, and the through operation is performed in the first or second latency mode.
And a data input / output circuit including a second stage output latch which is latched in the latency mode. 2. The generation timing of the first output latch control signal is changed according to the latency mode, and the generation timing of the second output latch control signal is fixed regardless of the latency mode. 2. The semiconductor memory device according to claim 1, wherein the access time to the clock signal in the read mode is regulated by the generation timing of the second output latch control signal. apparatus. 3. The semiconductor memory device comprises a synchronous D
3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a RAM, and the activation control signal is a column address strobe signal.