JPH08138377A - Semiconductor memory device - Google Patents

Abstract

(57) [Summary] (Correction) [Purpose] To reduce the size and cost of a chip such as a synchronous DRAM equipped with an internal data bus of multi-bit configuration. [Structure] Data input buffer IB and write amplifier WA
The write internal data bus provided between the read internal data bus D and the read amplifier RA is also used as the read internal data bus provided between the read amplifier RA and the data output buffer OB.
BUS0 etc. Further, these internal data buses are used as a single signal line, and the write bus driver WD, the read bus driver RD, and the read bus driver RD are provided on the output terminal side of the data input buffer IB and the read amplifier RA and the input terminal side of the write amplifier WA and the data output buffer OB. A write bus receiver WR and a read bus receiver RR are provided respectively. Further, the level of the signal transmitted by the internal data bus DBUS0 or the like is set to the MOS level, and the internal data bus DBUS0 or the like is coupled to the input / output node of the bus latch circuit BL to which the CMOS inverters V1 and V2 are cross coupled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a synchronous DRAM having a multi-bit structure.
The present invention relates to a (dynamic random access memory) and a technique that is particularly effective when used for cost reduction.

[0002]

2. Description of the Related Art There is a so-called synchronous DRAM having a multi-bit structure and its operation is synchronized in accordance with a predetermined clock signal. The synchronous DRAM is provided with a plurality of data input buffers and data output buffers provided corresponding to each bit of input / output data, and between these data input buffers and data output buffers and the corresponding write amplifier or read amplifier. An internal data bus for transmitting write data or read data is provided.

[0003]

[Problems to be Solved by the Invention] Conventional Synchronous D
In the RAM, the internal data bus is separated into a so-called write internal data bus for writing provided between the data input buffer and the write amplifier and a so-called read internal data bus for reading provided between the read amplifier and the data output buffer. Moreover, both are complementary signal lines composed of non-inverted and inverted signal lines. For this reason,
When the bit configuration of the synchronous DRAM is made into a multi-bit configuration such as a x16 bit configuration or a x32 bit configuration,
Correspondingly, the number of bits of the write internal data bus and the read internal data bus arranged over a relatively long distance on the chip (semiconductor substrate) also increases, and the required layout area increases. As a result, synchronous DRAM
However, there is a problem that the chip size is increased, which hinders the cost reduction.

An object of the present invention is to reduce the chip size of a synchronous DRAM or the like having a multi-bit structure and to reduce its cost.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a synchronous DRAM or the like having a multi-bit configuration and having a pair of banks each made up of a plurality of memory mats, the write internal data bus provided between the data input buffer and the corresponding write amplifier corresponds to the read amplifier. It also functions as a read internal data bus provided between the data output buffer and the data output buffer, and these internal data buses are used as a single signal line, and the input terminal of the data input buffer and read amplifier and the input of the write amplifier and data output buffer A bus driver and a bus receiver are provided on the terminal side. Further, the levels of the write signal and the read signal transmitted by the internal data bus are set to the MOS level, and each bit of the internal data bus is connected to the input / output node of the bus latch circuit formed by cross-coupling the CMOS inverters. Further, a plurality of memory mats constituting each bank, and write amplifiers and read amplifiers are arranged in the normal order so that the wiring length of the corresponding internal data bus is substantially constant.

[0007]

According to the above means, the transmission delay time of each bit of the internal data bus is set to a substantially constant value, and the signal level of the internal data bus when both the bus drivers are in the high impedance state is determined, The predetermined number of internal data buses can be reduced and the required layout area can be significantly reduced. As a result, the synchronous DRAM adopting a multi-bit configuration while stabilizing its operation
It is possible to reduce the chip size such as, and to reduce the cost.

[0008]

1 is a block diagram showing an embodiment of a synchronous DRAM to which the present invention is applied. 2 shows a block diagram of one embodiment of the bank BANK0 included in the synchronous DRAM of FIG. 1, and FIG. 3 shows a chip layout diagram of one embodiment of the synchronous DRAM of FIG. Has been done. Based on these figures,
First, the structure and operation of the synchronous DRAM of this embodiment and the outline of the chip layout will be described. The circuit elements forming each block in FIG. 1 are not particularly limited, but known MOSFETs (metal oxide semiconductor field effect transistors. In this specification, MOSFETs are generically called insulated gate field effect transistors. It is formed on one semiconductor substrate such as single crystal silicon by the manufacturing technology of integrated circuits. Further, in FIG. 2, bank B
The description of the banks BANK0 and BANK1 will be given by taking ANK0 as an example. However, since the bank BANK1 has the same configuration as this, it should be analogized. Furthermore, in the following description regarding the chip layout, the top, bottom, left and right of the semiconductor substrate surface will be expressed with the positional relationship of FIG.

In FIG. 1, the synchronous DRAM of this embodiment comprises a pair of banks BANK0 and BANK1, each of which has a memory array MARY arranged to occupy most of its layout area and a direct peripheral circuit. A row address decoder RD, a sense amplifier SA and a column address decoder CD, and a main amplifier MA including a write amplifier and a read amplifier.

In this embodiment, the synchronous DRA
M has × n, that is, × 16 bits, and n pieces, that is, 1
Six data input / output terminals D0 to DF (here, the serial numbers of the 16 data input / output terminals etc. provided are represented by hexadecimal numbers, the same applies hereinafter). Further, the memory arrays MARY forming the banks BANK0 and BANK1 respectively have 16 memory arrays MARY0 to MAR corresponding to the data input / output terminals D0 to DF as illustrated in FIG.
The sense amplifier SA, the row address decoder RD, and the main amplifier MA are also divided into YFs, and the 16 sense amplifiers SA0 to SAF, the row address decoders RD0 to RDF, and the main amplifier MA0 are also correspondingly provided.
It is divided into 0 to MA0F (MA10 to MA1F). Among them, the memory array, the sense amplifier, and the row address decoder are combined to form 16 memory mats MM00 to MM0F (MM10).
~ MM1F). In addition, the main amplifier MA00
.About.MA0F and MA10 to MA1F are coupled to corresponding unit circuits of data input / output circuit IO via corresponding internal data buses DBUS0 to DBUSF.

On the other hand, memory mats MM00 to MM0F and MM forming banks BANK0 and BANK1.
As shown in FIG. 3, 10 to MM1F are arranged adjacent to each other in the bit line extension direction, that is, in the vertical direction of the chip, corresponding to the upper or lower 8 bits of the input / output data, and are arranged inside the vertical direction. Is a column address decoder CD divided into a total of four, that is, CD00 and CD01.
And CD10 and CD11 respectively.
In addition, inside the horizontal direction of these memory mats, the corresponding main amplifiers MA00 to MA07, MA08 to M are provided.
A0F, MA10-MA17 and MA18-MA1
Four Fs are collectively arranged, and four internal data buses DBUS0 to DBUSF are similarly collectively arranged inside thereof. In the vertical central portion of the semiconductor substrate SUB,
Data input / output circuit IO divided into 16 pieces, that is, IO0
-IOFs are arranged in a predetermined order.

By the way, the banks BANK0 and BANK
1 is selectively activated in accordance with bank selection signals BS0 to BS1, and corresponding to memory mats MM00 to M.
M0F, MM10 to MM1F and main amplifier MA
00 to MA0F and MA10 to MA1F are selectively activated. In this embodiment, selectively activated memory mats MM00 to MM07 and MM1.
As is clear from FIG. 3, 0 to MM17 are arranged in the forward order from the upper part to the lower part of the chip surface, and the corresponding main amplifiers MA00 to MA07 and MA10 to MA17 are positively arranged close to each other although they are arranged in groups of four. Placed in order.
Further, the memory mats MM08 to M that are selectively activated.
On the contrary, M0F and MM18 to MM1F are arranged in the forward order from the bottom to the top of the chip surface, and the corresponding main amplifier M
Although A08 to MA0F and MA18 to MA1F are also arranged in groups of four, they are also arranged in a normal order close to each other. As a result, in the synchronous DRAM of this embodiment, the main amplifiers MA00 to MA03 and MA10 to MA13, M are provided.
A04-MA07, MA14-MA17, MA08-M
A0B and MA18-MA1B and MA0C-MA0
Internal data buses DBUS0 to DBUS3, DBUS4 to DBUS7, D commonly connecting F and MA1C to MA1F
BUS8-DBUSB and DBUSC-DBUSF
Have almost the same wiring length, and thereby the transmission delay time has almost the same value.

On the other hand, in this embodiment, the internal data bus DBUS is arranged over the chip surface over a relatively long distance.
Each of 0 to DBUSF is composed of a single signal line, and is also used as a write internal data bus for writing and a read internal data bus for reading. Further, the data input / output circuit IO, that is, IO0 to IOF
Data input buffer IB and main amplifier MA constituting the
A write bus driver WD and a read bus driver RD are respectively provided on the output terminal side of the read amplifiers RA that compose 00 to MA0F and MA10 to MA1F, and the main amplifiers MA00 to MA0F and MA10 are provided.
-MA1F and the data input / output circuit IO, that is, the input terminal side of the data output buffer OB forming IO0-IOF, the write bus receiver WR.
And a read bus receiver RR, respectively. Further, each bit of the internal data bus is connected to the bus latch circuit B.
Each of the unit bus latch circuits UBL0 to UBLF corresponding to L is connected to each of the unit bus latch circuits UBL0 to UBLF.
It includes a latch circuit in which a pair of CMOS inverters are cross-coupled. As a result, in the synchronous DRAM of this embodiment, even when the write bus driver WD and the read bus driver RD are in the high impedance state, the level of the signal transmitted via the internal data bus is fixed and the internal data is determined. The required number of buses can be reduced and the required layout area can be significantly reduced. The bus configuration of the internal data bus of the synchronous DRAM will be described later in detail.

Returning to the explanation of FIG. The memory arrays MARY forming the banks BANK0 and BANK1 include a predetermined number of word lines arranged in parallel in the vertical direction in the figure and a predetermined set of complementary bit lines arranged in parallel in the horizontal direction. At the intersection of these word lines and complementary bit lines,
A large number of dynamic memory cells including information storage capacitors and address selection MOSFETs are arranged in a grid.

The word lines forming the memory arrays MARY of the banks BANK0 and BANK1 are coupled to the corresponding row address decoders RD and are alternatively set to the selected state. To these row address decoders RD, i-bit internal address signals X0 to Xi-1 excluding the most significant bit are commonly supplied from the row address buffer RB, and an internal control signal RG is commonly supplied from the timing generation circuit TG. Supplied. The row address buffer RB is supplied with the X address signals AX0 to AXi in a time division manner via the address input terminals A0 to Ai, and the timing control circuit TG supplies the internal control signal R.
L is supplied.

The row address buffer RB has an X address signal A input via address input terminals A0 to Ai.
X0 to AXi are fetched and held according to internal control signal RL, and internal address signals X0 to Xi are formed based on these X address signals. Of these, the most significant bit internal address signal Xi is supplied to the bank selection circuit BS and the other internal address signals X0 to Xi-4.
Are commonly supplied to the row address decoders RD of the banks BANK0 and BANK1.

The bank selection circuit BS decodes the internal address signal Xi supplied from the row address buffer RB and selectively sets the corresponding bank selection signals BS0 to BS1 to the high level. Also, banks BANK0 and B
The row address decoder RD of ANK1 has the internal control signal RG set to the high level and the corresponding bank selection signal B.
When S0 to BS1 are set to the high level, they are selectively brought into the operating state, and the internal address signals X0 to Xi-1
Is decoded and the designated word line of the corresponding memory array MARY is selectively set to the high level selected state.

Next, the complementary bit lines forming the memory array MARY of the banks BANK0 and BANK1 are coupled to the corresponding sense amplifier SA. A bit line selection signal of a predetermined bit is supplied from the corresponding column address decoder CD to each of these sense amplifiers SA. Further, the internal control signal P from the timing generation circuit TG
A is commonly supplied, and corresponding bank selection signals BS0 to BS1 are supplied from the bank selection circuit BS.
On the other hand, each column address decoder CD is commonly supplied with the internal address signals Y0 to Yi of i + 1 bits from the column address buffer CB. Further, the internal control signal CG is commonly supplied from the timing generation circuit TG, and the corresponding bank selection signals BS0 to B0 are supplied from the bank selection circuit BS.
S1 is supplied respectively. Column address buffer C
B is supplied with Y address signals AY0 to AYi in a time division manner via address input terminals A0 to Ai, and an internal control signal CL is supplied from a timing generation circuit TG.

The column address buffer CB fetches the Y address signals AY0 to AYi supplied via the address input terminals A0 to Ai in accordance with the internal control signal CL,
The internal address signals Y0 to Yi are formed based on these Y address signals while being held and supplied to the column address decoder CD of each bank. The column address decoder CD of each bank has the internal control signal CG set to the high level and the corresponding bank selection signals BS0 to B0.
When S1 is set to the high level, it is selectively brought into the operating state, the internal address signals Y0 to Yi are decoded, and the corresponding bit line selection signals are selectively set to the high level.

On the other hand, the sense amplifier SA of each bank includes a predetermined number of unit circuits provided corresponding to the complementary bit lines of the corresponding memory array MARY, and each of these unit circuits has a pair of CMOS inverters. And a pair of switch MOSFETs of N-channel type. Among them, the unit amplifier circuit is selectively and simultaneously activated by setting the internal control signal PA to the high level and the corresponding bank selection signals BS0 to BS1 to the high level, and the corresponding memory array MARY. A minute read signal output from a predetermined number of memory cells coupled to the selected word line via the corresponding complementary bit line is amplified to be a high level or low level binary read signal. In addition, switch MOSFETs that make up each unit circuit
Is 1 after receiving the high level of the corresponding bit line selection signal.
The memory array MAR is selectively turned on by 6 pairs each.
16 sets of complementary bit lines corresponding to Y and complementary common data lines CD00 * to CD0F * or CD10 * to CD1F
* (Here, for example, the non-inverted common data line CD00T and the inverted common data line CD00B are collectively denoted by an asterisk such as a complementary common data line CD00 *. Also, when it is enabled, it is selectively set to a high level. A so-called non-inverted signal or the like that is set as a level is indicated by adding T to the end of the name, and an inverted signal or the like that is selectively set to low level when it is enabled is added by B at the end of the name. The same applies to the following).

Complementary common data line CD00 * to which 16 designated complementary bit lines of the memory array MARY of the bank BANK0 or BANK1 are selectively connected, respectively.
.About.CD0F * and CD10 * to CD1F * are coupled to the corresponding main amplifier MA. As described above, these main amplifiers MA have complementary common data lines CD00.
* To CD0F * and CD10 * to CD1F * are divided into 16 main amplifiers MA00 to MA0F and MA10 to MA1F. Each of these main amplifiers has a write bus receiver W, as will be described later.
R, write amplifier WA, read amplifier RA and read bus driver RD are included. Of these, the input terminal of each write bus receiver WR is the corresponding internal data bus DBUS0.
To DBUSF are commonly connected, and their output terminals are respectively connected to the input terminals of the corresponding write amplifier WA. The output terminal of each write amplifier WA has a corresponding complementary common data line CD00 * to CD0F * or CD10 * to CD.
1F *, respectively. On the other hand, each read amplifier R
The input terminal of A is the corresponding complementary common data line CD00 *
-CD0F * and CD10 * -CD1F *, respectively, and their output terminals are connected to the input terminals of the corresponding read bus driver RD. The output terminal of each read bus driver RD has a corresponding internal data bus DBUS.
0 to DBUSF are commonly connected. The main amplifier MA includes an internal control signal MWE from the timing generation circuit TG,
MRE and BRE are commonly supplied, and the bank selection circuit B
Corresponding bank selection signals BS0 to BS1 are supplied from S, respectively.

Internal data buses DBUS0 to DBUSF
Are coupled to data input / output circuit IO and to bus latch circuit BL. Here, data input / output circuit IO is divided into 16 data input / output circuits IO0-IOF corresponding to internal data buses DBUS0-DBUSF, and each of these data input / output circuits IO0-IOF is provided with a data input buffer. It includes an IB, a write bus driver WD, a read bus receiver RR and a data output buffer OB. Of these, the input terminal of each data input buffer IB is commonly coupled to the corresponding data input / output terminals D0 to DF, and the output terminal thereof is coupled to the input terminal of the corresponding write bus driver WD. Each light bus driver W
The output terminal of D corresponds to the corresponding internal data bus DBUS0 to DBUS0.
Commonly coupled to DBUSF respectively. On the other hand, the input terminal of each read bus receiver RR is commonly coupled to the corresponding internal data bus DBUS0 to DBUSF, and the output terminal thereof is coupled to the input terminal of the corresponding data output buffer OB. The output terminals of each data output buffer OB are commonly coupled to the corresponding data input / output terminals D0 to DF. The data input / output circuit IO is supplied with internal control signals DIE, BWE, BRL and DOE from the timing generation circuit TG. Internal data buses DBUS0 to DBUSF
Are all composed of a single signal line as described above.

The data input buffers IB of the data input / output circuits IO0 to IOF take in the write data input via the data input / output terminals D0 to DF according to the internal control signal DIE when the synchronous DRAM is in the write mode. , To the corresponding write bus driver WD. Further, the write bus driver WD is selectively brought into a transmission state in response to the high level of the internal control signal BWE,
The write data supplied from the corresponding data input buffer IB is output to the internal data buses DBUS0 to DBUSF. At this time, each write bus receiver WR of the main amplifier MA is selectively latched by setting the internal control signal MWE to the high level and the corresponding bank selection signals BS0 to BS1 to the high level. The write data supplied via the buses DBUS0 to DBUSF is fetched and transmitted to the corresponding write amplifier WA. Further, each write amplifier WA is selectively brought into an operating state when the internal control signal MWE is set to the high level and the corresponding bank selection signals BS0 to BS1 are set to the high level, and the corresponding write bus receiver WR The transmitted write data is used as a predetermined write signal, and is written to the selected 16 memory cells of the corresponding memory array MARY via the complementary common data lines CD00 * to CD0F * or CD10 * to CD1F *.
When the internal control signal BWE or the corresponding bank selection signals BS0 to BS1 are at low level, the output of each write bus driver WD is in a high impedance state.

On the other hand, the read amplifier RA forming the main amplifier MA of the banks BANK0 and BANK1 is selectively operated by setting the internal control signal MRA to the high level and the corresponding bank selection signals BS0 to BS1 to the high level. Activated and corresponding memory array MARY
Complementary common data lines CD00 * to CD0F * or CD10 * to CD1F from the selected 16 memory cells
The binary read signal output via * is amplified and transmitted to the corresponding read bus driver RD. Further, each read bus driver RD has the internal control signal BRE at the high level and the corresponding bank selection signals BS0 to BS1.
Is set to a high level to selectively switch to the transmission state,
The read data output from the corresponding read amplifier RA is output to the internal data buses DBUS0 to DBUSF. At this time, the read bus receivers RR of the data input / output circuits IO0 to IOF are selectively latched by the internal control signal BRL being set to a high level, and read out transmitted via the internal data buses DBUS0 to DBUSF. Captures data and supports corresponding data output buffer O
Communicate to B. Further, the data output buffer OB receives the high level of the internal control signal DOE to be selectively operated, and sends the read data transmitted from the corresponding read bus receiver RR to the data input / output terminals D0 to DF. When the internal control signals BRE and DOE are at low level, the outputs of the read bus driver RD and the data output buffer OB are in a high impedance state.

The bus latch circuit BL is an internal data bus D.
It includes 16 unit bus latch circuits UBL0 to UBLF provided corresponding to BUS0 to DBUSF, and each of these unit bus latch circuits includes a pair of cross-coupled CMOS inverters, as described later. One of the input / output nodes of these latch circuits is coupled to the corresponding bits of internal data buses DBUS0-DBUSF, respectively. Internal data buses DBUS0 to DBUSF are
The write bus driver W corresponding to the data input / output circuit IO
When D and the corresponding read bus driver RD of the main amplifier MA are set to a high impedance state, they try to enter a floating state. At this time, each unit bus latch circuit of the bus latch circuit BL is in the latch state in which the logical level of the signal output to the corresponding bit of the internal data buses DBUS0 to DBUSF is held until then, and the signal level is determined. As a result, even when the write bus driver WD and the read bus driver RD are in the operating state for a relatively short time, the level of the signal to be transmitted is held in the internal data buses DBUS0 to DBUSF, which causes the synchronous DRAM. The substantial cycle time of can be shortened. It should be noted that the bus latch circuit BL is arranged substantially in the center of the semiconductor substrate SUB, as shown in FIG.

The timing generation circuit TG includes a clock signal CLK supplied from the outside, a chip selection signal CSB serving as a start control signal, and a row address strobe signal RAS.
Based on B, the column address strobe signal CASB and the write enable signal WEB, the above various internal control signals are selectively formed and supplied to each section.

FIG. 4 is a partial bus configuration diagram of an embodiment of the internal data bus of the synchronous DRAM of FIG. Further, FIG. 5 shows the internal data bus DB of FIG.
A circuit diagram of an embodiment of a write bus receiver WR and a read bus driver RD of a main amplifier MA00 coupled to US0 is shown, and FIG. 6 shows an embodiment of a synchronous DRAM having the internal data bus of FIG. A signal waveform diagram is shown. Based on these figures, the bus configuration of the internal data bus of the synchronous DRAM of this embodiment, the specific circuit configuration of the bus driver and the bus receiver, and their features will be described. It should be noted that in the circuit diagrams below, an MO with an arrow on its channel (back gate) part
The SFET is a P-channel type and is an N without an arrow.
It is shown separately from the channel MOSFET. Further, the following description will be given regarding the internal data bus DBUS0 of the least significant bit.
The write bus receiver WR and the read bus driver RD of the main amplifier MA00 corresponding thereto can be taken as an example, but other internal data buses DBUS1 to DBUSF
And main amplifiers MA01 to MA0F and MA10
Please analogize about MA1F. Data input / output circuit I
O, that is, the write bus driver WD and the read bus receiver RR of IO0 to IOF have the same configurations as the read bus driver RD and the write bus receiver WR of FIG. 5, respectively. Further, in FIG. 6, the write mode of the synchronous DRAM is illustrated as the cycles A and B, and the read mode thereof is illustrated as the cycles C and D.

In FIG. 4, the internal data bus DBUS0 is used.
Is composed of a single signal line, as described above, and has a write bus driver WD (second
The output terminal of the bus driver) and the input terminal of the corresponding read bus receiver RR (second bus receiver) are coupled. In addition, the main amplifier MA00 of the bank BANK0
In addition, the input terminal of the write bus receiver WR (first bus receiver) of the main amplifier MA10 of the bank BANK1 and the output terminal of the corresponding read bus driver RD (first bus driver) are commonly coupled, and further the bus latch circuit BL of the bus latch circuit BL is connected. The input / output nodes of the corresponding unit bus latch circuit UBL0 are coupled.

Here, the bus latch circuit BL includes a pair of CMOS inverters V1 and V2 whose input terminals and output terminals are cross-coupled to each other, as represented by the unit bus latch circuit UBL0. These inverters V1
And V2 are designed to have a smaller driving capability than the write bus driver WD of the data input / output circuit IO0 and the read bus driver RD of the main amplifiers MA00 and MA10. The input terminal of the inverter V1, that is, the output terminal of the inverter V2 is coupled to the corresponding internal data bus DBUS0 as one input / output node of the unit bus latch circuit UBL0. As a result, the unit bus latch circuit UBL0 of the bus latch circuit BL does not prevent the level change of the internal data bus DBUS0 by the write bus driver WD of the data input / output circuit IO0 or the read bus driver RD of the main amplifier MA00 or MA10, and these buses are not disturbed. When the driver is in the high impedance state, the logic level of the internal data bus DBUS0 is held and determined.

Next, main amplifiers MA00 and MA10
As shown in FIG. 5, the read bus driver RD of the P-channel type output MOSFET P1 provided between the power supply voltage of the circuit and its output terminal, that is, the internal data bus DBUS0, the internal data bus DBUS0 and the circuit. N-channel type output M provided between it and ground potential
And OSFET N1. Of these, the output MOSFET
An inverted signal of the output signal of the NOR gate NO1 by the inverter V6 is supplied to the gate of P1 to output the output MOSFE.
The output signal of the NOR gate NO2 is supplied to the gate of TN1. The inverted output signal OB and the non-inverted output signal OT of the read amplifier RA are respectively supplied to one input terminals of the NOR gates NO1 and NO2, and the output signal of the NAND gate NA3, that is, the inverted internal signal BRE0B is supplied to the other input terminals. Commonly supplied. Nand Gate NA3
The bank selection signal BS0 is supplied to one of the input terminals, and the internal control signal BRE is supplied to the other input terminal.

As a result, the output of the NAND gate NA3, that is, the inverted internal signal BRE0B is selectively set to the low level when the internal control signal BRE is set to the high level and the corresponding bank selection signal BS0 is set to the high level,
Upon receiving the low level of the inverted internal signal BRE0B, the read bus driver RD is selectively brought into the transmission state. At this time, the output MOSFET P1 of the read bus driver RD
Is selectively turned on when the output signal of the NOR gate NO1 is set to the high level, in other words, the inverted internal signal BRE0B is set to the low level and the inverted output signal OB of the read amplifier RA is set to the low level, A high level such as the power supply voltage of the circuit is output to the corresponding internal data bus DBUS0. Also, output MOSF
ETN1 is an inverted internal signal BRE0 when the output signal of the NOR gate NO2 is at a high level.
When B is set to low level and the non-inverted output signal OT of the read amplifier RA is set to low level, it is selectively turned on, and a low level such as the ground potential of the circuit is output to the corresponding internal data bus DBUS0. When the internal control signal BRE or the bank selection signal BS0 is set to the low level and the inverted internal signal BRE0B is set to the high level, the output MOSFETs P1 and N1 are turned off and the output of the read bus driver RD is set to the high impedance state.

On the other hand, main amplifiers MA00 and MA10
As illustrated in FIG. 5, the write bus receiver WR includes a clocked inverter CV1 having its input terminal coupled to the internal data bus DBUS0 and a latch circuit formed by cross-coupling its input terminal and output terminal. It includes a clocked inverter CV2 and an inverter V4. Of these, the output signal of the NAND gate NA1, that is, the inverted internal signal MWE0B is commonly supplied to the non-inversion control terminal of the clocked inverter CV1 and the inversion control terminal of the clocked inverter CV2, and the inversion control terminal and the clock of the clocked inverter CV1 are commonly supplied. De-inverter CV2
An inverted signal of the inverted internal signal MWE0B from the inverter V3 is commonly supplied to the non-inverted control terminal of the. The output signal of the inverter V4 is supplied to the write amplifier WA as the non-inverted output signal IT of the write bus receiver WR.
Further, after being inverted by the inverter V5, the write amplifier W is provided as an inverted output signal IB of the write bus receiver WR.
Supplied to A. The bank selection signal BS0 is supplied to one input terminal of the NAND gate NA1, and the internal control signal MWE is supplied to the other input terminal.

As a result, the output of the NAND gate NA1, that is, the inverted internal signal MWE0B is selectively set to the low level when the internal control signal MWE is set to the high level and the corresponding bank selection signal BS0 is set to the high level.
Upon receiving the low level of the inverted internal signal MWE0B, the write bus receiver WR is selectively latched. At this time, the clocked inverter CV2 and the inverter V4 of the write bus receiver WR have the inverted internal signal MWE0.
When the low level of B is received, it is selectively latched and the clocked inverter CV1 is set to the non-transmission state. In addition, the write amplifier WA also outputs the inverted internal signal MWE0.
When it receives the low level of B, it is selectively activated. As a result, the write data transmitted via the internal data bus DBUS0 is first taken in by the latch circuit including the clocked inverter CV2 and the inverter V4, transmitted to the write amplifier WA, and then the write amplifier WA.
Is converted into a predetermined complementary write signal and written in the selected memory cell of the memory array MARY via the complementary common data line CD00 *.

Incidentally, the synchronous DR of this embodiment
The AM write mode is selectively started by inputting a write command at the rising edge of the clock signal CLK, as represented by cycles A and B in FIG. Needless to say, the write command is the chip selection signal CSB and the row address strobe signal RA.
The SB, the column address strobe signal CASB, the write enable signal WEB, and the like are selectively designated by a predetermined combination of activation control signals. At this time, the Y address signals AY0 to AYi are sequentially supplied to the address input terminals A0 to Ai in a combination designating the column addresses CAa and CAb, and the write data DIa and DIb are sequentially supplied to the data input / output terminals D0 to DF. Supplied. As described above, these write data are stored in the corresponding data input buffer IB of the data input / output circuit IO when the internal control signal DIE is set to the high level.
Are transmitted to the internal data buses DBUS0 to DBUSF when the internal control signal BRE is set to the high level. Further, when the internal control signal MWE is set to the high level and the corresponding bank selection signals BS0 to BS1 are set to the high level, it is taken into the write bus receiver WR of the main amplifier MA00 to MA0F or MA10 to MA1F. Then, after being made into a predetermined complementary write signal by the write amplifier WA, the complementary common data line C
D00 * to CD0F * or CD10 * to CD1F *
Is written to the selected 16 memory cells of the memory array MARY of the bank BANK0 or BANK1 via.

On the other hand, the synchronous DRAM of this embodiment
The read mode is selectively started by inputting a read command at the rising edge of the clock signal CLK, as represented by cycles C and D in FIG. At this time, the Y address signals AY0 to AYi are sequentially supplied again to the address input terminals A0 to Ai in a combination designating the column addresses CAa and CAb. As a result, the corresponding 16 memory cells are selected from the memory array MARY of the bank BANK0 or BANK1, and the read signals DOa and DOb thereof have complementary common data lines CD00 * to CD0F * or CD10.
Main amplifier MA00-MA0 via * -CD1F *
It is sequentially output to the read amplifier RA of F or MA10 to MA1F. These read signals are amplified by the corresponding read amplifier RA when the internal control signal MRA is set to the high level and the corresponding bank selection signals BS0 to BS1 are set to the high level, and then the internal control signal BRE is set to the high level. The internal data buses DBUS0 to DBUS0-D are set via the corresponding read bus driver RD when set to the level.
It is output to BUSF. Further, the high level of the internal control signal BRL is received and the data is input to the corresponding read bus receiver RR of the data input / output circuit IO, and the internal control signal DOE is set to the high level to input the data from the corresponding data output buffer OB. It is sent to the output terminals D0 to DF. The data output buffer OB of the data input / output circuit IO has a function of delaying the read data transmitted from the read bus receiver RR by the cycle corresponding to the specified latency. In the case of FIG. 6, the delay cycle due to the latency is provided. The number is 3.

As described above, the synchronous DRAM of this embodiment has a multi-bit structure of .times.16 bits, and data input / output terminals D0 to DF provided corresponding to each bit of input / output data, and these data. The data input / output circuit IO includes 16 data input buffers IB and data output buffers OB provided corresponding to the input / output terminals. Further, the synchronous DRAM has a pair of banks BA
NK0 and BANK1, and each of these banks includes 16 memory mats MM00 to MM0F or M including a memory array MARY and its direct peripheral circuits.
16 main amplifiers MA00 to M10 to MM1F each including a write amplifier WA and a read amplifier RA
MA0F and MA10-MA1F. The banks BANK0 and BANK1 are connected to the bank selection signal BS0.
~ BS1 is selectively activated according to the main amplifiers MA00-MA0F and MA10-MA
1F is selectively activated. Further, the output terminal of the data input buffer IB forming the data input / output circuit IO is
From the corresponding write bus driver WD to the internal data bus D
Corresponding main amplifier M via BUS0 to DBUSF
Coupled to the write bus receiver WR of A00 to MA0F and MA10 to MA1F, that is, the write amplifier WA,
Main amplifier MA00-MA0F and MA10-M
The output terminal of the read amplifier RA forming A1F is connected to the corresponding read bus driver RD to the internal data bus DBU.
It is coupled to the corresponding read bus receiver RR of the data input / output circuit IO, that is, the data output buffer OB via S0 to DBUSF.

In this embodiment, the internal data bus DB
US0 to DBUSF are all composed of a single signal line and are also used as a write internal data bus for transmitting write data and a read internal data bus for transmitting read data. In addition, internal data buses DBUS0 to DBU
A write signal and a read signal transmitted via SF are both signals of MOS level, and each bit of the internal data buses DBUS0 to DBUSF constitutes a bus latch circuit BL and a pair of cross-coupled CMOSs.
16 unit bus latch circuits UBL0 including inverters
~ UBLF are respectively coupled. Furthermore, Bank BA
Memory mat MM00 constituting NK0 and BANK1
.About.MM0F, MM10 to MM1F and main amplifiers MA00 to MA0F, MA10 to MA1F are arranged in the normal order so that the corresponding internal data buses DBUS0 to DBUSF have almost the same wiring length. Therefore, in this embodiment, the internal data buses DBUS0 to DBUSF are used.
The transmission delay time of each bit is set to a substantially constant value, and further, the signal level when the write bus driver WD and the read bus driver RD are set to the high impedance state can be determined to stabilize the operation of the synchronous DRAM. The predetermined number of internal data buses arranged over a relatively long distance on the chip surface is a quarter of that of a conventional synchronous DRAM in which a write internal data bus and a read internal data bus are individually prepared as complementary signal lines. Therefore, the required layout area can be significantly reduced. As a result, the chip size of the synchronous DRAM can be reduced and its cost can be reduced.

FIG. 8 shows a block diagram of an embodiment of a computer system to which the synchronous DRAM of FIG. 1 is applied. The outline and features of the application system of the synchronous DRAM of this embodiment will be described with reference to FIG.

In FIG. 8, the synchronous DRAM of this embodiment has a so-called stored program type central processing unit CPU as its basic constituent element. The central processing unit CPU is provided with a random access memory RA composed of an ordinary static RAM via a system bus SBUS.
M1 and random access memory RAM2, which is a synchronous DRAM to which the present invention is applied, are coupled.
The system bus SBUS is further coupled with a read-only memory ROM including a mask ROM and the like, a display control device DPYC and a peripheral device controller PERC. The display control device DPYC includes an image memory VRAM including a synchronous DRAM to which the present invention is applied. A display device DPY is connected to the display control device DPYC, and a keyboard KBD and an external storage device EXM are connected to the peripheral device controller PERC.

The central processing unit CPU performs step operations according to a control program stored in advance in the read-only memory ROM, and controls / controls each unit of the computer system. The random access memory RAM1 is used as, for example, a cache memory, and the random access memory RAM2 is, for example, a read-only memory R.
It is used as a buffer memory for temporarily storing and relaying control programs, operation data, etc. transmitted from the OM to the central processing unit CPU. Further, the display control device DPYC is used for display control of the display device DPY, and the peripheral device controller PERC controls the keyboard K.
It controls various peripheral devices such as the BD and the external storage device EXM. The computer system includes a power supply device POWS. The power supply device POWS forms a stable predetermined DC power supply voltage based on a predetermined AC input power supply voltage and supplies the DC power supply voltage to each unit of the computer system.

In this embodiment, the random access memory RAM2 and the synchronous DRAM which constitutes the image memory VRAM of the display controller DPYC are composed of a single signal line and have a write internal data bus and a read internal data bus as described above. It also has an internal data bus that is also used as the device, and the chip size can be reduced, that is, the cost can be reduced. As a result, the cost of the random access memory RAM2 and the image memory VRAM can be correspondingly reduced, and the cost of the computer system can be reduced accordingly.

The operational effects obtained by the above embodiment are as follows. That is, (1) a synchronous DRAM having a multi-bit configuration and having a pair of banks each made up of a plurality of memory mats.
Etc., the write internal data bus provided between the data input buffer and each write amplifier is also used as the read internal data bus provided between the read amplifier and each data output buffer, and these internal data buses are also used. All the single signal lines are used, and the bus driver and bus receiver are provided on the output terminal side of the data input buffer and read amplifier, and the input terminal side of the write amplifier and data output buffer, respectively. Compared with the conventional synchronous DRAM in which the data bus and the read internal data bus are individually prepared as complementary signal lines, the required layout area can be significantly reduced by a quarter.

(2) In the above item (1), the level of the write signal and the read signal transmitted by the internal data bus is set to the MOS level, and each bit of the internal data bus is cross-coupled with a CMOS inverter. Even if each bus driver is in a high-impedance state by coupling to one of the input / output nodes,
The effect that the signal level of the internal data bus can be determined is obtained. (3) In the above item (1), the plurality of memory mats constituting each bank and the write amplifier and the read amplifier are arranged in the forward order so that the wiring lengths of the corresponding internal data buses are substantially constant, so that the internal data bus is formed. It is possible to obtain the effect that the transmission delay time of each bit can be set to a substantially constant value. (4) According to the above items (1) to (3), the synchronous DRA adopts a multi-bit configuration while stabilizing its operation.
The effect that the chip size such as M can be reduced and the cost can be reduced can be obtained. (5) Synchronous DR according to the above (1) to (4)
By constructing the buffer memory and the image memory of the computer system by the AM, it is possible to obtain the effect that the operation of the buffer memory and the image memory can be stabilized and the cost of the buffer memory and the image memory and hence the computer system including the same can be reduced. .

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIGS. 1 and 2, the synchronous DRAM is
An arbitrary bit structure such as a × 8 bit structure or a × 32 bit structure can be adopted, and an arbitrary number of banks can be provided. In addition, internal data buses DBUS0 to DBUSF
As shown in FIG. 7, the write internal data bus DBUS is provided on the condition that they both consist of a single signal line.
W0-DBUSWF and read internal data bus DB
It can be separated as USR0 to DBUSRF for each purpose,
The data input / output terminals D0 to DF can also be separated as a data input terminal and a data output terminal according to use. The memory mats MM00 to MM0F and MM10 to MM1F can be further divided into a plurality of submats, and the synchronous D
Various embodiments can be adopted for the block configuration of the RAM, the names and combinations of the activation control signal and the internal control signal, the logic level thereof, and the like.

In FIG. 3, the chip layout of the synchronous DRAM is not restricted by this embodiment.
4, 5, and 7, main amplifiers MA00 to MA00
Various embodiments can be adopted for the specific configurations of MA0F and MA10-MA1F, their write bus receivers WR and read bus drivers RD, the polarity of the power supply voltage, the conductivity type of MOSFET, and the like. In FIG. 6, the combination of the start control signal and the internal control signal, the time relationship, etc. are not restricted by this embodiment. In FIG.
The block configuration of the computer system can adopt various embodiments, and the application range of the synchronous DRAM is not limited to this embodiment.

In the above description, the case where the invention made by the present inventor is mainly applied to the synchronous DRAM and the computer system to which the invention is applied, which is the background field of the invention, has been described, but the invention is not limited thereto. Instead, for example, it can be applied to various memory integrated circuits such as ordinary dynamic RAM and static RAM, and various digital systems including similar memory integrated circuits. The present invention can be widely applied to a semiconductor memory device including at least a plurality of internal data buses and devices and systems including such a semiconductor memory device.

[0047]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a synchronous DRAM or the like having a multi-bit configuration and having a pair of banks each made up of a plurality of memory mats, the write internal data bus provided between the data input buffer and the corresponding write amplifier corresponds to the read amplifier. It also serves as a read internal data bus provided between the data input buffer and the data output buffer, and these internal data buses are all single signal lines, and the output terminal side of the data input buffer and read amplifier and the write amplifier and data output buffer A bus driver and a bus receiver are provided on the input terminal side. Further, the levels of the write signal and the read signal transmitted by the internal data bus are set to the MOS level, and each bit of the internal data bus is connected to the input / output node of the bus latch circuit formed by cross-coupling CMOS inverters. Further, a plurality of memory mats constituting each bank, and write amplifiers and read amplifiers are arranged in the normal order so that the wiring length of the corresponding internal data bus is substantially constant. As a result, the transmission delay time of each bit of the internal data bus is set to a substantially constant value, and the signal level when both the bus drivers are in the high impedance state is fixed, while the predetermined number of internal data buses is reduced. The required layout area can be reduced. As a result,
It is possible to reduce the chip size of a synchronous DRAM or the like having a multi-bit configuration and reduce its cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronous DRAM to which the present invention is applied.

2 is a block diagram showing an embodiment of a bank BANK0 included in the synchronous DRAM of FIG.

FIG. 3 is a chip layout diagram showing an embodiment of the synchronous DRAM of FIG.

4 is a partial bus configuration diagram showing a first embodiment of an internal data bus of the synchronous DRAM of FIG. 1. FIG.

5 is a circuit diagram showing an embodiment of a bus driver and a bus receiver of a main amplifier MA00 coupled to the internal data bus of FIG.

FIG. 6 is a synchronous D having the internal data bus of FIG.
It is a signal waveform diagram which shows one Example of RAM.

7 is a partial bus configuration diagram showing a second embodiment of the internal data bus of the synchronous DRAM of FIG.

8 is a block diagram showing an embodiment of a computer system to which the synchronous DRAM of FIG. 1 is applied.

[Explanation of symbols]

BANK0-BANK1 ... Bank, MARY ...
Memory array, RD ... Row address decoder, SA
... Sense amplifier, CD ... Column address decoder, MA ... Main amplifier, RB ... Row address buffer, CB ... Column address buffer, BS ...
..Bank selection circuits, BL ... Bus latch circuits, IO
... Data input / output circuit, TG ... Timing generation circuit. CD00 to CD01, CD10 to CD11 ... Column address decoder, MM00 to MM0F, MM10
~ MM1F ... Memory mat, MARY0-MARY
F ... Memory array, RD0-RDF ... Row address decoder, SA0-SAF ... Sense amplifier, M
A00 to MA0F, MA10 to MA1F ... Main amplifier, DBUS0 to DBUSF ... Internal data bus.
SUB: Semiconductor substrate. WR ... write bus receiver, WA ... write amplifier, RA ... read amplifier, RD ... read bus driver, IB ... data input buffer, WD ... write bus driver, RR ...
.. Read bus receiver, OB ... Data output buffer, UBL0 to UBLF ... Unit bus latch circuit N
A1 to NA3 ... NAND gate, NO1
~ NO2 ... NOR gate, CV1 to CV2
... Clocked inverter, V1-V8 ... CMO
S inverter, P1 ... P-channel MOSFET,
N1 ... N-channel MOSFET. CPU ... Central processing unit, SBUS ... System bus, RAM1 ...
RAM2 ... Random access memory, ROM ...
Read-only memory, DPYC ... display control device, VRAM ... image memory, DPY ... display device, PERC ... peripheral device controller, KBD ... keyboard, EXM ... external storage device, POWS ... Power supply device.

Claims (3)

[Claims] 1. A plurality of memory mats that are selectively activated, and a write amplifier that is provided corresponding to each of the plurality of memory mats and that transmits a write signal to a selected memory cell of the corresponding memory mat. , A first bus receiver whose output terminal is coupled to an input terminal of the write amplifier, and a read signal of a selected memory cell of a corresponding memory mat provided corresponding to each of the plurality of memory mats And a first input amplifier whose input terminal is coupled to the output terminal of the read amplifier.
Bus driver, a data input buffer that substantially transfers write data input from the outside to the write amplifier, and a second bus driver whose input terminal is coupled to the output terminal of the data input buffer. Of the data output buffer, which outputs the read data output from the read amplifier to the outside, a second bus receiver whose output terminal is coupled to an input terminal of the data output buffer, and a first bus receiver. An internal data bus formed of a single signal line is provided between the input terminal and the output terminal of the first bus driver and the output terminal of the second bus driver and the input terminal of the second bus receiver. A semiconductor memory device comprising: 2. A signal transmitted through the internal data bus is set to a MOS level, and an input / output of a bus latch circuit in which a pair of CMOS inverters are cross-coupled to the internal data bus. The semiconductor memory device according to claim 1, wherein the nodes are coupled. 3. The semiconductor memory device comprises a pair of n-bit memory banks each of which includes n memory mats and a write amplifier and a read amplifier and is selectively activated. 2. The plurality of memory arrays forming the pair of banks, and the write amplifier and the read amplifier are arranged in the forward order so that the wiring length of the corresponding internal data bus is substantially constant. Alternatively, the semiconductor memory device according to claim 2.