JPH08180677A - Semiconductor device - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] Input clock signal C for synchronous DRAM, etc.
The timing margin for LK is expanded to prevent its malfunction. A clock input circuit IBCK included in a timing generation circuit TG such as a synchronous DRAM is a one-shot pulse which forms an internal pulse signal CLKS having a predetermined pulse width whose phase is inverted based on a substantial input clock signal CLK. The input latch circuit I of the latter stage is composed of a generating circuit, and the output signal of the generating circuit is the substantial internal clock signal CLKI.
It is supplied to LT1 to ILT4. As a result, when the signal width of the input clock is larger than the predetermined value, the internal clock signal is used as it is, and when it is short, the pulse width can be expanded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique which is particularly effective for use in a synchronous DRAM which operates synchronously in accordance with an input clock signal and a clock input circuit included in its timing generation circuit.

[0002]

2. Description of the Related Art There is a synchronous DRAM (dynamic type random access memory) which operates synchronously in accordance with a predetermined input clock signal supplied from the outside. The synchronous DRAM includes, for example, an input latch circuit that determines and holds a logic level of a chip selection signal or the like serving as a start control signal by using its high level period from the rising edge of the input clock signal, and based on the output signal thereof. A predetermined write operation or read operation is started. For this reason,
Detailed specifications are defined for the input clock signal, including its pulse width and time relationship with the start control signal, and the user of the synchronous DRAM must design the device to meet these specifications.

[0003]

However, as the speeding up of the device progresses and the demand for further speeding up of the cycle time of the synchronous DRAM increases, the conventional synchronous DRAM has the following problems. . That is, as described above, the conventional synchronous DRAM has an input latch circuit that determines and holds the logic level of the chip selection signal or the like to be the start control signal by utilizing the high level period from the rising edge of the input clock signal. However, especially when the pulse width of the input clock signal becomes shorter than a predetermined value due to noise or the like, the startup control signal etc. is not normally captured by the input latch circuit,
Synchronous DRAM malfunctions. This malfunction can be eliminated by satisfying the specifications of the input clock signal, but the burden on the user becomes heavy as the speed of the device and the synchronous DRAM increases significantly, and the usability of the synchronous DRAM decreases. It is a thing.

An object of the present invention is to provide a synchronous DRAM.
The purpose is to expand the timing margin for the input clock signal such as, and prevent its malfunction. Another object of the present invention is to relax the specifications of an input clock signal and the like for a user such as a synchronous DRAM,
It is to improve the usability of M etc.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, a clock input circuit included in a timing generation circuit such as a synchronous DRAM is provided with a one-shot pulse generation circuit that forms an internal pulse signal having a predetermined pulse width whose phase is inverted based on a substantial input clock signal. A first clocked inverter, which is brought into a transmission state selectively when the internal pulse signal is brought to a high level when receiving a substantially input clock signal, and its input terminal is coupled to an output terminal of the first clocked inverter. An inverter whose output signal is supplied as a substantial internal clock signal to the input latch circuit in the subsequent stage, and an inverter provided in the form of a latch with this inverter and selectively brought into a transmission state when the internal pulse signal is at a low level The second clocked inverter is basically used.

[0007]

According to the above means, when the pulse width of the input clock signal exceeds the predetermined value and is long, the input clock signal is directly used as the internal clock signal, and when the pulse width of the input clock signal is shorter than the predetermined value. It is possible to realize a clock input circuit capable of selectively adjusting and expanding the pulse width.
As a result, a synchronous DRA including a clock input circuit
It is possible to expand the timing margin for an input clock signal such as M, prevent its malfunction, relax the specifications of the input clock signal for the user, and improve the usability of the synchronous DRAM or the like.

[0008]

FIG. 1 is a block diagram showing an embodiment of a synchronous DRAM (semiconductor device) to which the present invention is applied. First, the outline of the configuration and operation of the synchronous DRAM of this embodiment will be described with reference to FIG.
The circuit elements forming each block in FIG. 1 are manufactured by a known CMOS (complementary MOS) integrated circuit manufacturing technique.
It is formed on one semiconductor substrate such as single crystal silicon.

In FIG. 1, the synchronous DRAM of this embodiment is not particularly limited, but a pair of banks BAN is used.
K0 and BANK1, each of these banks occupying most of the required layout area of the memory array MARY, and these memory arrays MAR.
It includes a row address decoder RD which is a direct peripheral circuit of Y, a sense amplifier SA and a column address decoder CD.

Here, the banks BANK0 and BANK1
Each of the memory arrays MARY constituting the memory cell array comprises a plurality of word lines arranged in the vertical direction in the figure, a plurality of sets of complementary bit lines arranged in the horizontal direction, and a grid pattern at intersections of these word lines and complementary bit lines. And a large number of dynamic memory cells arranged in.

The word lines forming the memory arrays MARY of the banks BANK0 and BANK1 are coupled to the corresponding row address decoders RD and are alternatively set to the selected state. The row address decoder RD of the banks BANK0 and BANK1 has a row address buffer RB.
I-bit internal address signal X excluding the most significant bit from
0 to Xi-1 are commonly supplied. Further, the internal control signal RG is commonly supplied from the timing generation circuit TG, and the corresponding bank selection signal BS0 or BS1 is respectively supplied from the bank selection circuit BS. The row address buffer RB is supplied with the X address signals AX0 to AXi in a time division manner through the address input terminals A0 to Ai, and the timing control circuit TG supplies the internal control signal RL.
The internal control signal RL is a row address strobe signal RASB at the rising edge of an internal clock signal CLKI (to be referred to as an inversion signal or the like which is selectively brought to a low level when it is enabled). The name is suffixed with B. The same applies hereinafter) is selectively formed by setting the low level, that is, the internal row address strobe signal RASI to the high level.

The row address buffer RB has an X address signal A input via address input terminals A0 to Ai.
X0 to AXi are fetched and held according to internal control signal RL, and internal address signals X0 to Xi are formed based on these X address signals. Of these, the most significant bit internal address signal Xi is supplied to the bank selection circuit BS, and the remaining i-bit internal address signals X0 to Xi.
-1 is commonly supplied to the row address decoders RD of the banks BANK0 and BANK1.

The bank selection circuit BS decodes the internal address signal Xi supplied from the row address buffer RB and selectively sets the corresponding bank selection signal BS0 or BS1 to the high level. Further, the row address decoder RD forming the banks BANK0 and BANK1 is selectively activated by setting the internal control signal RG to the high level and the corresponding bank selection signal BS0 or BS1 to the high level. Internal address signal X
0 to Xi-1 are decoded and the corresponding memory array M
The word line corresponding to ARY is alternatively set to the high level.

Next, the complementary bit lines forming the memory array MARY of the banks BANK0 and BANK1 are coupled to the corresponding sense amplifiers SA, and eight sets of the complementary common data lines IC0 are selectively selected via the respective sense amplifiers SA.
0 * to IC07 * or IC10 * to IC17 * (where, for example, the non-inverted common data line IC00T and the inverted common data line IC00B are combined together, the complementary common data line IC
It is expressed by adding * like 00 *. Further, a so-called non-inverted signal or the like which is selectively set to a high level when it is validated is indicated by adding T to the end of its name. The same shall apply hereinafter). A bit line selection signal of a predetermined bit is supplied from the corresponding column address decoder CD to the sense amplifier SA. Also, the timing generation circuit T
An internal control signal PA is commonly supplied from G, and
The corresponding bank selection signal BS0 from the bank selection circuit BS
Alternatively, BS1 is supplied respectively.

Here, the banks BANK0 and BANK1
Each of the sense amplifiers SA includes a predetermined number of unit circuits provided corresponding to each complementary bit line of the corresponding memory array MARY, and each of these unit circuits is
A unit amplifier circuit in which a pair of CMOS inverters are cross-coupled, and a pair of N-channel type switch MOSFETs
T (metal oxide semiconductor type field effect transistor. In this specification, MOSFET is referred to as a general term for an insulated gate field effect transistor).

In the unit amplifier circuit constituting each unit circuit of the sense amplifier SA, the internal control signal PA is set to the high level and the corresponding bank selection signal BS0 or BS1 is set to the high level to selectively and simultaneously. A small read signal output from a predetermined number of memory cells that are brought into an operating state and coupled to a selected word line of a corresponding memory array MARY via a corresponding complementary bit line is amplified to a high level or a low level. The binary read signal of In addition, the switch MOS that constitutes each unit circuit
The FETs are selectively turned on simultaneously by 8 pairs when the corresponding bit line selection signals are selectively set to the high level, and the corresponding 8 of the corresponding memory array MARY is turned on.
Complementary bit line and complementary common data line IC00 * to IC
07 * or IC10 * to IC17 * are selectively connected.

The column address buffer C is provided in the column address decoder CD of the banks BANK0 and BANK1.
Internal address signals Y0 to Yi of i + 1 bits are commonly supplied from B. Further, the internal control signal CG is commonly supplied from the timing generation circuit TG, and the bank selection circuit BS
From the corresponding bank selection signal BS0 or BS1. The column address buffer CB has Y address signals AY0 to AYi via address input terminals A0 to Ai.
Are supplied in a time division manner, and the internal control signal CL is supplied from the timing generation circuit TG. The internal control signal CL is a column address strobe signal CAS at a rising edge of an internal clock signal CLKI which will be described later.
It is selectively formed by setting B to low level, that is, the internal column address strobe signal CASI to high level.

The column address buffer CB fetches the Y address signals AY0 to AYi supplied via the address input terminals A0 to Ai in accordance with the internal control signal CL,
The bank BANK is formed by holding the internal address signals Y0 to Yi based on these Y address signals.
0 and BANK1 column address decoder CD. Further, the column address decoder CD of the banks BANK0 and BANK1 has the internal control signal CG set to the high level and the corresponding bank selection signal BS0 or BS1.
Is set to a high level to be selectively activated,
The internal address signals Y0 to Yi supplied from the column address buffer CB are decoded and the bit line selection signals are alternatively set to the high level.

Complementary common data lines IC00 * to IC07 * and IC10 * to IC in which eight designated sets of complementary bit lines of the memory array MARY are selectively connected.
17 * is coupled to the data input / output circuit IO. The data input / output circuit IO is supplied with bank selection signals BS0 and BS1 from the bank selection circuit BS and internal control signals WT and RD from the timing generation circuit TG.

The data input / output circuit IO includes complementary common data lines IC00 * to IC07 * and IC10 * to IC1.
It includes eight write amplifiers and eight main amplifiers provided corresponding to 7 *, a data input buffer and a data output buffer. Of these, the output terminals of the respective write amplifiers and the input terminals of the respective main amplifiers selectively correspond to the complementary common data lines IC00 * to IC07 * or IC10 * to I corresponding to the bank selection signals BS0 to BS1.
Connected to C17 * respectively. In addition, the input terminal of each write amplifier is coupled to the output terminal of the corresponding data input buffer, and the output terminal of each main amplifier is coupled to the input terminal of the corresponding data output buffer. The input terminal of each data input buffer and the output terminal of each data output buffer are commonly coupled to the corresponding data input / output terminals D0 to D7. The internal control signal WT is commonly supplied to the write amplifiers of the data input / output circuit IO, and the internal control signal RD is commonly supplied to the main amplifiers.

Each data input buffer of the data input / output circuit IO corresponds to the corresponding data input / output terminals D0 to D7 when the synchronous DRAM is selected in the write mode.
Take in the 8-bit input data supplied via
It is transmitted to the corresponding light amplifier. At this time, each write amplifier is selectively activated by receiving the high level of the internal control signal WT, and after the input data transmitted from the data input buffer is made into a predetermined complementary write signal, the corresponding complementary common data is sent. Write to the selected eight memory cells of the memory array MARY of the bank BANK0 or BANK1 via the lines IC00 * to IC07 * or IC10 * to IC17 *.

On the other hand, each main amplifier of the data input / output circuit IO is selectively operated by receiving the high level of the internal control signal RD when the synchronous DRAM is selected in the read mode, and the bank BANK0 is selected. Or BA
Complementary common data lines IC00 * to IC corresponding to the selected eight memory cells of the memory array MARY of NK1
The binary read signal output via 07 * or IC10 * to IC17 * is further amplified and transmitted to the corresponding data output buffer. These read data are output from the respective data output buffers to the outside of the synchronous DRAM via the corresponding data input / output terminals D0 to D7.

The timing generation circuit TG includes an input clock signal CLK and a clock enable signal CKE which are supplied from the outside and a chip selection signal CS which is a start control signal.
Based on B, the row address strobe signal RASB, the column address strobe signal CASB and the write enable signal WEB, the above various internal control signals are selectively formed and supplied to each part of the synchronous DRAM.

In this embodiment, the timing generation circuit TG includes a clock input circuit IBCK which receives an input clock signal CLK and a clock enable signal CKE to form an internal clock signal CLKI having a predetermined pulse width. Further, input latch circuits ILT1 to ILT4 are provided which selectively determine and capture the logic levels of the chip selection signal CSB, the row address strobe signal RASB, the column address strobe signal CASB and the write enable signal WEB using the internal clock signal CLKI as an input trigger. Further, a signal generating circuit for selectively forming various internal control signals in accordance with internal clock signal ICLK is provided. The specific configuration and operation of the timing generation circuit TG and its characteristics will be described later in detail.

FIG. 2 shows a partial circuit diagram of an embodiment of the timing generation circuit TG included in the synchronous DRAM of FIG. Further, FIG. 3 shows a clock input circuit IBCK included in the timing generation circuit TG of FIG.
FIG. 4 shows a signal waveform diagram of one embodiment when the pulse width of the input clock signal CLK is small, and FIG. 4 shows a signal waveform diagram of one embodiment when the pulse width of the input clock signal CLK is large. ing. Based on these figures, the specific configurations and operations of the timing generation circuit TG and the clock input circuit IBCK included in the synchronous DRAM of this embodiment and their characteristics will be described. In the following circuit diagrams, the MOSFET with an arrow added to its channel (back gate) portion is a P-channel type MOSFET, and is shown separately from the N-channel MOSFET without an arrow. Further, in FIGS. 2 to 4, the input latch circuits ILT1 to ILT1 to ILT1 are taken as a representative example.
Although a detailed description of the ILT4 will be made, the other input latch circuits ILT2 to ILT4 have the same configuration as that of the ILT4.

In FIG. 2, the timing generation circuit TG
Is a clock input circuit IBCK that receives an input clock signal CLK and a clock enable signal CKE to form a predetermined internal clock signal CLKI, and a chip selection signal CS using this internal clock signal CLKI as an input trigger.
B, a row address strobe signal RASB, a column address strobe signal CASB, and four input latch circuits ILT1 to ILT4 for determining and fetching the logic levels of the write enable signal WEB.

Of these, the clock input circuit IBCK is
It includes an inverter V1 that receives the input clock signal CLK supplied to the clock input terminal CLK at its input terminal via the protection resistor R1 and the protection MOSFET M1. The output signal of the inverter V1 is supplied to the input terminal of the clocked inverter CV1 (first clocked inverter) via the inverter V2, and the clocked inverter CV1.
The output terminal of 1 is coupled to the input terminal of inverter V3 (first inverter). The output signal of the inverter V3 is
The internal pulse signal CLKL is supplied to one input terminal of a NAND gate NA1 and also becomes an internal clock signal CLKI via the inverters V4 and V5 and is supplied to the input latch circuits ILT1 to ILT4. The inverter V3 has a clocked inverter CV2.
The (second clocked inverters) are provided in latch form to be cross-coupled to each other.

The other input terminal of the NAND gate NA1 is connected to the protection resistor R2 and the protection MOSF from the external terminal CKE.
The clock enable signal CKE is supplied via the ETM2 and the inverters V6 and V7. The output signal of the NAND gate NA1 becomes the internal pulse signal CLKE through the inverter V8, is supplied to one input terminal of the NAND gate NA2 that constitutes the one-shot pulse generation circuit, and also passes through the delay circuit including the inverters V9 to VB. It becomes the internal pulse signal CLKD and is supplied to the other input terminal of the NAND gate NA2. The output signal of the NAND gate NA2 is the internal pulse signal CLKS.
The (first internal pulse signal) is supplied to the non-inverting control terminal of the clocked inverter CV1 and the inverting control terminal of the clocked inverter CV2.
As a result, the clocked inverter CV1 is selectively turned on when the internal pulse signal CLKS is at a high level, and the clocked inverter CV2 is selectively turned on when the internal pulse signal CLKS is at a low level. To be in a state.

By the way, the internal pulse signal CLKE, which is a substantial output signal of the NAND gate NA1, has a clock enable signal CKE, as is apparent from FIGS.
Is set to the high level and the internal pulse signal CLKL is set to the high level, so that the signal is selectively set to the high level. The internal pulse signal CLKD, which is the output signal of the delay circuit including the inverters V9 to VB, is the internal pulse signal CL.
It is set to low level after a delay time t3 from the rising edge of KE, and is set to high level after a delay time t3 from the falling edge of the internal pulse signal CLKE. Further, the NAND gate NA2, that is, the internal pulse signal C which is the output signal of the one-shot pulse generation circuit.
The LKS is set to low level in response to the high level change of the internal pulse signal CLKE, and is set to high level in response to the low level change of the internal pulse signal CLKD. The internal pulse signal CLKL is formed in accordance with the substantial input clock signal CLK, as described later. As a result, the one-shot pulse generating circuit including the NAND gate NA2 and the inverters V9 to VB is phase-inverted based on the internal pulse signal CLKL, that is, the substantial input clock signal CLK, and has the first internal pulse width t3. It forms the pulse signal CLKS.

As described above, the internal pulse signal CLKS is supplied to the non-inversion control terminal of the clocked inverter CV1 and the inversion control terminal of the clocked inverter CV2. Therefore, the internal pulse signal C
LKS is set to high level and clocked inverter CV1
Is transmitted, the clocked inverter CV2
Is not transmitted. Therefore, the clock input terminal C
The high level of the input clock signal CLK supplied from the LK via the inverters V1 and V2 is directly transmitted via the clocked inverter CV1 and the inverter V3, and the internal pulse signal CLKL and the internal clock signal C are transmitted.
It becomes the high level of LKI. In addition, the internal pulse signal CL
The internal pulse signal CLKE is set to the high level in response to the high level of KL, and the internal pulse signal CLK is received in response to this.
S is set to low level. As a result, the clocked inverter CV1 is placed in the non-transmission state, but instead the clocked inverter CV2 is placed in the transmission state, and the inverter V
3 and 3 form a latch circuit to hold the high level of the input clock signal CLK immediately before.

Here, as illustrated in FIG. 3, when the effective pulse width of the input clock signal CLK, that is, its high level period is short as t2, the internal pulse signal CLKL and the internal clock signal CLKI become Since the high level immediately before the input clock signal CLK is held by the latch circuit including the inverter V3 and the clocked inverter CV2, it remains at the high level even after the input clock signal CLK is set to the low level. And
When the clocked inverter CV2 is brought into the non-transmitted state and the clocked inverter CV1 is brought into the transmitted state by the internal pulse signal CLKS being set to the high level, the low level of the input clock signal CLK is changed via the clocked inverter CV1 and the inverter V3. Since it is transmitted, it is returned to the low level. As a result, the input clock signal CLK
Even if the pulse width is smaller than a predetermined value, that is, the pulse width t3 of the internal pulse signal CLKS, a substantially constant pulse width t3.
It becomes possible to secure the internal clock signal CLKI having

On the other hand, as shown in FIG. 4, when the effective pulse width of the input clock signal CLK is as long as t5, the internal pulse signal CLKS temporarily becomes low level while the input clock signal CLK is high level. And is returned to the high level. Therefore, the internal pulse signal CLKS
Is returned to the high level, the input clock signal CLK is still at the high level, and the internal pulse signal CLKL and the internal clock signal CLKI maintain the high level of the input clock signal CLK. Then, when the time corresponding to the pulse width t5 elapses and the input clock signal CLK becomes low level, the internal pulse signal CLKL becomes low level and the internal clock signal CLKI also becomes low level.
As a result, when the pulse width of the input clock signal CLK is longer than a predetermined value, that is, substantially longer than the pulse width t3 of the internal pulse signal CLKS, the pulse width of the input clock signal CLK becomes the pulse width of the internal clock signal CLKI as it is.

As a result of the above, the clock input circuit IBCK
When the pulse width of the input clock signal CLK exceeds a predetermined value and is long, the input clock signal CLK is directly used as the internal clock signal CLKI, and when the pulse width of the input clock signal CLK is shorter than the predetermined value, the The pulse width can be adjusted and expanded.

Next, the input latch circuits ILT1 to ILT4 of the timing generation circuit TG are input latch circuits ILT of FIG.
As represented by LT1, the inverters VC to V
It also includes a one-shot pulse generation circuit formed of E and a NAND gate NA3 to form an internal pulse signal CLKT having a predetermined pulse width, the phase of which is inverted based on the internal clock signal CLKI. Hereinafter, this input latch circuit IL
Taking T1 as an example, a detailed description will be given of the input latch circuits ILT1 to ILT4.

The input latch circuit ILT1 further includes an inverter VF which receives the chip selection signal CSB supplied to the external terminal CSB at its input terminal via the protection resistor R3 and the protection MOSFET M3. The output signal of the inverter VF is supplied to the input terminal of the clocked inverter CV3 via the inverter VG, and the output terminal of the clocked inverter CV3 is coupled to the input terminal of the inverter VH. The output signal of the inverter VH is the inverter VI.
And VJ, and is supplied to the subsequent circuit as an internal chip selection signal CSI. The clocked inverter CV4 is provided in the inverter VH in a latch form so as to be cross-coupled. The non-inverting control terminal of the clocked inverter CV3 and the inverting control terminal of the clocked inverter CV4 are connected to the inverters VC to VE and the NAND gate NA.
The output signal of the one-shot pulse generating circuit consisting of 3 (that is, the internal pulse signal CLKT) is supplied.

From these facts, the clocked inverter CV3 is selectively brought into the transmission state when the internal pulse signal CLKT is set to the high level. The clocked inverter CV4 is selectively brought into a transmission state when the internal pulse signal CLKT is at a low level, and constitutes a latch circuit together with the inverter VH. Therefore, the chip selection signal CSB input via the external terminal CSB
3 and 4, the logic level of the internal clock signal CLKI, that is, the input clock signal CLK is determined at the rising edge of the input clock signal CLK, and the logical level is taken into the latch circuit including the inverter VH and the clocked inverter CV4. In response to this, the internal chip selection signal C
The effective logical level of SI is determined.

Similarly, the row address strobe signal RASB input from the external terminal RASB via the protection resistor R4 and the protection MOSFET M4 has the logical level at the rising edge of the internal clock signal CLKI, that is, the rising edge of the input clock signal CLK. It is determined and taken into the input latch circuit ILT2 and becomes the internal row address strobe signal RASI. Also, the external terminal C
A column address strobe signal CASB input from the ASB via the protection resistor R5 and the protection MOSFET M5.
Is determined at the rising edge of the internal clock signal CLKI to be taken into the input latch circuit ILT3, and the internal column address strobe signal CASI
Becomes Further, the write enable signal WEB input from the external terminal WEB via the protection resistor R6 and the protection MOSFET M6 has its logical level determined at the rising edge of the internal clock signal CLKI, and is taken into the input latch circuit ILT4 to enable internal write enable. Signal W
It becomes EI.

On the other hand, in a subsequent circuit (not shown) of the timing generation circuit TG, a synchronous circuit is produced according to the logic levels of the internal chip select signal CSI, the internal row address strobe signal RASI, the internal column address strobe signal CASI and the internal write enable signal WEI. DRAM
The operation mode of is determined. Further, the internal control signals RL and CL which are the trigger signals of the row address buffer RB and the column address buffer CB are selectively formed, and various internal controls for advancing the operation of each part of the synchronous DRAM in a predetermined sequence. The signal is selectively formed. As a result, the operation of the synchronous DRAM becomes synchronized with the input clock signal CLK, that is, its rising edge, and the input latch circuit I
The stability and high speed of the operation are influenced by the attributes of the internal clock signal CLKI, which is a substantial trigger signal of the LT1 to ILT4, the row address buffer RB, the column address buffer CB, etc., that is, the cycle and pulse width. .

In this embodiment, the internal clock signal C
As described above, the clock input circuit IBCK of the timing generation circuit TG forming the LKI has the input clock signal C
When the pulse width of LK exceeds the predetermined value and is long, the input clock signal CLK is directly used as the internal clock signal CLKI, and when the pulse width of the input clock signal CLK is shorter than the predetermined value, the pulse width is selectively adjusted. Expand to a specified value. As a result, for some reason, the input clock signal C
Synchronous DRAM even if the pulse width of LK becomes short
Since the timing margin for the input clock signal CLK can be expanded and its malfunction can be prevented, the specifications of the input clock signal for the user can be relaxed, and the synchronous D
The usability of RAM and the like can be improved.

The operational effects obtained by the above embodiment are as follows. That is, (1) One-shot pulse generation for forming an internal pulse signal having a predetermined pulse width whose phase is inverted based on a substantial input clock signal by a clock input circuit included in a timing generation circuit such as a synchronous DRAM. A circuit, a first clocked inverter that receives a substantial input clock signal and is selectively brought into a transmission state when the internal pulse signal is at a high level, and its input terminal is an output of the first clocked inverter An inverter coupled to the terminal and having its output signal supplied as a substantial internal clock signal to the input latch circuit of the subsequent stage, and an inverter provided in a latch form with this inverter and selectively transmitting state when the internal pulse signal is at a low level The second clocked inverter, which is assumed to be When it is longer than the value, the input clock signal is used as it is as the internal clock signal, and when it is shorter than the predetermined value, it is possible to realize a clock input circuit capable of selectively adjusting and expanding the pulse width. To be

(2) According to the above item (1), it is possible to expand the timing margin for the input clock signal of the synchronous DRAM including the clock input circuit and prevent the malfunction. (3) According to the above items (1) and (2), it is possible to relax the specifications of the input clock signal and the like for the user of the synchronous DRAM and the like, thereby improving the usability of the synchronous DRAM and the like. .

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the synchronous DRAM can have an arbitrary bit configuration such as a so-called x4 bit configuration or a 16-bit configuration, and can have an arbitrary number of banks. Further, the banks BANK0 and BANK1 can be divided into an arbitrary number of memory mats, and the combination with the direct peripheral circuit can adopt various embodiments. Complementary common data lines IC00 * to IC07 * and IC10 * to I
The C17 * can be separated for writing and reading, and the data input / output terminals D0 to D7 can also be separated for usage as data input terminals and data output terminals. Further, the block configuration of the synchronous DRAM, the names and combinations of the activation control signal and the internal control signal, the logic level, etc. are not restricted by this embodiment.

In FIG. 2, the synchronous DRAM is
It is not always necessary to provide the clock enable signal CKE. In this case, for example, the output signal of the inverter V2 may be directly supplied to one input terminal of the inverter V9 and the NAND gate NA2 as an internal pulse signal instead of the internal pulse signal CLKE. Clock input circuit IBC
Specific configuration of K and input latch circuits ILT1 to ILT4, polarity and absolute value of power supply voltage, and MOSFET
Various conductivity types and the like can be adopted. In FIGS. 3 and 4, the time relationship, the logic level, etc. of the input clock signal, the internal clock signal, the internal pulse signal, etc.
It can be set arbitrarily. Further, in the above embodiment, when the pulse width of the input clock signal CLK is shorter than the predetermined value, the pulse width is selectively compensated and expanded.
When the pulse width of the input clock signal CLK easily fluctuates in the direction of exceeding a predetermined value, its inverted signal may be input to a clock input circuit similar to that of the above-described embodiment to adjust the pulse width. It is also possible to form an internal clock signal adjusted to an intermediate pulse width by combining the internal clock signal output from the above and the internal clock signal CLKI output from the clock input circuit IBCK of the above embodiment.

In the above description, the invention mainly made by the present inventor is applied to the synchronous DRAM and its clock input circuit, which are the fields of application in the background, but the invention is not limited thereto. For example, the present invention can be applied to a single clock input circuit, a memory integrated circuit including a similar clock input circuit, and various digital systems including such a memory integrated circuit. The present invention can be widely applied to a semiconductor device including at least a clock input circuit and a system including such a semiconductor device.

[0045]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a clock input circuit included in a timing generation circuit such as a synchronous DRAM is provided with a one-shot pulse generation circuit that forms an internal pulse signal having a predetermined pulse width whose phase is inverted based on a substantial input clock signal. A first clocked inverter, which is brought into a transmission state selectively when the internal pulse signal is brought to a high level when receiving a substantially input clock signal, and its input terminal is coupled to an output terminal of the first clocked inverter. An inverter whose output signal is supplied as a substantial internal clock signal to an input latch circuit or the like in the subsequent stage, and an inverter provided in the form of a latch with this inverter and selectively brought into a transmission state when the internal pulse signal is at a low level With the second clocked inverter as a basic configuration, the pulse width of the input clock signal has a predetermined value. Therefore, it is possible to realize a clock input circuit in which the input clock signal is used as it is as an internal clock signal when it is long, and when the pulse width of the input clock signal is shorter than a predetermined value, the pulse width can be selectively corrected and expanded. . As a result, a timing margin for an input clock signal of a synchronous DRAM or the like including a clock input circuit can be expanded, its malfunction can be prevented, and specifications of the input clock signal or the like for a user can be relaxed to improve usability of the synchronous DRAM or the like. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronous DRAM to which the present invention is applied.

2 is a partial circuit diagram showing an embodiment of a timing generation circuit included in the synchronous DRAM of FIG.

FIG. 3 is a signal waveform diagram showing an embodiment when the pulse width of the input clock signal of the clock input circuit included in the timing generation circuit of FIG. 2 is small.

4 is a signal waveform diagram showing an embodiment when the pulse width of the input clock signal of the clock input circuit included in the timing generation circuit of FIG. 2 is large.

[Explanation of symbols]

BANK0-BANK1 ... Bank, MARY ...
Memory array, RD ... Row address decoder, BS
... Bank selection circuit, RB ... Row address buffer, SA ... Sense amplifier, CD ... Column address decoder, CB ... Column address buffer, IO
... Data input / output circuit, TG ... Timing generation circuit. IBCK ... Clock input circuit, ILT1 to IL
T4 ... Input latch circuit, R1 to R6 ... Protection resistance, M1 to M6 ... Protection MOSFET, V1 to VJ
..Inverters, CV1 to CV4 ... Clocked inverters, NA1 to NA3 ... NAND gates.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shoji Wada 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hiritsu Cho-LS Engineering Co., Ltd.

Claims (3)

[Claims] 1. A clock input terminal to which an input clock signal is supplied, and an internal clock signal formed based on the input clock signal, and selectively when an effective pulse width of the input clock signal is less than a predetermined value. A semiconductor device, comprising: a clock input circuit that adjusts a pulse width of an internal clock signal. 2. A one-shot pulse generating circuit for forming a first internal pulse signal having a predetermined pulse width, the phase of which is inverted based on the input clock signal, and the input terminal thereof. And a first clocked inverter that is brought into a transmission state selectively when the first internal pulse signal is set to a high level, and its input terminal is the first clocked inverter. An inverter coupled to the output terminal of the inverter, the output signal of which is substantially the internal clock signal; and a transmission state which is provided in the form of a latch with the inverter and is selectively transmitted when the first internal pulse signal is at a low level. 2. The semiconductor device according to claim 1, further comprising a second clocked inverter that is formed. 3. The semiconductor device is a synchronous DRAM that operates synchronously in accordance with the input clock signal, and the clock input circuit is the synchronous DRA.
3. The semiconductor device according to claim 1, which is included in the M timing generation circuit.