JPH09167773A - Bump manufacturing method and bonding method - Google Patents
Bump manufacturing method and bonding methodInfo
- Publication number
- JPH09167773A JPH09167773A JP7327044A JP32704495A JPH09167773A JP H09167773 A JPH09167773 A JP H09167773A JP 7327044 A JP7327044 A JP 7327044A JP 32704495 A JP32704495 A JP 32704495A JP H09167773 A JPH09167773 A JP H09167773A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- bumps
- metal
- metal layer
- melting point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 56
- 229910052751 metal Inorganic materials 0.000 claims abstract description 56
- 238000002844 melting Methods 0.000 claims abstract description 25
- 230000008018 melting Effects 0.000 claims abstract description 24
- 238000005304 joining Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000002245 particle Substances 0.000 claims 1
- 230000004907 flux Effects 0.000 abstract description 17
- 239000000758 substrate Substances 0.000 abstract description 10
- 239000010953 base metal Substances 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 description 11
- 239000000956 alloy Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000003870 refractory metal Substances 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000001017 electron-beam sputter deposition Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】
【課題】 バンプの製造方法と接合方法に関し、フラッ
クスを用いずにフリップチップ接合を可能とする。
【解決手段】 素子と素子、あるいは素子と基板をフリ
ップチップ接合するに際して、少なくとも一方の素子１
に設けるバンプの製造方法は、前記素子１に設けた下地
金属層２の上に低融点金属からなるバンプ４を設け、前
記バンプ４の上に高融点金属からなる金属層５を被せ、
前記バンプ４を溶融温度を制御しながら加熱し、前記金
属層５を前記バンプの表面に粒状に散在させるようにバ
ンプの製造方法を構成し、前記バンプを他方の素子の対
向バンプ、あるいは対向する基板の上のパッドに押圧し
て前記金属層５によってバンプ表面の酸化膜を突き破
り、加熱するように接合方法を構成する。
(57) Abstract: A bump manufacturing method and a bonding method enable flip-chip bonding without using flux. At least one element (1) when flip-chip bonding the elements to each other or the elements to the substrate
In the method of manufacturing the bumps, the bumps 4 made of a low melting point metal are provided on the base metal layer 2 provided on the element 1, and the bumps 4 are covered with the metal layer 5 made of a high melting point metal.
The bump manufacturing method is configured such that the bumps 4 are heated while controlling the melting temperature, and the metal layers 5 are dispersed in a granular manner on the surfaces of the bumps, and the bumps are opposed bumps of the other element or opposed to each other. The bonding method is configured such that the metal layer 5 is pressed against the pad on the substrate to break through the oxide film on the surface of the bump and heated.
Description
【０００１】[0001]
【発明の属する技術分野】本発明はバンプの製造方法と
接合方法に係わり、高集積され高精度化された素子や回
路基板をフラックス無しで接合できるバンプの製造方法
と接合方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bump manufacturing method and a bonding method, and more particularly to a bump manufacturing method and a bonding method capable of bonding highly integrated and highly accurate devices and circuit boards without flux.
【０００２】[0002]
【従来の技術】図３は従来のフリップチップ接合法の模
式的な説明図である。図３（Ａ）において、半導体素子
が設けられたチップ同士のフリップチップ接合、例え
ば、信号処理回路などが形成された半導体素子30と化合
物半導体からなる赤外線検出素子31をフリップチップ接
合する赤外線検出装置のような場合には、半導体素子30
の第一の下地金属層32の上に設けられた第一のバンプ33
と、赤外線検出素子31の第二の下地金属層34の上に設け
られた第二のバンプ35とを加圧溶融して接合する。2. Description of the Related Art FIG. 3 is a schematic explanatory view of a conventional flip chip bonding method. In FIG. 3 (A), an infrared detecting device for flip-chip joining chips provided with semiconductor elements, for example, flip-chip joining a semiconductor element 30 having a signal processing circuit and the like with an infrared detecting element 31 made of a compound semiconductor. In such cases, the semiconductor element 30
The first bump 33 provided on the first underlying metal layer 32 of
And the second bump 35 provided on the second underlying metal layer 34 of the infrared detection element 31 are pressure-melted and bonded.
【０００３】また、図３（Ｂ）において、例えば、セラ
ミックプリント板などの基板36の上に半導体素子30がフ
リップチップ接合される場合には、基板36の上に下地電
極37が設けられている。そして、半導体素子30の第一の
下地金属層32の上に設けられた第一のバンプ33を、下地
電極37に加圧溶融して接合する。In FIG. 3B, when the semiconductor element 30 is flip-chip bonded onto a substrate 36 such as a ceramic printed board, a base electrode 37 is provided on the substrate 36. . Then, the first bumps 33 provided on the first base metal layer 32 of the semiconductor element 30 are pressure-melted and bonded to the base electrode 37.
【０００４】つまり、一般に、フリップチップ接合を行
うに際して、素子同士を接合する場合には、両者にバン
プが設けられており、基板に素子を接合する場合には、
素子の方にバンプが設けられる。That is, generally, when performing flip-chip bonding, bumps are provided on both elements when they are bonded to each other, and when bonding elements to a substrate,
Bumps are provided on the element side.
【０００５】このようなフリップチップ接合では、バン
プ同士、あるいはバンプと下地電極との接合の信頼性を
維持するために、比較的高融点の金属をバンプとして用
いる場合には、例えば、ＡｇバンプにＰｄを被覆するよ
うに、バンプの上にバンプ金属と合金や共晶を形成する
金属を被覆したり、ＡｕバンプにＩｎを含む金属を介在
させたりする提案がなされている。In such flip-chip bonding, when a metal having a relatively high melting point is used as the bump in order to maintain the reliability of the bonding between the bumps or between the bump and the base electrode, for example, an Ag bump is used. It has been proposed to coat the bump metal with a metal that forms an alloy or eutectic with the bump metal so as to coat Pd, or to interpose a metal containing In in the Au bump.
【０００６】[0006]
【発明が解決しようとする課題】しかし、素子の温度が
余り上げられないために、例えば、低融点金属のＩｎを
バンプ金属として用いる場合には、バンプ頭部の接合面
にＩｎの酸化膜が生成してフリップチップ接合における
密着性が低下してしまう。こうした酸化膜の除去には通
常フラックスが用いられる。ところが、バンプのピッチ
が細かくなるとフラックス処理が困難となり、バンプ間
の短絡の原因となったりする。However, since the temperature of the element cannot be raised too much, for example, when In, which is a low melting point metal, is used as the bump metal, an In oxide film is formed on the bonding surface of the bump head. Adhesion during flip chip bonding is reduced. A flux is usually used to remove such an oxide film. However, if the pitch of the bumps becomes fine, it becomes difficult to carry out the flux treatment, which may cause a short circuit between the bumps.
【０００７】そこで本発明は、低融点金属のバンプを用
いたフリップチップ接合に際して、フラックスを用いず
に安定した接合が可能なバンプの製造方法と接合方法を
提供することを目的としている。Therefore, an object of the present invention is to provide a bump manufacturing method and a bonding method capable of performing stable bonding without using flux in flip-chip bonding using a low melting point metal bump.
【０００８】[0008]
【課題を解決するための手段】上で述べた課題は、請求
項１および２において、金属下地層の上に低融点金属か
らなるバンプを設け、前記バンプの上に高融点金属から
なる金属層を被せ、前記バンプを溶融温度を制御しなが
ら加熱し、前記金属層を前記バンプの表面に粒状に散在
させるバンプの製造方法によって解決される。According to the first and second aspects of the present invention, a bump made of a low melting point metal is provided on a metal underlayer, and a metal layer made of a high melting point metal is provided on the bump. It is solved by a method of manufacturing a bump in which the metal layer is dispersed in a granular shape on the surface of the bump by heating the bump while controlling the melting temperature.
【０００９】また、請求項３において、低融点金属から
なるバンプの表面に、粒状に散在する高融点金属からな
る金属層を設け、前記バンプを対向するバンプまたはパ
ッドに押圧して前記金属層によってバンプ表面の酸化膜
を突き破り、加熱して接合方法によって解決される。According to a third aspect of the present invention, a metal layer made of a high melting point metal dispersed in a granular form is provided on the surface of the bump made of a low melting point metal, and the bump is pressed against the opposing bump or pad by the metal layer. The oxide film on the bump surface is broken through and heated to solve the problem by the bonding method.
【００１０】つまり、Ｉｎのような低融点金属からなる
バンプは表面に酸化膜が形成し易いので、通常はフラッ
クスを用いて除去しているが、本発明においては、少な
くとも一方のバンプの表面にＰｄのような高融点金属か
らなる金属層を被せるようにしている。そして、加熱温
度を制御して金属層を薄片皿状を経て粒状に散在させる
ようにしている。That is, since an oxide film is easily formed on the surface of a bump made of a low melting point metal such as In, it is usually removed by using a flux, but in the present invention, at least one of the bumps has a surface. A metal layer made of a refractory metal such as Pd is covered. Then, the heating temperature is controlled so that the metal layer is scattered in a granular shape through a thin plate-like shape.
【００１１】バンプの表面に粒状に散在した金属層は低
融点金属のバンプよりも硬い。そこで、接合に際して、
少なくとも一方の、粒状に散在した金属層を有する低融
点バンプと対向バンプ、あるいはバンプと基板のパッド
をそれぞれ衝合して押圧すると、粒状の金属層が、自ら
のバンプや対向バンプの表面に形成されている酸化膜を
突き破って接合される。そのあと加熱するとＩｎ−Ｐｄ
の合金が形成され、安定したフリップチップ接合が達成
できる。The metal layer dispersed in a granular form on the surface of the bump is harder than the bump of the low melting point metal. So, when joining,
When at least one of the low-melting point bumps and the opposing bumps having the metal layer scattered in a granular form is abutted against and pressed against the bump and the substrate pad, the granular metal layer is formed on the surface of the bump or the opposing bump. It breaks through the oxide film that is formed and is joined. Then, when heated, In-Pd
The alloy is formed, and stable flip chip bonding can be achieved.
【００１２】こうして本発明になるバンプによれば、フ
ラックスを用いずに、酸化膜によって覆われたバンプを
よるフリップチップ接合を行うことができる。Thus, according to the bump of the present invention, flip chip bonding can be performed by using the bump covered with the oxide film without using flux.
【００１３】[0013]
【発明の実施の形態】図１は本発明になるバンプの製造
方法の模式的工程図、図２は本発明になるフリップチッ
プ接合方法の模式的説明図である。図において、１は素
子、２は下地金属層、3aは第１のレジスト膜、3bは第２
のレジスト膜、４はバンプ、4aはＩｎ膜、５は金属膜、
5aはＰｄ膜、６はフラックス、７は対向素子、８は対向
バンプ、９は基板、10はパッドである。1 is a schematic process diagram of a bump manufacturing method according to the present invention, and FIG. 2 is a schematic explanatory diagram of a flip chip bonding method according to the present invention. In the figure, 1 is an element, 2 is a base metal layer, 3a is a first resist film, and 3b is a second
Resist film, 4 bumps, 4a In film, 5 metal film,
5a is a Pd film, 6 is a flux, 7 is an opposing element, 8 is an opposing bump, 9 is a substrate, and 10 is a pad.
【００１４】図１（Ａ）において、例えば、半導体ＩＣ
などが設けられた素子１の上には、Ａｌ−Ｓｉ配線の上
にＴｉ／Ｐｄの多層膜からなる下地金属層２が設けられ
ている。この素子１の全面に例えば膜厚10〜15μｍのレ
ジストを塗布して第１のレジスト膜3aを形成し、下地金
属層２が露出するようにパターニングする。第１のレジ
スト膜3aには、リフトオフ用としてポジティブレジスト
を用いるとよい。In FIG. 1A, for example, a semiconductor IC
The underlying metal layer 2 made of a Ti / Pd multilayer film is provided on the Al-Si wiring on the element 1 provided with the above. A resist having a film thickness of 10 to 15 μm, for example, is applied to the entire surface of the element 1 to form a first resist film 3a, and patterning is performed so that the underlying metal layer 2 is exposed. A positive resist may be used for the first resist film 3a for lift-off.
【００１５】次いで、図２（Ｂ）において、素子１の全
面にＩｎ膜4aを例えば10〜15μｍの膜厚になるように蒸
着する。次いで、素子１を有機溶剤に浸漬し、リフトオ
フ法によって第１のレジスト膜3aと共に該第１のレジス
ト膜3a上に被着したＩｎ膜4aを剥離すると、図１（Ｃ）
に示したように、下地金属層２上に残ったＩｎ膜4aがバ
ンプ４となる。Then, in FIG. 2B, an In film 4a is vapor-deposited on the entire surface of the device 1 so as to have a film thickness of, for example, 10 to 15 μm. Then, the element 1 is immersed in an organic solvent, and the In film 4a deposited on the first resist film 3a together with the first resist film 3a is peeled off by a lift-off method.
As shown in, the In film 4a remaining on the underlying metal layer 2 becomes the bump 4.
【００１６】次いで、図１（Ｄ）において、バンプ４が
形成された素子１の全面にレジストを塗布して第２のレ
ジスト膜3bを形成し、バンプ４が露出するようにパター
ニングする。第２のレジスト膜3bも第１のレジスト膜3a
と同様、リフトオフ用としてポジティブレジストを用い
るとよい。そして、バンプ４を形成するＩｎに比べて融
点が高い金属、例えばＰｄを 0.5μｍ以下の膜厚になる
ように電子ビーム蒸着とかスパッタリングによって被着
しＰｄ膜5aを形成する。そして、素子１を有機溶剤に浸
漬し、リフトオフ法によって第２のレジスト膜3bと共に
該第２のレジスト膜3b上に被着したＰｄ膜5aを剥離する
と、図１（Ｅ）に示したように、バンプ４の上に残った
Ｐｄ膜5aが金属膜５となる。Ｐｄ膜5aの被着は、図１
（Ｂ）に示したＩｎ膜4aを被着したあと引き続いて行う
こともできる。Next, in FIG. 1D, a resist is applied to the entire surface of the element 1 having the bumps 4 formed thereon to form a second resist film 3b, and patterning is performed so that the bumps 4 are exposed. The second resist film 3b is also the first resist film 3a.
Similarly to, it is preferable to use a positive resist for lift-off. Then, a metal having a melting point higher than that of In forming the bump 4 such as Pd is deposited by electron beam evaporation or sputtering to a film thickness of 0.5 μm or less to form a Pd film 5a. Then, the element 1 is dipped in an organic solvent, and the Pd film 5a deposited on the second resist film 3b together with the second resist film 3b is peeled off by a lift-off method. As shown in FIG. The Pd film 5a remaining on the bump 4 becomes the metal film 5. The deposition of the Pd film 5a is shown in FIG.
It is also possible to continue after depositing the In film 4a shown in (B).
【００１７】次いで、図１（Ｆ）において、素子１の全
面にフラックス６を例えば回転塗布法によって30μｍの
膜厚に塗布する。こゝで用いるフラックス６には、素子
１の上にはバンプ４が突出しているので、例えば15Ｐの
高粘度のフラックスを用いるとよい。そして、バンプ４
を構成するＩｎの融点近傍まで加熱する。Next, in FIG. 1 (F), the flux 6 is applied to the entire surface of the element 1 to a film thickness of 30 μm by, for example, a spin coating method. Since the bumps 4 project above the element 1, the flux 6 used here is preferably a highly viscous flux of 15P, for example. And bump 4
Is heated to near the melting point of In.
【００１８】先ず、Ｉｎの融点 156.6°Ｃ近傍の例えば
160°Ｃに加熱すると、Ｉｎが溶融してバンプ４が伏せ
た半円球状になると共に、図１（Ｇ）に示したように金
属膜５が薄片皿状になり、さらに、 180°Ｃまで温度を
上げると図１（Ｈ）に示したように金属膜５が粒状に散
在した状態となる。こうして、表面に粒状の高融点金属
が散在する本発明になるバンプ４が形成できる。First, a melting point of In near 156.6 ° C., for example,
When heated to 160 ° C, In melts and the bumps 4 lie flat, forming a semi-spherical shape, and the metal film 5 becomes a thin plate shape as shown in Fig. 1 (G). When the temperature is raised, the metal films 5 are scattered in a granular form as shown in FIG. In this way, the bumps 4 according to the present invention in which granular refractory metals are scattered on the surface can be formed.
【００１９】こうして形成したバンプ４によってフリッ
プチップ接合を行うに際して、図２（Ａ）はバンプ同士
のフリップチップ接合を示している。つまり、一方の素
子１のバンプ４は、粒状の金属膜５を有しており、他方
の対向素子７には対向バンプ８が形成されている。この
場合には、まず、両バンプ４、８同士を衝合して素子
１、７を押圧すると、粒状の金属膜５が自身のバンプ４
と衝合する対向バンプ８とに食い込み、バンプ４、８の
表面に自然酸化によって形成された図示してないＩｎ2
Ｏ3 のような酸化膜が突き破られる。そのあと、不活性
ガス雰囲気中で、Ｉｎのバンプ４、８が十分に融解する
温度、例えば 200°Ｃで10分間加熱すると、Ｉｎ−Ｐｄ
の合金が形成され、フラックスを用いずに安定したフリ
ップチップ接合ができる。When performing the flip-chip bonding by the bumps 4 thus formed, FIG. 2A shows the flip-chip bonding between the bumps. That is, the bump 4 of the one element 1 has the granular metal film 5, and the counter bump 8 is formed on the other counter element 7. In this case, first, when the bumps 4 and 8 are abutted against each other and the elements 1 and 7 are pressed, the granular metal film 5 causes the bumps 4 of its own.
In 2 ( not shown) formed by natural oxidation on the surfaces of the bumps 4 and 8 by digging into the opposing bumps 8 that collide with
An oxide film such as O 3 is broken through. After that, when the bumps 4 and 8 of In are sufficiently melted in an inert gas atmosphere, for example, at 200 ° C. for 10 minutes, In-Pd
The alloy of is formed, and stable flip chip bonding can be performed without using flux.
【００２０】図２（Ｂ）に示したように、一方が、例え
ば、半導体ＩＣが形成された素子１で、バンプ４には粒
状の金属膜５を有し、他方が、例えば、セラミックプリ
ント板のような基板９であり、このようなバンプ−基板
間のフリップチップ接合の場合には、基板９に、例え
ば、Ｃｕ／Ｎｉ／Ａｕのようなパッド10が設ける。そし
て、このパッド10にバンプ４を衝合して押圧すると、粒
状の金属膜５が自身のバンプ４の表面に自然酸化によっ
て形成されている図示してない酸化膜を破壊する。その
あと、不活性ガス雰囲気中で、Ｉｎのバンプ４が十分に
融解する温度、例えば 200°Ｃで10分間加熱すると、バ
ンプ４とパッド10の間でＩｎ−Ｐｄ−Ａｕの合金化が起
こり、フラックスを用いなくても安定した確実なフリッ
プチップ接合ができる。As shown in FIG. 2B, one side is, for example, the element 1 having a semiconductor IC formed thereon, the bumps 4 have a granular metal film 5, and the other side is, for example, a ceramic printed board. In the case of such flip-chip bonding between the bump and the substrate, the substrate 9 is provided with a pad 10 such as Cu / Ni / Au. When the bump 4 is pressed against the pad 10, the granular metal film 5 destroys the oxide film (not shown) formed on the surface of the bump 4 by natural oxidation. After that, when heated at a temperature at which the In bump 4 is sufficiently melted, for example, 200 ° C. for 10 minutes in an inert gas atmosphere, In—Pd—Au alloying occurs between the bump 4 and the pad 10, Stable and reliable flip chip bonding can be performed without using flux.
【００２１】こゝでは、バンプに低融点金属のＩｎを例
示したが、これは素子が化合物半導体からなる赤外線セ
ンサの場合に、フリップチップ接合に際して、高い温度
に加熱することを嫌ったからである。また、金属層を形
成する高融点金属にＰｄを例示したが、ＴｉやＭｏなど
も用いることができる。Here, In is used as the low melting point metal for the bump. This is because when the element is an infrared sensor made of a compound semiconductor, heating at a high temperature during flip chip bonding is disliked. Further, although Pd is exemplified as the refractory metal forming the metal layer, Ti, Mo or the like can also be used.
【００２２】[0022]
【発明の効果】本発明によれば、Ｉｎのような低融点で
酸化し易いバンプによるフリップチップ接合に対して、
バンプのピッチが細かくなってフラックス処理が厄介な
場合でも、フラックスを用いずに安定した接合を得るこ
とができる。According to the present invention, flip chip bonding using bumps such as In having a low melting point and easily oxidized,
Even if the pitch of the bumps becomes fine and the flux treatment is troublesome, stable joining can be obtained without using flux.
【００２３】その結果、例えば、化合物半導体から形成
された赤外線センサを制御回路が設けられた半導体チッ
プと直にフリップチップ接合する工程のように、バンプ
が低融点金属で形成され、バンプのピッチが細かくてフ
ラックス処理が難しく、高温度の加熱処理も避けたい素
子のフリップチップ接合の実現に対して、本発明は寄与
するところが大である。As a result, the bumps are formed of a low melting point metal and the pitch of the bumps is changed, for example, in the process of directly flip-chip joining an infrared sensor formed of a compound semiconductor to a semiconductor chip provided with a control circuit. The present invention largely contributes to the realization of flip-chip bonding of elements that are fine and difficult to perform flux processing and that do not require heat treatment at high temperature.
【図１】 本発明になるバンプの製造方法の模式的工程
図である。FIG. 1 is a schematic process diagram of a bump manufacturing method according to the present invention.
【図２】 本発明になるフリップチップ接合方法の模式
的説明図である。FIG. 2 is a schematic explanatory view of a flip chip bonding method according to the present invention.
【図３】 従来のフリップチップ接合法の模式的な説明
図である。FIG. 3 is a schematic explanatory view of a conventional flip chip bonding method.
１ 素子 ２ 下地金属層 3a 第１のレジスト膜 3b 第２のレジス
ト膜 ４ バンプ 4a Ｉｎ膜 ５ 金属膜 5a Ｐｄ膜 ６ フラックス ７ 対向素子 ８ 対向バンプ ９ 基板 10 パッド1 Element 2 Base Metal Layer 3a First Resist Film 3b Second Resist Film 4 Bump 4a In Film 5 Metal Film 5a Pd Film 6 Flux 7 Opposing Element 8 Opposing Bump 9 Substrate 10 Pad
Claims (3)
ンプを設け、 前記バンプの上に高融点金属からなる金属層を被せ、 前記バンプを溶融温度を制御しながら加熱し、前記金属
層を前記バンプの表面に粒状に散在させることを特徴と
するバンプの製造方法。1. A bump made of a low melting point metal is provided on a metal underlayer, a metal layer made of a high melting point metal is covered on the bump, and the bump is heated while controlling a melting temperature. A method for manufacturing a bump, characterized in that the particles are scattered on the surface of the bump in a granular form.
がＰｄからなる請求項１記載のバンプの製造方法。2. The method of manufacturing a bump according to claim 1, wherein the bump is made of In and the metal layer is made of Pd.
状に散在する高融点金属からなる金属層を設け、 前記バンプを対向するバンプまたはパッドに押圧して前
記金属層によってバンプ表面の酸化膜を突き破り、加熱
することを特徴とする接合方法。3. A bump formed of a low melting point metal is provided with a metal layer made of a high melting point metal dispersed in a granular form, and the bump is pressed against an opposing bump or pad to form an oxide film on the bump surface by the metal layer. A joining method characterized by breaking through and heating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32704495A JP3419183B2 (en) | 1995-12-15 | 1995-12-15 | Bump manufacturing method and bonding method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32704495A JP3419183B2 (en) | 1995-12-15 | 1995-12-15 | Bump manufacturing method and bonding method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09167773A true JPH09167773A (en) | 1997-06-24 |
| JP3419183B2 JP3419183B2 (en) | 2003-06-23 |
Family
ID=18194689
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32704495A Expired - Fee Related JP3419183B2 (en) | 1995-12-15 | 1995-12-15 | Bump manufacturing method and bonding method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3419183B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007173637A (en) * | 2005-12-22 | 2007-07-05 | Matsushita Electric Works Ltd | Sensor module |
-
1995
- 1995-12-15 JP JP32704495A patent/JP3419183B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007173637A (en) * | 2005-12-22 | 2007-07-05 | Matsushita Electric Works Ltd | Sensor module |
| JP4715503B2 (en) * | 2005-12-22 | 2011-07-06 | パナソニック電工株式会社 | Manufacturing method of sensor module |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3419183B2 (en) | 2003-06-23 |
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