JPH09129873A - Buried gate structure mos transistor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an MOS transistor which is similar to SOI structure and has a merit of the SOI(silicon on insulator) structure, and a manufacturing method of it. SOLUTION: This buried structure MOS transistor consists of the following: a plurality of buried insulating regions 21 buried in a semiconductor substrate, a gate electrode 31 and a gate insulating film 22 which are so buried in a region sandwiched between these buried insulating regions that channels are formed perpendicularly to the surface of the substrate, and an upper layer impurity diffusion layer 11 and a lower layer impurity diffusion layer 12 which are formed on the substrate as a source region and a drain region, respectively. Thus a vertical structure is constituted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor in which a gate electrode is embedded in a substrate and a channel is formed in a direction perpendicular to the substrate, and a method for manufacturing the same.

[0002]

2. Description of the Related Art In the structure of a conventional MOS transistor, as shown in FIG. 3A, a gate electrode 31 is formed on a surface of a semiconductor substrate 10 with a gate insulating film 21 interposed therebetween, and a source / drain region 11 is formed on the substrate. , 12 are formed.

Compared with such a MOS transistor, an SOI (Silicon on) transistor is formed in a semiconductor region 10 provided on an insulating layer as shown in FIG. 3B.
Due to its structure, the MOS transistor of the Insulator structure has the features that the parasitic (stray) capacitance can be reduced, that it has low power consumption, high speed, is resistant to radiation, and latch-up does not occur.

When forming an SOI structure, it is difficult to form single crystal such as silicon on the insulating layer.
Therefore, conventionally, a method has been adopted in which the insulating layer 20 is formed by ion-implanting oxygen into a silicon substrate, or a silicon substrate having an insulating region formed on one surface is bonded to another silicon substrate.

However, the ion implantation method has a problem that it is difficult to separate elements having an arbitrary shape. In addition, the method of laminating requires a manufacturing process that has not been used in the past and has a problem that the cost is high. The present invention has been made in view of the above circumstances.
An object of the present invention is to provide a MOS transistor having a structure similar to that of the SOI structure and a manufacturing method thereof.

[0006]

In order to achieve the above object, the present invention provides the following buried gate structure MOS transistor and its manufacturing method. (1) A plurality of buried insulating regions buried in a semiconductor substrate, and a gate electrode buried in a region sandwiched by these buried insulating regions so that a channel is formed in a direction perpendicular to the surface of the substrate. And a gate insulating film and an upper impurity diffusion layer and a lower impurity diffusion layer formed on a substrate as source / drain regions, respectively, embedded gate structure MOS transistor. (2) The buried gate structure MOS transistor according to the above (1), wherein the distance between the gate insulating film and the buried insulating region is set to a distance required for forming a channel. (3) A step of forming source / drain regions by introducing an upper impurity diffusion layer and a lower impurity diffusion layer into the semiconductor substrate, and a step of embedding a plurality of buried insulating regions for element isolation in the semiconductor substrate. And a step of forming a hole for a gate electrode, a step of forming a gate insulating film on the inner wall of the hole, and a step of filling the hole with a conductive material. Manufacturing method. (4) The method for manufacturing a buried structure MOS transistor according to the above (3), wherein when forming the buried insulating region, an insulating hole is formed in the semiconductor substrate, and ions are implanted obliquely into the insulating hole. (5) The method of manufacturing a buried structure MOS transistor according to the above (3), in which a hole for a gate electrode is formed and then ions are obliquely injected into the hole.

The MOS transistor of the present invention is formed in a region sandwiched between embedded insulating regions embedded in a substrate, a gate electrode is embedded in the substrate, and a channel is formed in a direction perpendicular to the substrate surface. It is a type structure. For this reason,
The gate insulating film that insulates the gate electrode from the substrate and the buried insulating region can be made as close as possible, and the so-called floating region can be made as narrow as possible, so a structure similar to the SOI structure Can be

Therefore, the advantages of the SOI structure, that is, the parasitic (stray) capacitance can be reduced, the power consumption is high, the speed is high, and the radiation resistance is high. High integration is possible. In the process of manufacturing such a MOS transistor, after forming a hole when forming a buried insulating region for element isolation or when forming a gate electrode,
By performing oblique ion implantation into this hole, impurities can be introduced in the direction perpendicular to the region between the gate insulating film and the buried insulating region, and the threshold voltage can be adjusted.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below. 1A to 1E are sectional views showing an example of a buried gate structure MOS transistor of the present invention.

The embedded MOS transistor 1 of FIG. 1 (a)
Has a surface impurity diffusion layer 11 as a source region and a lower impurity diffusion layer 12 as a drain region formed on a semiconductor substrate 10. A buried insulating region for element isolation is formed so as to divide these diffusion layers. 21 is formed in a direction perpendicular to the substrate. In addition, these buried insulating regions 21
In the region between the gate electrode 31 and the surface impurity diffusion layer 1
1 to connect the lower impurity diffusion layer 12 to the substrate 1.
The gate electrode 31 is covered with a gate insulating film 22 which is formed in contact with one embedded insulating region 21 in the direction perpendicular to 0 and further insulates the gate electrode 31 from the substrate 10.

In this case, the source 11 and the drain 12 can be replaced with each other. Further, in the N-type transistor, as shown in FIG. 1C, N-type impurity diffusion layers 11N and 12N are formed on the P-type substrate 10P as source / drain regions, respectively.
As shown in (d), the P-type impurity diffusion layers 11P and 12P are respectively formed as the source / drain regions in the N-type substrate 10N.
Formed.

The embedded gate structure MOS transistor 1
The channel region of the gate insulating film 22 and the buried insulating region 2 is
It is formed in the region between 1 and is perpendicular to the substrate surface. Since the channel is formed in the region near the buried insulating region, the buried gate structure MOS transistor 1 of the present invention is provided.
Has a structure similar to the SOI structure. Therefore, FIG.
The gate insulating film 22 and the buried insulating region 2 as shown in FIG.
The distance L from 1 can be narrowed to a distance required for depleting the channel region. Therefore, parasitic (stray) capacitance can be reduced, low power consumption,
The feature of the SOI structure that it is high speed and resistant to radiation can be given. In order to realize this, the distance L between the gate insulating film 22 and the buried insulating region 21 is set to 0.
About 1 μm or less is suitable.

This embedded gate structure MOS transistor is
Since the channel is in the vertical direction, when the planar MOS transistor becomes finer and the channel length becomes shorter,
While problems such as the hot electron effect and punch through occur, it is possible to miniaturize while maintaining the optimum channel length. Therefore, the gate length is 0.35 to 0.5.
It is preferable that the thickness be about μm.

In the above example, the gate electrode 31 is in contact with one of the buried insulating regions 21, but the present invention is not limited to this. For example, as shown in FIG. 1E, the gate electrode 31 is buried with the buried insulating region 21. It is also possible to provide a structure in which a channel is formed on both side surfaces of the gate electrode 31 provided in the center portion between them.

A method of manufacturing such a buried gate electrode structure MOS transistor will be described with reference to FIG. First, as shown in FIG. 2A, a surface impurity diffusion layer 11 serving as a source (drain) and a lower impurity diffusion layer 12 serving as a drain (source) are formed on the substrate 10 by an ion implantation process or the like. In this case, the surface impurity diffusion layer 11 and the lower impurity diffusion layer 12 are 1.0 × 10 ^{20 to} 1.0.
Ion implantation is performed so that the ^pressure becomes × 10 ²² cm ^-3 .

Next, as shown in FIG. 2B, the first hole 1H for the buried insulating region is formed by a method such as etching in the vertical direction so as to divide the impurity diffusion layers 11 and 12. Form. This etching is performed, for example, by RIE.
By using (Reactive Ion Etching) or a wafer having a (100) surface as a surface, holes in the vertical direction can be formed by chemical etching. These first
The interval for forming the holes is determined in consideration of the interval L as shown in FIG.

Then, oblique ion implantation is performed on the wall surface of the first hole 1H on the transistor formation side. As a result, impurities can be introduced below the channel region to prevent punch through and the like. This step can be omitted in some cases. After that, as shown in FIG. 2D, the first hole 1H is filled with an insulating material by a method such as deposition to form a buried insulating region 21. The source / drain impurity diffusion layers 11 and 12 may be formed after the buried insulating region 21 is formed.

Next, as shown in FIG. 2E, the second hole 2H for the gate electrode is formed at a position where it contacts the buried insulating layer 21 and at a depth such that it contacts the lower diffusion layer region 12. Formed by etching. In this case, the width of the hole is determined in consideration of the distance from the buried insulating region.

Then, as shown in FIG. 2F, oblique ion implantation is performed on the side wall of the second hole where the channel is formed. As a result, an impurity diffusion layer can be formed in the channel formation region and the threshold voltage can be adjusted. This ion implantation step can also be omitted and may be performed after the gate oxide film is formed in the next step.

After that, as shown in FIG. 2G, a gate oxide film 22 is formed on the inner surface of the second hole 2H by, for example, an oxidation process. Finally, the second hole 2H having the oxide film 22 formed on the inner surface is filled with an electrode material by a method such as deposition to form a gate electrode 31, thereby obtaining the embedded gate electrode structure MOS transistor 1 shown in FIG. be able to.

[0021]

The buried electrode structure MOS transistor of the present invention consumes less power, can operate at higher speed, and can be downsized. Further, according to the method of manufacturing a buried structure MOS transistor of the present invention, such a MOS transistor can be reliably obtained.

[Brief description of the drawings]

1A to 1E are embedded electrode structures MO of the present invention.
FIG. 3 is a cross-sectional view showing an example of an S transistor.

2A to 2H are embedded electrode structures MO of the present invention.
It is a flow chart which shows an example of the manufacturing process of an S transistor.

FIG. 3 is a sectional view showing an example of a structure of a conventional MOS transistor.

[Explanation of symbols]

1 Embedded Electrode Structure MOS Transistor 1H First Hole 2H Second Hole 10 Substrate 11 Source 12 Drain 21 Embedded Insulation Region 22 Gate Insulation Film 31 Gate Electrode

[Procedure amendment]

[Submission date] January 31, 1996

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] Fig. 1

[Correction method] Change

[Correction contents]

FIG.

Claims (5)

[Claims] 1. A plurality of embedded insulating regions embedded in a semiconductor substrate, and a region sandwiched between these embedded insulating regions so that channels are embedded in a direction perpendicular to the surface of the substrate. A buried gate structure MOS transistor comprising a gate electrode and a gate insulating film, and an upper impurity diffusion layer and a lower impurity diffusion layer formed on a substrate as source / drain regions, respectively. 2. A buried gate structure MOS transistor according to claim 1, wherein a distance between the gate insulating film and the buried insulating region is set to a distance required for forming a channel. 3. A step of forming source / drain regions by introducing an upper impurity diffusion layer and a lower impurity diffusion layer into a semiconductor substrate, and a plurality of buried insulating regions for element isolation in the semiconductor substrate. A buried gate structure comprising: a step of filling, a step of forming a hole for a gate electrode, a step of forming a gate insulating film on the inner wall of the hole, and a step of filling the hole with a conductive material. Manufacturing method of MOS transistor. 4. The method of manufacturing a buried structure MOS transistor according to claim 3, wherein an insulating hole is formed in the semiconductor substrate when the buried insulating region is formed, and ions are obliquely implanted into the insulating hole. 5. The method of manufacturing a buried structure MOS transistor according to claim 3, wherein after forming a hole for the gate electrode, ions are obliquely implanted into the hole.