JPH088365B2 - Field effect transistor array - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor array.

[0002]

2. Description of the Related Art Recently, studies have been made on the use of a field effect transistor (FET) using amorphous silicon as a switching element provided for each pixel of a liquid crystal matrix display panel. This type of liquid crystal matrix panel has a full-surface electrode on one substrate, a matrix electrode is formed on the other substrate, and an FET is provided at each intersection.
It has a structure in which a display electrode to be a pixel is formed by connecting to T, and a liquid crystal is filled in a gap between these two substrates. The amorphous silicon FET has advantages such as being able to be formed uniformly on a large transparent substrate and having a large on / off current ratio, and is suitable as a switching element for this type of panel. However, amorphous silicon FE
When a large number of Ts are arranged in a matrix on a transparent glass substrate, between the source / drain electrode and the gate electrode, and
There is a risk of leakage at the intersection of the row and column electrodes. That is, conventionally, silicon oxide SiO ₂ or silicon nitride Si ₃ N ₄ has been used as an insulating layer interposed between the source / drain electrode and the gate electrode. By homogenizing the film quality and increasing the film thickness, Efforts have been made to form an insulating layer that does not suffer from the aforementioned drawbacks. However, when silicon nitride is applied as a film at a temperature of about 350 ° C. or higher, a hard one can be produced, but it has a drawback that cracks easily occur. Silicon oxide can also be formed by a thermal CVD method at a temperature of about 500 ° C. or lower, a sputtering method, or a plasma CVD method, but even if the film thickness is increased to about 6000Å, there is a drawback that a leak still occurs.

When such an amorphous FET is used in a liquid crystal matrix panel and designed with 200 gate lines and 250 drain lines, the number of gate-drain intersections is 50,000. If a leak occurs in one of the FETs, a defect will occur in 449 (200 + 249) FETs. This leak phenomenon is caused by dust in the air, pinholes in the insulating layer, or erosion of amorphous silicon by an etching solution. However, even if measures are taken to eliminate the above-mentioned cause, many leaks still occur if the film quality of the insulating layer is poor. To create an FET array of amorphous silicon on a glass substrate,
Only heat treatment at about 500 ° C. or lower is possible, and there is a limit to strengthening silicon oxide or silicon nitride by heat treatment, and a complete insulating layer cannot be obtained.

[0004]

SUMMARY OF THE INVENTION The present invention has been made to solve such a drawback, and suppresses a leak between a source / gate electrode, a drain / gate electrode, and a row / column electrode of a transistor. The present invention provides a field effect transistor array.

[0005]

A field effect transistor array according to the present invention has an insulating substrate, a plurality of row electrodes formed in parallel on the surface of the insulating substrate, and field effect transistors formed by connecting to the row electrodes. A gate electrode formed in a region, an insulating layer formed to cover the row electrode and the gate electrode, a semiconductor layer formed in at least a region on the insulating layer where a field effect transistor is formed, and a semiconductor layer formed on the semiconductor layer. A source electrode and a drain electrode formed on
A column electrode connected to the drain electrode is provided, and the semiconductor layer is interposed between the source / gate electrodes, between the drain / gate electrodes, and between the row / column electrodes, and at least between the electrodes, both electrodes are provided. Completely covers the overlap area.

[0006]

According to the field-effect transistor array of the present invention, the amorphous silicon layer is formed so as to completely include at least the overlapping regions of the source and gate electrodes, between the drain and gate electrodes, and between the row and column electrodes. Since it is formed, two layers of insulating films, which are the normal insulating film and this amorphous silicon layer added, always exist between the two electrodes.

[0007]

EXAMPLES Examples will be described below with reference to the drawings. 1 and 2, (1) is a transparent substrate such as a glass plate,
(G) is a gate electrode selectively deposited on the FET formation region on the surface of the transparent substrate (1) and is connected to the row electrode (X). These gate electrode (G) and row electrode (X)
Is formed by vapor deposition or sputtering of ITO (Indium Tin Oxide). (2) S _i formed on the substrate (1) surface to cover the gate electrode (G) and row electrodes (X)
O ₂ film, about 25 by thermal CVD or plasma CVD
Filmed under heating at 0-300 ° C. The S _i O ₂ film (2)
The film thickness of is set within the range of about 1000 to 5000Å.
This is for the following reasons. That is, the S _i O ₂ film (2), made for example, as thin as about 500Å about the unstable characteristics of the FET, also the dark current at the OFF time ^10-9
-8 A (However, when the gate voltage is 30 V and the drain voltage is 0 V)
And the variation of the obtained current is 10 ^-8 to 10 ^-5 A
It is very unstable. From the viewpoint of stabilizing the characteristics, 10
It is desirable to set the film thickness to about 00Å. On the other hand, the thicker the film thickness, the smaller the leakage current, but the thicker the film, the higher the drive voltage,
Since the threshold voltage becomes high and the current does not easily flow, the upper limit of the film thickness is preferably about 5000Å.

[0008] (AS) is a SiO ₂ film (2) amorphous silicon layer which is deposited in the strip over the FET forming region on the amorphous silicon by SiO ₂ film (2) over the entire surface to a plasma CVD method to be After wearing, it is formed into a predetermined pattern by etching. This amorphous silicon layer (AS) completely covers the gate electrode (G) and has a shape extending from the gate electrode (G) to the left and right (FIG. 2). (S) and (D) are amorphous silicon layers (A
On S), the source / drain electrodes provided at a predetermined interval directly above the gate electrode (G),
It is formed by sputtering Al or the like. A part of the column electrode (Y) is also used as the drain electrode (D).

Therefore, as is apparent from the plan view of FIG. 1, the overlapping region of the gate electrode (G) and the source / drain electrodes (S) (D) is completely covered by the amorphous silicon layer (AS). Will be done.

Incidentally, (3) is a display electrode made of an ITO film, which is in contact with the source electrode (S).

With this structure, the amorphous silicon layer (AS) extends between the source / drain electrodes (S) (D) and the gate electrode (G), and the SiO ₂ film (2) is formed.
Since the two layers are formed, leakage between the source / drain electrodes (S) (D) and the gate electrode (G) is prevented. Further, the amorphous silicon layer (AS) is formed at the intersections of the row / column electrodes (X) and (Y) as shown in FIG.
Since it completely intervenes in at least the overlapping portion of both the upper and lower electrodes, current leakage between them is similarly blocked.

In the above embodiment, a single layer of SiO ₂ film is used as the insulating film, but instead of this, _two layers of SiO ₂ film and Si ₃ N ₄ film are used.
A layered structure can also be used. In this case, the SiO ₂ film has a thickness of about 1000 to 2000Å, and the Si ₃ N ₄ film has a thickness of about 1
It is set to 000 to 3000Å.

[0013]

As is apparent from the above description, the field-effect transistor array of the present invention has, in the electrode overlap region between the source and drain electrodes and the gate electrode,
Since the amorphous silicon layer extends completely without any space and forms a multilayer insulating film in addition to the normal insulating film, leakage between the source / drain electrode and the gate electrode is prevented. Further, since the amorphous silicon layer completely exists at the intersection of the row and column electrodes, at least in the overlapping portion of both electrodes, current leakage between them is also blocked. In addition, since the band-shaped semiconductor film is formed under the column electrodes, the column electrodes are less likely to be disconnected due to a step, and even if there is a defect in the insulating film, the gate electrode is disconnected during the processing of the semiconductor film. Has the advantage that it decreases.

[Brief description of drawings]

FIG. 1 is a plan view of an embodiment of a field effect transistor array of the present invention,

2 is a cross-sectional view taken along the line I-I 'of the device of the present invention in FIG.

[Explanation of symbols]

1 transparent substrate G gate electrode X row electrode 2 SiO ₂ film AS amorphous silicon layer S source electrode D drain electrode Y column electrode 3 display electrode

Claims (1)

[Claims] 1. An insulating substrate, a plurality of row electrodes formed in parallel on the surface of the insulating substrate, a gate electrode connected to the row electrode in a region where a field effect transistor is formed, the row electrode and a gate. An insulating layer formed to cover the electrode, a semiconductor layer formed on at least a region where a field effect transistor is formed on the insulating layer, a source electrode and a drain electrode formed on the semiconductor layer, and a drain electrode A continuous column electrode is provided, and the semiconductor layer is present between the source / gate electrodes, between the drain / gate electrodes, and between the row / column electrodes, and at least between the electrodes completely includes the overlapping region of both electrodes, A field effect transistor array characterized by being formed in a strip shape under the column electrodes.