JPH04348076A - Field-effect transistor array - Google Patents

Abstract

PURPOSE:To restrain a leak between a source electrode and a gate electrode, between a drain electrode and the gate electrode and between matrix electrode by a method wherein an amorphous silicon layer is formed so as to completely wrap the superposed region of at least both electrodes out of the source and gate electrodes, the darin and gate electrodes and the matrix electrodes. CONSTITUTION:Amorphous silicon is applied, by a plasma CVD method, to the whole surface of an SiO2 film 2 so as to cover an FET formation region on the SiO2 film 2; after that, an amorphous silicon layer AS is formed to be a prescribed pattern by an etching operation. The amorphous silicon layer AS is stretched between a source electrode and a drain electrode S, D and a gate electrode G; it constitutes two layers together with the SiO2 film. As a result, a leak is stopped between the source and drain electrodes S, D and the gate electrode G. The amorphous silicon layer AS is situated completely at least in the superposed part of both upper and lower electrodes even at the intersection of matrix electrodes X, Y. As a result, a current leak between them is suppressed in the same manner.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to field effect transistor arrays.

0002

2. Description of the Related Art Recently, research has been carried out on the use of field effect transistors (FETs) using amorphous silicon as switching elements provided for each pixel of a liquid crystal matrix display panel. This type of liquid crystal matrix panel has full-surface electrodes on one substrate, row and column electrodes are formed on the other substrate, and FETs are provided at each intersection.
It has a structure in which a display electrode that becomes a pixel is connected to the
The gap between these two substrates is filled with liquid crystal. Amorphous silicon FETs have advantages such as being able to be uniformly formed on a large transparent substrate and having a high on/off current ratio, and are suitable as switching elements for this type of panel. However, when a large number of amorphous silicon FETs are arranged in a matrix on a transparent glass substrate, there are
There is a risk of leakage occurring at the intersection of the column electrodes. That is, conventionally, silicon oxide SiO2 or silicon nitride Si3N4 has been used as an insulating layer interposed between the source/drain electrode and the gate electrode, and by making the film quality uniform and increasing the film thickness, the above-mentioned drawbacks can be solved. Efforts have been made to form insulating layers that do not cause However, if silicon nitride is formed into a film at a temperature of about 350° C. or higher, a hard film can be produced, but it has the drawback of being susceptible to cracking. Silicon oxide can also be deposited as a film by thermal CVD, sputtering, or plasma CVD at temperatures below about 500° C., but it has the disadvantage that leakage still occurs even if the film is thickened to about 6000 Å.

If such an amorphous FET is used in a liquid crystal matrix panel and designed with 200 gate lines and 250 drain lines, there will be 50,000 gate-drain intersections. Of these, one FE
If a leak occurs in T, 449 (200+24
9) will result in a defect in the FET. This leakage phenomenon is caused by dust in the air, pinholes in the insulating layer, or erosion of amorphous silicon by an etching solution. However, even if measures are taken to eliminate the above-mentioned causes, many leaks still occur if the quality of the insulating layer is poor. To create an amorphous silicon FET array on a glass substrate, heat treatment at temperatures below approximately 500°C is required, and there are limits to strengthening silicon oxide and silicon nitride through heat treatment, making it impossible to form a complete insulating layer. cannot be obtained.

0004

[Problems to be Solved by the Invention] The present invention has been made to eliminate these drawbacks, and suppresses leakage between the source and gate electrodes, between the drain and gate electrodes, and between the row and column electrodes of a transistor. The present invention provides a field effect transistor array.

[0005]

[Means for Solving the Problems] The field effect transistor array of the present invention comprises an insulating substrate, a large number of row electrodes formed in parallel on the surface of the insulating substrate, and field effect transistors connected to the row electrodes. an insulating layer formed covering the row electrode and the gate electrode; a semiconductor layer formed on this insulating layer in at least a region where a field effect transistor is formed; a source electrode and a drain electrode formed on the
The semiconductor layer is provided with a column electrode connected to the drain electrode, and the semiconductor layer is arranged between the source and gate electrodes, between the drain electrode and the drain electrode.
It is interposed between gate electrodes and between row and column electrodes, and completely encompasses at least the overlapping region of both electrodes between each electrode.

[0006]

[Operation] According to the field effect transistor array of the present invention, the amorphous silicon layer is formed between the source and gate electrodes, between the drain and gate electrodes, and between the row and column electrodes so as to completely cover at least the overlapping region of both electrodes. Therefore, a two-layer insulating film consisting of a normal insulating film and this amorphous silicon layer is always present between each of the two electrodes.

[0007]

[Embodiment] An embodiment will be described below based on the drawings. 1 and 2, (1) is a transparent substrate such as a glass plate, (G
) is a gate electrode selectively deposited on the FET formation region on the surface of the transparent substrate (1), and is connected to the row electrode (X). These gate electrodes (G) and row electrodes (X) are
It is formed by vapor deposition or sputtering of ITO (Indium Tin Oxide). (2) is a SiO2 film formed on the surface of the substrate (1) covering the gate electrode (G) and row electrode (X), using thermal CVD method or plasma CVD method.
The film is formed by heating at about 250 to 300°C. The thickness of this SiO2 film (2) is about 1000 to 50
It is set within a range of 00 Å. This is due to the following reasons. That is, this SiO2 film (
If 2) is made as thin as, for example, about 500 Å, the characteristics of the FET will become unstable, and the dark current when off will be 10-9 to 1
It is large at 0-8A (when the gate voltage is 30V and the drain voltage is 0V), and the variation in the obtained current is 10-8~
It is highly unstable at 10-5A. In order to stabilize the characteristics, the film thickness is preferably about 1000 Å. On the other hand, the thicker the film, the smaller the leakage current, but the thicker the film, the higher the drive voltage and threshold voltage, and the more difficult it is for current to flow, so the upper limit of the film thickness is preferably about 5000 Å.

(AS) is a FET on SiO2 film (2)
The amorphous silicon layer is deposited in a band shape covering the formation area, and after depositing amorphous silicon on the entire surface of the SiO2 film (2) by plasma CVD, it is formed into a predetermined pattern by etching. This amorphous silicon layer (AS) completely covers the gate electrode (G),
Moreover, it has a shape extending from the gate electrode (G) to the left and right (FIG. 2). (S) (D) are amorphous silicon layers (
AS), these are source/drain electrodes disposed directly above the gate electrode (G) at a predetermined interval, and are formed by Al sputtering or the like. Drain electrode (
In D), a part of the column electrode (Y) is also used.

Therefore, as is clear from the plan view of FIG. 1, the overlapping region of the gate electrode (G) and the source/drain electrodes (S) and (D) is completely covered by the amorphous silicon layer (AS). will be done.

Note that (3) is a display electrode made of an ITO film, which is in contact with the source electrode (S).

With such a structure, an amorphous silicon layer (AS) extends between the source and drain electrodes (S) (D) and the gate electrode (G), and the SiO2 film (2
), so the source/drain electrodes (
Leakage between S) (D) and the gate electrode (G) is prevented. Furthermore, since the amorphous silicon layer (AS) is completely interposed at the intersection of the row and column electrodes (X) and (Y) at least in the overlapping portion of both the upper and lower electrodes, as is clear from FIG.
Current leakage during this time is also prevented.

In the above embodiment, a single layer of SiO2 film was used as the insulating film, but instead of this, a SiO2 film and a Si3N4 film were used.
A two-layer structure of membranes can also be used. In this case, Si
The thickness of the O2 film is approximately 1000 to 2000 Å, and the thickness of the Si3 film is approximately 1000 to 2000 Å.
The thickness of the N4 film is set to about 1000 to 3000 Å.

[0013]

Effects of the Invention As is clear from the above description, the field effect transistor array of the present invention is completely amorphous in the electrode overlapping region between the source and drain electrodes and the gate electrode. The silicon layer extends
Since a multilayer insulating film is formed in addition to a normal insulating film, leakage between the source/drain electrode and the gate electrode is prevented. Furthermore, since the amorphous silicon layer is completely interposed at the intersection of the row and column electrodes, at least in the overlapping portion of both electrodes, current leakage between the two electrodes is similarly prevented.

[Brief explanation of drawings]

FIG. 1 is a plan view of an embodiment of a field effect transistor array of the present invention;

FIG. 2 is a sectional view taken along line I-I' of the device of the present invention in FIG. 1;

[Explanation of symbols]

1 Transparent substrate G Gate electrode X row electrode 2 SiO2 film AS Amorphous silicon layer S Source electrode D Drain electrode Y Column electrode 3 Display electrode

Claims (1)

[Claims] 1. An insulating substrate, a large number of row electrodes formed in parallel on the surface of the insulating substrate, a gate electrode connected to the row electrode and formed in a region where a field effect transistor is formed, the row electrode and the gate. an insulating layer formed to cover the electrode; a semiconductor layer formed on this insulating layer at least in a region where a field effect transistor is formed; a source electrode and a drain electrode formed on this semiconductor layer; The semiconductor layer is provided with a series of column electrodes, and the semiconductor layer is interposed between the source and gate electrodes, between the drain and gate electrodes, and between the row and column electrodes, and completely encompasses the overlapping region of both electrodes at least between each electrode. Features a field-effect transistor array.