JPH08331009A - Spread spectrum signal demodulator - Google Patents

Abstract

PURPOSE: To apply inverse spread of a spread spectrum signal by generating a PN code accurately synchronously with a reception signal with a simple circuit configuration. CONSTITUTION: A PLL takes synchronization with a received spectrum and a PN code generator 18 generates a PN code and provides an output based on a clock signal obtained by frequency-dividing a carrier signal outputted from the PLL. A multiplier 30 multiplies an inverse spread signal obtained by multiplying the received signal with the generated PN code at a multiplier 10 with the carrier signal from a VCO 16. The signal obtained by multiplication is fed to a PN code synchronization detector 26 via a low pass filter 22, and the PN code synchronization detector 26 detects an asynchronizing state between the received PN code and the generated PN code. When the asynchronizing state is detected, a phase of a clock signal outputted from a 1/N frequency divider 20 is shifted based on the detection to adjust an output timing of a self-running PN code.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum signal demodulation device for demodulating a signal spread spectrum by a predetermined spread code.

[0002]

2. Description of the Related Art Conventionally, various wireless communication systems have been proposed, among which there is a spread spectrum communication system.
This spread spectrum communication system (in particular, direct spread system: D
In S), the primary modulation signal obtained by modulating the information signal on the transmission side is multiplied by a spread code to obtain a spectrum-spread signal. Then, the spectrum-spread signal is wirelessly transmitted. On the other hand, on the receiving side, the received signal is despread by multiplying the received signal by a spread code to return the received signal to a primary modulated signal, and this is demodulated to obtain an information signal.

Here, in the spread spectrum communication system, the receiving side has to despread the received signal. Due to this despreading, the spreading code generated at the receiving side is spread code (received spreading code) in the received signal. Code) must be synchronized and multiplied.

As one of such despreading means, there is a delay lock loop (hereinafter referred to as DLL).
In this DLL, as shown in FIG. 4, despreading is performed by multiplying the received signal (SS) by a spreading code in a multiplier 40. Therefore, the multiplier 40 receives the received signal (SS)
The spreading code (in this example, a PN (pseudo noise) code) to be multiplied by must be synchronized with the spreading code superimposed on the received signal (SS).

Therefore, in this apparatus, the PN code generator 4
Two PN codes different from each other by 1 bit among the PN codes generated by 6 are supplied to multipliers 42 and 44, respectively, and these two multipliers 42 and 44 respectively multiply the received signal (SS) by the PN code. To do.

Envelope detectors 48 and 50 detect envelopes from the signals obtained as a result of the multiplication, and obtain correlation outputs 1 and 2 as shown in FIGS. 5 (a) and 5 (b). This correlation output 1, 2
Becomes a high level when the PN code of the received signal (SS) and the multiplied PN code are synchronized, and becomes a triangular wave whose output becomes 0 when deviated by 1 bit or more. This 2
The three triangular waves are shifted by one bit from each other, and the triangular waves are output from the envelope detectors 48 and 50 and are output from the comparator 52.
Is input to the comparator 2, and the difference between the two triangular waves is obtained by the comparator 2. Then, as a result, a composite correlation signal as shown in FIG. 5C is obtained.

When the composite correlation signal is output from the comparator 52, it is input to the voltage controlled crystal oscillator (VCO) 56 whose phase of the output signal is controlled by the input voltage via the low pass filter 54. In the configuration of FIG. 4, the output frequency of the VCO 56 changes according to the output voltage of the comparator 52, the output control clock of the PN code generator 46 is controlled accordingly, and the PN code from the PN code generator 46 is changed. The output timing is changed. Therefore, the output from the PN code generator 46 is controlled so that the output of the comparator 52 reaches the tracking point a point (0 level) in FIG. 5C.

Here, the point a is located in the middle of the synchronization points of the outputs of the two 1-bit shifted PN codes which are the outputs of the PN code generator 46. The time corresponding to 1 bit of the PN code is 1T (chip). Therefore, the (n-1) PN code whose phase is advanced is delayed by T / 2 by the (1/2) T delay unit 58, and the delayed PN code is delayed.
If the code is supplied to the multiplier 40 and multiplied by the received signal, despreading can be performed by the PN code synchronized with the received signal (SS). The information signal can be taken out by supplying the despread signal as described above to an information demodulation circuit (primary demodulation circuit) not shown.

[0009]

Such a DLL is
Follow-up control can be effectively performed for shifts of 1 bit or less, but follow-up cannot be performed when the synchronization is lost by 1 bit or more. Therefore, in order to capture the initial synchronization, a sliding correlator or the like forcibly forcing the synchronization within a 1-bit range is required, which causes a problem that the circuit configuration becomes complicated.

The present invention has been made in view of the above problems, and can follow a sync loss of 1 bit or more to within 1 bit with a simple configuration, and can also shift to within 1 bit. An object of the present invention is to provide a spread spectrum signal demodulation device capable of tracking control and accurately performing despreading of a spread spectrum signal.

[0011]

The present invention is a spread spectrum signal demodulating device for demodulating a received signal that has been spread spectrum by a predetermined spread code, wherein the spread spectrum received signal is multiplied by the created spread code. A phase-locked loop that detects a carrier from the despread signal obtained by generating a carrier signal having the same frequency as the carrier, and a spreading code that generates a spreading code in synchronization with the carrier signal from the phase-locked loop. A generation circuit, a first multiplication circuit for multiplying the spread code and the received signal to obtain a despread signal, the carrier signal from the phase locked loop, and the despread signal from the first multiplication circuit. A second multiplication circuit for multiplying by and a synchronization detection of the spread code created with respect to the received signal based on the output from the second multiplication circuit, A synchronization detection circuit for generating a synchronization detection signal according to the period error, and adjusting the output timing of the spread signal from the spread code generation circuit according to the synchronization detection signal output from the synchronization detection circuit. It is characterized by

Further, the synchronization detection signal has a frequency divider for generating a clock signal for controlling an output timing of the spread code from the spread code generation circuit based on the carrier signal from the phase locked loop. The phase of the clock signal generated by the frequency divider is shifted based on

[0013]

In the spread spectrum signal demodulating device of the present invention, the spread spectrum signal generated by the spread code generation circuit is multiplied by the spread spectrum signal received by the first multiplication circuit to obtain a despread signal. Further, the phase-locked loop detects a carrier from the despread signal and generates a carrier signal. The second multiplication circuit multiplies the carrier signal by the despread signal, and based on the signal obtained by the multiplication by the second multiplication circuit, the synchronization detection circuit causes the spread signal from the spread code generation circuit to operate. And a synchronization error between the received spread signal and the received spread signal is detected. Then, when the two spread signals are not synchronized, the synchronization detection signal is generated in response to this, and the output timing of the spread signal from the spread code generation circuit is changed. For example, the output timing of the spread signal can be changed by shifting the phase of the clock signal for outputting the spread code supplied from the frequency divider to the spread signal generating circuit. As a result, the spread code from the spread code generating circuit can be synchronized with the received spread signal, and by multiplying the received signal by this spread code, accurate spectrum despreading becomes possible.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment.

In the figure, the received spread spectrum signal (received signal) is input from the antenna 2 to the despreading multiplier 10 via the frequency converter 4. Multiplier 10
Multiplies the received signal (SS) by the PN code output from the PN code generator 18 as a spread code, whereby
A despread signal (primary modulation signal) is obtained. When the obtained despread signal is supplied to the primary demodulator 28, the primary demodulator 2
8 demodulates this and an information signal is obtained.

Further, a phase locked loop (PLL)
Is a phase comparator (PD) 12, a low pass filter 14,
It is composed of a VCO 16. Then, the phase comparator (PD) 12 causes the PN code generator 18 to generate a PN code (hereinafter referred to as a free-running PN code) for the received signal (SS).
The despread signal obtained by multiplying by and the carrier signal (CS) output from the VCO 16 are phase-compared with each other, and the PLL operates so as to eliminate this phase difference. Therefore, during phase synchronization of the PLL, the VCO 16 oscillates at the same frequency as the carrier wave of the received signal (SS) and outputs the carrier signal (CS). The carrier signal (CS) is supplied to the N divider 20 and divided by N, and this is supplied to the PN code generator 18 as a clock signal. The PN code generator 18 multiplies the free-running PN code by the multiplier 1 at the timing based on this clock signal.
Output to 0. The received signal (SS) in the PLL
The initial oscillation frequency of the VCO 16 is set to a frequency shifted with respect to the carrier frequency of the known received signal (SS) in the system in order to acquire the initial synchronization with the carrier of the VCO 16.

The PN code generator 18 has, for example, a four-stage shift register 100 as shown in FIG. 2 and an exclusive OR circuit 101, and has a circuit configuration for generating an m-sequence code. The clock signal supplied from the N frequency divider 20 in FIG. 1 is input to the clock input terminal CK of each shift register, and the output from the Q terminal of the final stage shift register is output to the multiplier 10 via the inverting circuit. Is supplied to. The output from the shift register at the final stage is supplied to one input terminal of the exclusive OR circuit and compared with the output from the shift register at the first stage. If the two signs are different, "0" is output. Is supplied to the D terminal of the first-stage shift register.

Further, in FIG. 1, the carrier signal (CS) output from the VCO 16 is also supplied to the multiplier 30. Then, the multiplier 30 calculates the despread signal obtained by multiplying the received signal (SS) by the free-running PN code, and the VCO 16
With the carrier signal (CS) from Here, when the PN code is m (t), the carrier is cos (ωt + θi), and the modulation signal is ignored, the reception signal (SS) is expressed by the following equation.

[0019]

## EQU1 ## m (t) cos (ωt + θi) (1) Further, the carrier signal (CS) output from the VCO 16 is
It is shown by the following formula. Here, since the phase of the output signal of the multiplier 10 deviates from the phase of the received signal due to the signal delay in the circuit such as the PN code generator 18, the phase of the output signal from the VCO 16 does not match the phase of the received signal. So VCO
The shifted phase between the 16 output signals and the received signal is shown as θo.

[0020]

## EQU00002 ## cos (.omega.t + .theta.o) (2) Then, the free-running PN code that the PN code generator 18 outputs in synchronization with the clock signal from the N frequency divider 20 is m '(t).
Then, the despread signal obtained by multiplying the received signal (SS) by this free-running PN code in the multiplier 10 is given by the following equation.

[0021]

## EQU3 ## m (t) .m '(t) cos (ωt + θi) (3) Further, in the multiplier 30, the despread signal and the carrier signal (CS) are added.
The signal obtained by multiplying by and is given by

[0022]

[Mathematical formula-see original document] m (t) m '(t) {cos ([theta] i- [theta] o) + cos (2 [omega] t + [theta] i + [theta] o)} (4) where the cos ([theta] i- [theta] o) component is indicated by a constant value k, and further PLL Locks and the phase shift between the received signal (SS) and the carrier signal (CS) is eliminated, (θi-θ
o) = 0, and the cos (θi−θo) component of the equation (4) becomes 1. Also, the sum component cos (2ωt +
θi + θo) is removed by passing through the low-pass filter 22. Therefore, the PN code synchronization detector 26
Will be supplied with the following signal.

[0023]

## EQU00005 ## m (t) .m '(t) .k (5) In the above equation (5), the received PN code m (t) and the free-running PN code m' (t) are If synchronized, it becomes m ² (t), and the value becomes “1”. On the other hand, the received PN code m (t)
If the self-propelled PN code m '(t) is deviated, the value of the equation (5) becomes "0". Furthermore, if the deviation between the two PN codes is within 1T, the value of the expression (5) becomes a value smaller than "1".

The PN code sync detector 26 does not generate a sync signal when the output signal level from the LPF 22 is "1", and generates a sync signal when the output signal level from the LPF 22 is other than "1". Specifically, for example, LP
When the output signal level from F22 is other than "1",
An H-level synchronization detection signal is generated, and this synchronization detection signal is output to the N frequency divider 20 in synchronization with the carrier signal (CS).
Then, the N frequency divider 20 changes the phase of the clock signal that controls the output timing of the free-running PN code based on this synchronization detection signal for a fixed period (within 1T, for example, T / N).
In this way, the output timing of the free-running PN code is sequentially set to 1T.
Free-running P for the received PN code if shifting within
It is possible to eliminate even a shift of the N code within 1 bit, and accurate despreading becomes possible.

If it is determined that the deviation between the received PN code and the free-running PN code is large in accordance with the output signal level from the LPF 22, the shift amount of the output timing of the free-running PN code should be increased. Thereby, it becomes possible to establish the synchronization of the two codes in a short period of time. In this case, if the PN code synchronization detector 26 counts the carrier signal (CS) supplied as a clock and adjusts the output period of the synchronization detection signal, the output timing according to the output level of the LPF 22 can be changed. It's easy.

Further, since the received PN code and the free-running PN code may partially match, the PN code synchronization detector 2
It is preferable that 6 detects whether or not the two codes all match for a period of one cycle of the PN code or more.

The phase control of the clock signal output from the N frequency divider 20 will be described below with reference to FIG.
Here, FIG. 3A shows a carrier signal (CS) output from the VCO 16, and FIG. 3B shows a frequency-divided signal of the carrier signal. Then, FIG. 3 (c) shows the frequency-divided 4 signal, and FIG. 3 (d) shows the N-divided clock signal output from the N-frequency divider 20.

The N frequency divider 20 is composed of a binary counter in which a plurality of stages of flip-flops (FF) are connected in series, and the carrier signal (CS) is divided into two by each FF.
Divided by 4, ... N divided by N, and the signal divided by N is the final stage F
It is output from F. Then, the signal of this N frequency division is
Is supplied to the clock terminal CK of the PN code generator 18 as an output clock signal of the free-running PN code.

First, the PN code synchronization detector 26 detects the asynchronous state between the received PN code and the free-running PN code as described above, and outputs the H level synchronization detection signal in synchronization with the carrier signal (CS). Output. When the output signal of the first stage FF is at the "H" level, the first stage FF of the N frequency divider 20 is preset in accordance with the synchronization detection signal. Therefore, the rising edge of the carrier signal (CS) is skipped once. Therefore, the divided-by-2 signal maintains the "H" level as shown by the dotted line in FIG. 3B, and the divided-by-4 signal obtained by further dividing the divided-by-2 signal is The signal is as shown by the dotted line 3 (c).
Further, the N-divided signal output from the FF at the final stage, that is, the clock signal for outputting the free-running PN code, has a phase corresponding to one clock of the carrier signal as shown by the dotted line in FIG. Is a delayed signal. Therefore, the output timing of the free-running PN code output from the PN code generator 18 is
It is delayed by one clock of the carrier signal (CS).

In this way, the PN code synchronization detector 26 is applied to the free-running PN code output with a delay of one clock.
Detects again whether it is synchronized with the received signal (SS), and if synchronized, outputs the L level synchronization detection signal. On the other hand, if the synchronization is not yet established, the H-level synchronization detection signal is generated, and the phase of the output clock of the N frequency divider 20 is further delayed by one clock of the carrier signal. Then, the above operation is executed until synchronization is achieved.

The phase shift in the N frequency divider 20 may be performed not only in the direction of delaying the phase of the output clock signal as shown in FIG. 3 but also in the direction of advancing the phase.

[0032]

According to the spread spectrum signal demodulating apparatus of the present invention, the state of the synchronization error between the reception spread code of the spread spectrum received signal and the created spread signal is detected, and when the synchronization error is not detected, Adjusts the output timing of the spread signal from the spread code generation circuit. Therefore, the two spreading codes can be synchronized with each other, and the received signal can be accurately despread using the spread signal generated in synchronization with the received spread signal. Further, since a special circuit for initial acquisition is not necessary, the circuit configuration becomes simple.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

2 is a diagram showing a configuration example of a PN code generator 18 in FIG.

FIG. 3 is a waveform diagram for explaining phase control of a clock signal output from the N frequency divider 20 in FIG.

FIG. 4 is a block diagram showing a configuration of a conventional DLL.

FIG. 5 is a diagram showing waveforms of respective signals in a conventional DLL.

[Explanation of symbols]

2 antennas, 4 frequency converters, 10,301 multipliers, 12 phase comparators, 14,22 low pass filters, 16 VCOs, 18 PN code generators, 20N frequency dividers, 26 PN code synchronization detectors, 100 shift registers, 101 Exclusive OR circuit.

Claims (2)

[Claims] 1. A spread spectrum signal demodulating device for demodulating a received signal spread spectrum by a predetermined spread code, the despread signal being obtained by multiplying the spread spectrum received signal by the created spread code. A phase-locked loop that detects a carrier wave from the carrier wave and generates a carrier signal having the same frequency as the carrier wave; a spreading code generation circuit that generates a spreading code in synchronization with the carrier signal from the phase-locked loop; A second multiplication circuit for multiplying the received signal to obtain a despread signal; a second multiplication circuit for multiplying the carrier signal from the phase locked loop by the despread signal from the first multiplication circuit;
A multiplication circuit, and a synchronization detection circuit that performs synchronization detection of the spread code created for the reception signal based on the output from the second multiplication circuit and generates a synchronization detection signal according to a synchronization error, A spread spectrum signal demodulation device, characterized in that an output timing of the spread signal from the spread code generation circuit is adjusted according to a sync detection signal output from the sync detection circuit. 2. The spread spectrum signal demodulating device according to claim 1, further comprising a clock for controlling an output timing of the spread code from the spread code generating circuit based on the carrier signal from the phase locked loop. A spread spectrum signal demodulation device comprising a frequency divider for generating a signal, and shifting the phase of the clock signal generated by the frequency divider based on the synchronization detection signal.