JP3234446B2 - Spread spectrum signal demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum signal demodulator for demodulating a signal spread spectrum by a predetermined spread code.

[0002]

2. Description of the Related Art Conventionally, various radio communication systems have been proposed, and among them, there is a spread spectrum communication system.
This spread spectrum communication system (in particular, direct spread system: D
In S), the primary modulation signal obtained by modulating the information signal on the transmission side is multiplied by a spreading code to obtain a spectrum-spread signal. Then, the spectrum-spread signal is transmitted by radio. On the other hand, the receiving side despreads the spectrum-spread received signal by multiplying the received signal by a spreading code, returns the received signal to a primary modulated signal, and demodulates the signal to obtain an information signal.

Here, in the spread spectrum communication system, the receiving signal must be despread on the receiving side, and for this despreading, a spreading code generated on the receiving side is converted into a spreading code (receiving spread) in the received signal. Sign) and must be multiplied synchronously.

As one of such despreading means, there is a delay lock loop (hereinafter, referred to as DLL).
In this DLL, as shown in FIG. 4, a multiplier 40 performs despreading by multiplying the received signal (SS) by a spreading code. Therefore, the received signal (SS) is output by the multiplier 40.
(In this example, a PN (pseudo noise) code) must be synchronized with the spreading code superimposed on the received signal (SS).

Therefore, in this device, the PN code generator 4
6 are supplied to multipliers 42 and 44, respectively, and the two multipliers 42 and 44 respectively multiply the received signal (SS) by the PN code. I do.

The envelope detectors 48 and 50 detect an envelope from the signal obtained as a result of the multiplication, and obtain correlation outputs 1 and 2 as shown in FIGS. 5 (a) and 5 (b). This correlation output 1, 2
Becomes a high level when the PN code of the received signal (SS) and the multiplied PN code are synchronized, and becomes a triangular wave whose output becomes 0 when the PN code is shifted by one bit or more. This 2
The two triangular waves are shifted from each other by one bit, and the triangular waves are output from the envelope detectors 48 and 50 and output from the comparator 52.
, And the difference between the two triangular waves is obtained by the comparator 2. As a result, a synthetic correlation signal as shown in FIG. 5C is obtained.

When the composite correlation signal is output from the comparator 52, it is input via a low-pass filter 54 to a voltage-controlled crystal oscillator (VCO) 56 in which the phase of the output signal is controlled by the input voltage. 4, the output frequency of the VCO 56 changes in accordance with the output voltage of the comparator 52, and the output control clock of the PN code generator 46 is controlled accordingly. Output timing is changed. For this reason, the output from the PN code generator 46 is controlled so that the output of the comparator 52 reaches the tracking point a (0 level) in FIG.

Here, the point a is located in the middle of the synchronization points of the outputs of the two PN codes shifted by 1 bit, which are the outputs of the PN code generator 46. The time corresponding to one bit of the PN code is 1T (chip). Therefore, the (n-1) PN code whose phase is advanced is delayed by T / 2 by the (1/2) T delay unit 58, and the delayed PN code is used.
When the code is supplied to the multiplier 40 and multiplied by the received signal, despreading can be performed using a PN code synchronized with the received signal (SS). The information signal can be extracted by supplying the despread signal to an information demodulation circuit (primary demodulation circuit) (not shown).

[0009]

Such a DLL is,
The tracking control can be effectively performed for a shift of one bit or less, but cannot be followed for a shift of one bit or more. Therefore, for the initial synchronization acquisition, a sliding correlator or the like that forcibly drives the synchronization within a 1-bit range that can follow the synchronization is required, and there has been a problem that the circuit configuration is complicated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a simple structure which can follow out-of-synchronization of one or more bits to within one bit, and can also perform shifts within one bit. It is an object of the present invention to provide a spread spectrum signal demodulation apparatus capable of performing tracking control and accurately despreading a spread spectrum signal.

[0011]

SUMMARY OF THE INVENTION The present invention relates to a spread spectrum signal demodulator for demodulating a received signal which has been spread with a predetermined spreading code, and multiplies the spread signal by a generated spreading code. A phase-locked loop for detecting a carrier from the obtained despread signal and generating a carrier signal having the same frequency as the carrier, and a spreading code for generating a spreading code in synchronization with the carrier signal from the phase-locked loop. A generation circuit, a first multiplication circuit for multiplying the spread code and the reception signal to obtain a despread signal, the carrier signal from the phase locked loop, and the despread signal from the first multiplication circuit A multiplication circuit that multiplies the spread signal, and performs synchronization detection of the spread code created for the reception signal based on an output from the second multiplication circuit, It includes a synchronization detection circuit for generating a sync detection signal corresponding to the period error, and depending on the synchronization detection signal outputted from the synchronous detection circuit, the phase-locked dollars
And controlling the phase of the carrier signal from the loop to adjust the output timing of the spread signal from the spread code generation circuit.

A frequency divider for generating a clock signal for controlling an output timing of the spread code from the spread code generation circuit based on the carrier signal from the phase locked loop; The phase of the clock signal generated by the frequency divider is shifted based on

[0013]

In the spread spectrum signal demodulator of the present invention, the received signal spread in the first multiplication circuit is multiplied by the spread signal generated by the spread code generation circuit, thereby obtaining a despread signal. Further, a phase locked loop detects a carrier from the despread signal and generates a carrier signal. The second multiplication circuit multiplies the carrier signal by the despread signal, and based on the signal obtained by multiplication by the second multiplication circuit, the synchronization detection circuit generates a spread signal from the spread code generation circuit. And a synchronization error between the received signal and the received spread signal. If the two spread signals are not synchronized, a synchronization detection signal is generated accordingly and the phase lock is generated.
The output timing of the spread signal from the spread code generation circuit is changed by controlling the phase of the carrier signal from the quad loop . For example, the output timing of the spread signal can be changed by shifting the phase of the clock signal for outputting the spread code supplied from the frequency divider to the spread signal generating circuit. This makes it possible to synchronize the spread code from the spread code generation circuit with the received spread signal. By multiplying the received signal by this spread code, accurate spectrum despreading becomes possible.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment.

In FIG. 1, a received spread spectrum signal (received signal) is input from an antenna 2 to a multiplier 10 for despreading via a frequency converter 4. Multiplier 10
Multiplies the received signal (SS) by a PN code output as a spreading code from the PN code generator 18, whereby
A despread signal (primary modulation signal) is obtained. When the obtained despread signal is supplied to the primary demodulator 28, the primary demodulator 2
8 demodulates this, and an information signal is obtained.

A phase locked loop (PLL)
Is a phase comparator (PD) 12, a low-pass filter 14,
It is constituted by the VCO 16. Then, the phase comparator (PD) 12 outputs a PN code (hereinafter, referred to as a self-running PN code) generated by the PN code generator 18 to the received signal (SS).
Are compared with the carrier signal (CS) output from the VCO 16, and the above-mentioned PLL works so as to eliminate this phase difference. Therefore, during the phase synchronization of the PLL, the VCO 16 oscillates at the same frequency as the carrier of the received signal (SS) and outputs the carrier signal (CS). The carrier signal (CS) is supplied to an N frequency divider 20 and frequency-divided by N, and is supplied to the PN code generator 18 as a clock signal. The PN code generator 18 multiplies the free running PN code by the multiplier 1 at a timing based on the clock signal.
Output to 0. The received signal (SS) in the PLL
The initial oscillation frequency of the VCO 16 is set to a frequency shifted with respect to the carrier frequency of the known received signal (SS) in the system for the initial synchronization acquisition with the carrier of the VCO 16.

The PN code generator 18 has, for example, a four-stage shift register 100 as shown in FIG. 2 and an exclusive OR circuit 101, and has a circuit configuration for generating an m-sequence code. The clock signal supplied from the N frequency divider 20 in FIG. 1 is input to the clock input terminal CK of each shift register, and the output from the Q terminal of the last stage shift register is output to the multiplier 10 via an inverting circuit. Supplied to Also, the output from the last-stage shift register is supplied to one input terminal of the exclusive OR circuit, and is compared with the output from the first-stage shift register. Is supplied to the D terminal of the first-stage shift register.

In FIG. 1, the carrier signal (CS) output from the VCO 16 is also supplied to a multiplier 30. Then, multiplier 30 despreads a signal obtained by multiplying the received signal (SS) by the free-running PN code and VCO 16
Multiplied by the carrier signal (CS). Here, when the PN code is m (t), the carrier is cos (ωt + θi), and the modulated signal is ignored, the received signal (SS) is expressed by the following equation.

[0019]

M (t) cos (ωt + θi) (1) The carrier signal (CS) output from the VCO 16 is
It is shown by the following equation. Here, the phase of the output signal of the multiplier 10 deviates from the phase of the received signal due to a signal delay in a circuit such as the PN code generator 18, so that the output signal from the VCO 16 and the received signal do not match. So, VCO
The shifted phase between the 16 output signals and the received signal is shown as θo.

[0020]

Cos (ωt + θo) (2) Then, the free-running PN code output from the PN code generator 18 in synchronization with the clock signal from the N frequency divider 20 is represented by m ′ (t).
Then, a despread signal obtained by multiplying the received signal (SS) by the free-running PN code in the multiplier 10 is given by the following equation.

[0021]

M (t) · m ′ (t) cos (ωt + θi) (3) Further, in the multiplier 30, the despread signal and the carrier signal (CS) are obtained.
Is obtained by multiplying by the following equation.

[0022]

M (t) m ′ (t) {cos (θi−θo) + cos (2ωt + θi + θo)} (4) where the cos (θi−θo) component is represented by a constant value k, and PLL Are locked and the phase shift between the received signal (SS) and the carrier signal (CS) is eliminated, (θi−θ
o) = 0, and the cos (θi−θo) component of equation (4) becomes 1. Also, the sum component cos (2ωt +
θi + θo) is removed by passing through the low-pass filter 22. Therefore, the PN code synchronization detector 26
Is supplied with the following signal.

[0023]

M (t) · m ′ (t) · k (5) In equation (5), the received PN code m (t) and the free-running PN code m ′ (t) are If synchronized, the value is m ² (t), and the value is “1”. On the other hand, the reception PN code m (t)
And the self-running PN code m ′ (t) is shifted, the value of the expression (5) becomes “0”. Further, if the difference between the two PN codes is within 1T, the value of the expression (5) becomes a value smaller than “1”.

The PN code synchronization detector 26 does not generate a synchronization signal when the output signal level from the LPF 22 is "1", and generates a synchronization signal when the output signal level from the LPF 22 is other than "1". Specifically, for example, LP
When the output signal level from F22 is other than "1",
An H level synchronization detection signal is generated, and the synchronization detection signal is output to the N frequency divider 20 in synchronization with the carrier signal (CS).
Then, the N frequency divider 20 changes the phase of the clock signal for controlling the output timing of the free-running PN code based on the synchronization detection signal for a certain period (within 1T, for example, T / N).
As described above, the output timing of the self-running PN code is sequentially set to 1T.
If it is shifted within, the free-running P for the received PN code
A deviation within one bit of the N code can be resolved, and accurate despreading can be performed.

If it is determined that the difference between the received PN code and the free-running PN code is large according to the output signal level from the LPF 22, the shift amount of the output timing of the free-running PN code is increased. This makes it possible to establish synchronization of two codes in a short period of time. In this case, if the PN code synchronization detector 26 counts the carrier signal (CS) supplied as a clock and adjusts the output period of the synchronization detection signal, the output timing according to the output level of the LPF 22 can be changed. Easy.

Further, since the received PN code and the free-running PN code may partially coincide with each other, the PN code synchronization detector 2
6 preferably detects whether the two codes are all the same over one period of the PN code.

Hereinafter, the phase control of the clock signal output from the N frequency divider 20 will be described with reference to FIG.
Here, FIG. 3A shows a carrier signal (CS) output from the VCO 16, and FIG. 3B shows a halved signal of the carrier signal. FIG. 3C shows a divide-by-4 signal, and FIG. 3D shows a clock signal output from the N-divider 20 and divided by N.

The N frequency divider 20 is composed of a binary counter in which a plurality of stages of flip-flops (FF) are connected in series, and the FF of each stage divides the carrier signal (CS) by two.
Divides by 4,... Divides by N, and the signal which is divided by N is
Output from F. Then, the signal of this N frequency division is shown in FIG.
Is supplied to the clock terminal CK of the PN code generator 18 as an output clock signal of the free-running PN code.

First, the PN code synchronization detector 26 detects an asynchronous state between the received PN code and the free-running PN code as described above, and outputs an H level synchronization detection signal in synchronization with the carrier signal (CS). Output. When the output signal of the first stage FF is at “H” level, the first stage FF of the N frequency divider 20 is preset according to the synchronization detection signal. Therefore, the rise of the carrier signal (CS) is skipped once. Therefore, the divide-by-2 signal maintains the "H" level as shown by the dotted line in FIG. 3B, and the divide-by-4 signal obtained by further dividing the divide-by-2 signal is shown in FIG. The signal is as shown by the dotted line in FIG.
Further, the frequency-divided N signal output from the final stage FF, that is, the clock signal for output of the self-running PN code, has a phase corresponding to that of the carrier signal by one clock as shown by a dotted line in FIG. Is a delayed signal. Therefore, the output timing of the self-running PN code output from the PN code generator 18 is
It is delayed by one clock of the carrier signal (CS).

The self-propelled PN code output with a delay of one clock is output from the PN code synchronization detector 26.
Detects again whether or not it is synchronized with the received signal (SS), and if so, outputs an L level synchronization detection signal. On the other hand, if the synchronization has not yet been established, an H level synchronization detection signal is generated, and the phase of the output clock of the N frequency divider 20 is further delayed by one clock of the carrier signal. Then, the above operation is executed until synchronization is achieved.

The phase shift in the N frequency divider 20 may be not only in the direction of delaying the phase of the output clock signal as shown in FIG. 3, but also in the direction of increasing the phase.

[0032]

According to the spread spectrum signal demodulation apparatus of the present invention, the state of the synchronization error between the received spread code for the spread spectrum received signal and the generated spread signal is detected, Adjusts the output timing of the spread signal from the spread code generation circuit. Therefore, the two spread codes can be synchronized, and the received signal can be accurately despread using the spread signal generated in synchronization with the received spread signal. Further, since a special circuit or the like for initial capture is not required, the circuit configuration is simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a PN code generator 18 of FIG.

FIG. 3 is a waveform diagram for explaining phase control of a clock signal output from an N frequency divider 20 of FIG. 1;

FIG. 4 is a block diagram showing a configuration of a conventional DLL.

FIG. 5 is a diagram showing waveforms of signals in a conventional DLL.

[Explanation of symbols]

2 antenna, 4 frequency converter, 10,301 multiplier, 12 phase comparator, 14,22 low-pass filter, 16 VCO, 18 PN code generator, 20N frequency divider, 26 PN code synchronization detector, 100 shift register, 101 Exclusive OR circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-347600 (JP, A) JP-A-5-308342 (JP, A) JP-A-5-244117 (JP, A) JP-A-7- 326985 (JP, A) JP-A-7-297755 (JP, A) JP-A-7-240700 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04B 1/69-1 / 713 H04J 13/00-13/06 H04L 7/00

Claims (2)

(57) [Claims] 1. A spread spectrum signal demodulator for demodulating a received signal spread spectrum by a predetermined spread code, comprising: a despread signal obtained by multiplying a spread signal and a generated spread code. A phase locked loop that detects a carrier from the carrier and generates a carrier signal having the same frequency as the carrier, a spreading code generation circuit that generates a spreading code in synchronization with the carrier signal from the phase locked loop, A first multiplication circuit for multiplying the reception signal to obtain a despread signal; and a second multiplication circuit for multiplying the carrier signal from the phase locked loop by the despread signal from the first multiplication circuit.
A multiplication circuit, and a synchronization detection circuit that performs synchronization detection of the created spread code with respect to the reception signal based on an output from the second multiplication circuit, and generates a synchronization detection signal according to a synchronization error, According to a synchronization detection signal output from the synchronization detection circuit ,
The phase of the carrier signal from the phase locked loop
A spread-spectrum signal demodulation apparatus for controlling the output timing of the spread signal from the spread code generation circuit by controlling the spread-spectrum signal. 2. The spread spectrum signal demodulation apparatus according to claim 1, further comprising: a clock for controlling an output timing of said spread code from said spread code generating circuit based on said carrier signal from said phase locked loop. A spread spectrum signal demodulation apparatus, comprising: a frequency divider for generating a signal; and shifting a phase of the clock signal generated by the frequency divider based on the synchronization detection signal.