JPH08331008A - Demodulator for spread spectrum signal - Google Patents

Abstract

PURPOSE: To apply inverse spread of a spread spectrum signal by generating a PN code precisely synchronously with a reception signal with a simple circuit configuration. CONSTITUTION: A PLL takes synchronization with a received spectrum and a PN code generator 18 generates a PN code and provides an output of it to a multiplier 10 based on a carrier signal(CS) outputted from a VCO 16 of the PLL. A multiplier 30 multiplies a received signal (SS) with the carrier signal (CS) to extract the PN code in the received signal. A coincidence detector 26 compared the extracted PN code with a specific code in the PN code stored in a code string storage section 24 and generates a detection signal when they are coincident. The PN code generator 18 is set depending on the detection signal so that the PN code generated by the PN code generator 18 is coincident with a PN code extracted from a received signal. Thus, the PN code multiplied by the multiplier 10 is synchronously with the PN code of the received signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum signal demodulation device for demodulating a signal spread spectrum by a predetermined spread code.

[0002]

2. Description of the Related Art Conventionally, various wireless communication systems have been proposed, among which there is a spread spectrum communication system.
This spread spectrum communication system (in particular, direct spread system: D
In S), the primary modulation signal obtained by modulating the information signal on the transmission side is multiplied by a spread code to obtain a spectrum-spread signal. Then, the spectrum-spread signal is wirelessly transmitted. On the other hand, on the receiving side, the received signal is despread by multiplying the received signal by a spread code to return the received signal to a primary modulated signal, and this is demodulated to obtain an information signal.

Here, in the spread spectrum communication system, the receiving side has to despread the received signal. Due to this despreading, the spreading code generated at the receiving side is spread code (received spreading code) in the received signal. Code) must be synchronized and multiplied.

As one of such despreading means, there is a delay lock loop (hereinafter referred to as DLL).
In this DLL, as shown in FIG. 4, despreading is performed by multiplying the received signal (SS) by a spreading code in a multiplier 40. Therefore, the multiplier 40 receives the received signal (SS)
The spreading code (in this example, a PN (pseudo noise) code) to be multiplied by must be synchronized with the spreading code superimposed on the received signal (SS).

Therefore, in this apparatus, the PN code generator 4
Two PN codes different from each other by 1 bit among the PN codes generated by 6 are supplied to multipliers 42 and 44, respectively, and these two multipliers 42 and 44 respectively multiply the received signal (SS) by the PN code. To do.

Envelope detectors 48 and 50 detect envelopes from the signals obtained as a result of the multiplication, and obtain correlation outputs 1 and 2 as shown in FIGS. 5 (a) and 5 (b). This correlation output 1, 2
Becomes a high level when the PN code of the received signal (SS) and the multiplied PN code are synchronized, and becomes a triangular wave whose output becomes 0 when deviated by 1 bit or more. This 2
The three triangular waves are shifted by one bit from each other, and the triangular waves are output from the envelope detectors 48 and 50 and are output from the comparator 52.
The difference between the two triangular waves is obtained by the comparator 52. Then, as a result, a composite correlation signal as shown in FIG. 5C is obtained.

When the composite correlation signal is output from the comparator 52, it is passed through a low pass filter 54, and the phase of the output signal is controlled by a voltage controlled oscillator (V
CO) 56. In the configuration of FIG. 4, the comparator 52
The output frequency of the VCO 56 changes according to the output voltage of
Along with this, the output control clock of the PN code generator 46 is controlled, and the output timing of the PN code from the PN code generator 46 is changed. Therefore, the output of the comparator 52 is
In order to reach the tracking point a point (0 level) in FIG.
The output from the N code generator 46 is controlled.

Here, the point a is located in the middle of the synchronization points of the outputs of the two 1-bit shifted PN codes which are the outputs of the PN code generator 46. The time corresponding to 1 bit of the PN code is 1T (chip). Therefore, the (n-1) PN code whose phase is advanced is delayed by T / 2 by the (1/2) T delay unit 58, and the delayed PN code is delayed.
If the code is supplied to the multiplier 40 and multiplied by the received signal, despreading can be performed by the PN code synchronized with the received signal (SS). The information signal can be taken out by supplying the despread signal as described above to an information demodulation circuit (primary demodulation circuit) not shown.

[0009]

Such a DLL is
Follow-up control can be effectively performed for shifts of 1 bit or less, but follow-up cannot be performed when the synchronization is lost by 1 bit or more. Therefore, in order to capture the initial synchronization, a sliding correlator or the like forcibly forcing the synchronization within a 1-bit range is required, which causes a problem that the circuit configuration becomes complicated.

The present invention has been made in view of the above problems and is capable of following a loss of synchronism of 1 bit or more to within 1 bit with a simple configuration and also for shifting within 1 bit. An object of the present invention is to provide a spread spectrum signal demodulation device capable of tracking control and accurately performing despreading of a spread spectrum signal.

[0011]

The present invention is a spread spectrum signal demodulating device for demodulating a received signal that has been spread spectrum by a predetermined spread code, wherein the spread spectrum received signal is multiplied by the created spread code. A phase-locked loop that detects a carrier wave from the signal obtained by the above and generates a carrier signal having the same frequency as the carrier wave, and a spreading code generation circuit that generates a spreading code in synchronization with the carrier signal from the phase-locked loop. A first multiplication circuit for multiplying the spread code output from the spread code generation circuit by the received signal to obtain an information signal; the carrier signal from the phase locked loop; and the received signal. And a second multiplication circuit for multiplying by and to obtain a reception spreading code, and a detection signal by detecting a specific spreading code existing in the reception spreading code. Has a detection circuit for raw, the, and adjusting the spread code generation of the spread code generation circuits in response to said detection signal.

Further, the detection circuit compares data equal to a specific spreading code in the reception spreading code with the reception spreading code, and generates the detection signal when they match.

[0013]

According to the spread spectrum signal demodulating apparatus of the present invention, the phase locked loop detects the carrier from the spread spectrum received signal and generates the carrier signal having the same frequency as the carrier. The spread code (reception spread code) is extracted from the received signal by multiplying the carrier signal and the received signal in the second multiplication circuit. Then, the detection circuit detects the specific spread code in the obtained received spread codes and generates a detection signal. Specifically, the detection circuit
For example, the data equal to the specific spreading code existing in the reception spreading code is compared with the reception spreading code, and a detection signal is generated when the two codes match. Then, when the detection circuit generates the detection signal in this way, the spreading code generated by the spreading code generation circuit in response to the predetermined state,
That is, it is controlled so as to match the received spread code. Therefore, the spread code is output from the spread code generation circuit to the first multiplication circuit in synchronization with the received signal, and the spread signal is multiplied by the spread code to perform accurate despreading.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment.

In the figure, the received spread spectrum signal (received signal) is input from the antenna 2 to the despreading multiplier 10 via the frequency converter 4. Multiplier 10
The received signal (SS) is multiplied by the PN code output from the PN code generator 18 as a spread code, whereby a despread signal (primary modulated signal) is obtained. When the despread signal is supplied to the primary demodulator 28, the primary demodulator 28 demodulates it and an information signal is obtained.

The phase locked loop (PLL) includes a phase comparator (PD) 12, a low pass filter 14 and a VCO.
It is composed of 16. Then, the phase comparator (P
D) 12 is a signal obtained by multiplying the received signal (SS) by a PN code, and a carrier signal (C) output from the VCO 16.
S) and the phase are compared so that the phase difference is eliminated.
LL works. Therefore, when the PLL is in phase synchronization, the VCO 16 oscillates at the same frequency as the carrier wave of the received signal (SS) and outputs the carrier signal (CS). This carrier signal (CS) is supplied to the N divider 20 and divided by N,
This is supplied to the PN code generator 18 as a clock signal. The PN code generator 18 outputs the PN code to the multiplier 10 at the timing based on this clock signal. Note that the initial oscillation frequency of the VCO 16 is a frequency shifted with respect to the known carrier frequency of the received signal (SS) in the system in order to capture the initial synchronization with the carrier wave of the received signal (SS) in the PLL. It is set.

The PN code generator 18 has, for example, a four-stage shift register 100 as shown in FIG. 2 and an exclusive OR circuit 101, and has a circuit configuration for generating an m-sequence code. The clock signal supplied from the N frequency divider 20 in FIG. 1 is input to the clock input terminal CL of each shift register, and the output from the Q terminal of the final stage shift register is output to the multiplier 10 via the inverting circuit. Is supplied to. The output from the shift register at the final stage is supplied to one input terminal of the exclusive OR circuit 101 and compared with the output from the shift register at the first stage,
When the two signs are different, "0" is supplied to the D terminal of the first-stage shift register.

Here, in FIG. 2, the shift register 1
The data output from the Q terminals of the respective D-FFs that make up 00 are as shown in FIG. For example, if the data held by each D-FF is set to "0000" at the beginning (state 1), the shift register 100 sequentially holds 15 patterns, and then returns to state 1 again, that is, "0000".
By the way, such a PN code has a data array peculiar to the code. For example, as shown in FIG.
The array of 00 "(the output from the fourth stage D-FF) exists only in one place in the PN code. Therefore, as described above, the unique array" 0000 "of the PN code having only one place.
By detecting, the state of the PN code can be known.

Further, in FIG. 1, the carrier signal (CS) output from the VCO 16 is also supplied to the multiplier 30. Then, the multiplier 30 multiplies the received signal (SS) by the carrier signal (CS) from the VCO 16. Here, the PN code is m (t) and the carrier is cos (ωt + θ).
i) and ignoring the modulated signal, the received signal (SS) is expressed by the following equation.

[0020]

## EQU1 ## m (t) cos (ωt + θi) (1) Further, the carrier signal (CS) output from the VCO 16 is
It is shown by the following formula. Here, since the phase of the output signal of the multiplier 10 deviates from the phase of the received signal due to the signal delay in the circuit such as the PN code generator 18, the phase of the output signal from the VCO 16 does not match the phase of the received signal. So VCO
The phase shifted between the output signal from 16 and the received signal is θ
It is shown as o.

[0021]

## EQU00002 ## cos (.omega.t + .theta.o) (2) Then, the signal obtained by multiplying the received signal (SS) and the carrier signal (CS) in the multiplier 30 is expressed by the following equation. .

[0022]

[Mathematical formula-see original document] m (t) {cos ([theta] i- [theta] o) + cos (2 [omega] t + [theta] i + [theta] o)} (3) In the equation (3), the sum component of the signals obtained by multiplication passes through the low-pass filter 22. To be removed. Therefore, the coincidence detector 26 is supplied with the signal of the following equation.

[0023]

[Mathematical formula-see original document] m (t) cos ([theta] i- [theta] o) (4) where the cos ([theta] i- [theta] o) component has a constant value k, and therefore the coincidence detector 26 In this case, m (t) k, which is equal to the PN code, is input to.

The code string storage unit 24 stores a predetermined array of PN codes, for example, "0000", and the predetermined code string is sequentially supplied to the coincidence detector 26. The coincidence detector 26 compares the PN code of the received signal (SS) with this code string “0000”, and generates a coincidence detection signal when the PN code of the received signal (SS) matches this code string.
When this coincidence detection signal is supplied to the PN code generator 18, the PN code generator 18 outputs "0000" based on this.
The PN code generator 18 is controlled so as to generate a code sequence that follows, and the PN code generator 18 sequentially generates a corresponding code sequence. Therefore, the PN code that coincides with the PN code of the received signal (SS) can be output from the PN code generator 18.

For example, the PN code generator 18 shown in FIG.
However, in the pattern as shown in FIG. 3 (4th stage D-FF output), P
It is assumed that the N code is generated. In this case, the received signal (SS)
When the coincidence detection circuit 26 detects that the PN code extracted from the register is "0000", the shift register 1
The respective D-FFs that make up 00 are the final stage (fourth stage) DF
The output data from F is sequentially set to be "1010". That is, from the PN code generator 18, "1",
Data of "0", "1", and "0" are output. Therefore, when the shift register 100 is set, the PN
The pattern of the PN code generated by the code generator 18 matches the pattern of the PN code extracted from the received signal (SS). As a result, the PN code in the received signal (SS) multiplied by the multiplier 10 and the PN code of the PN code generator 18 are synchronized, and accurate spectrum despreading can be performed. In the coincidence detection circuit 26, the PN code in the received signal (SS) used as a reference for comparison is not limited to "0000", but may be an array pattern of other PN codes shown in FIG.

[0026]

According to the spread spectrum signal demodulating apparatus of the present invention, the spread signal for despreading the received signal is extracted from the received signal based on the received spread signal extracted from the spread spectrum received signal. It can be set to a spreading code that matches the spreading signal. Therefore, it is possible to accurately despread the received signal by the spread signal synchronized with the received signal. Further, since a special circuit for initial acquisition is not necessary, the circuit configuration becomes simple.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

2 is a diagram showing a configuration example of a PN code generator 18 in FIG.

3 is a diagram showing a pattern of a PN code generated by a PN code generator 18 of FIG.

FIG. 4 is a block diagram showing a configuration of a conventional DLL.

FIG. 5 is a diagram showing waveforms of respective signals in a conventional DLL.

[Explanation of symbols]

2 antennas, 4 frequency converters, 10 and 30 multipliers, 12 phase comparators, 14 and 22 low pass filters, 16 VCOs, 18 PN code generators, 20 N frequency dividers, 24 code string storage units, 26 coincidence detectors, 100
Shift register, 101 exclusive OR circuit.

Claims (2)

[Claims] 1. A spread spectrum signal demodulating device for demodulating a received signal which is spread spectrum by a predetermined spread code, wherein a carrier is obtained from a signal obtained by multiplying the spread spectrum received signal by the created spread code. A phase-locked loop that generates a carrier signal having the same frequency as the carrier wave, a spreading code generation circuit that generates a spreading code in synchronization with the carrier signal from the phase-locked loop, and a spreading code generation circuit. The spreading code output,
A first multiplication circuit for multiplying the received signal to obtain an information signal; and a second multiplication circuit for multiplying the carrier signal from the phase locked loop and the received signal to obtain a reception spread code.
A multiplying circuit; and a detection circuit that generates a detection signal by detecting a specific spreading code existing in the reception spreading code, wherein the spreading code generated by the spreading code generation circuit according to the detection signal. And a spread spectrum signal demodulating device. 2. The spread spectrum signal demodulating device according to claim 1, wherein the detection circuit compares data equal to a specific spreading code in the receiving spreading code with the receiving spreading code, and when they match, the detecting circuit compares the data. A spread spectrum signal demodulation circuit, which generates a detection signal.