JPH08330551A - Design method of semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] [Structure] First, provisionally determine the size (vertical width and width) of the basic cell placement area in which the basic cells are placed, and let it be built in at an arbitrary position within this basic cell placement area. Place the function module to be used. Then, the inside of the basic cell arrangement region is divided by a straight line including any two sides (for example, left and right two sides) of the outer shape of each functional module facing each other, and the basic cells are spread in each of the divided regions. I did it. [Effect] The base chip of the gate array incorporating the functional module can be developed in a short period of time, and the gate array incorporating the functional module can be used without using the design data of the base chip of the existing gate array. The base chip can be designed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique particularly effective when applied to a semiconductor integrated circuit design technique and a circuit layout design method. For example, a basic cell of a gate array having a functional circuit other than the basic cell is incorporated. It is related to the technology effectively used for the paving method.

[0002]

2. Description of the Related Art Conventionally, as a base chip of a gate array, a basic cell composed of a plurality of elements capable of forming a logic gate (for example, a NAND gate) that is a base of a logic circuit is tiled inside the chip. A so-called spread cell type gate array in which peripheral cells serving as input / output buffer circuits are arranged around the gate array has been put to practical use.

By the way, in recent years, a gate array incorporating a circuit having a predetermined logic function (hereinafter, referred to as a functional module), which has been designed and evaluated, along with the increase in scale of the gate array, has been developed. Proposed. As an example of the functional module built in the gate array, for example, a functional circuit generally called a macro cell such as a CPU, a memory, a DMA control circuit, or a so-called user logic designed by a user is called. However, the type is not limited.

[0004]

In the conventional method of designing a gate array incorporating a functional module, layout data of a base chip of a gate array which has already been developed is taken and the functional module is embedded therein. Was the way. Therefore, the cells of the functional module are invalidated, and the number depends on the area of the module.It is difficult to optimize the number of basic cells that can be used. If prepared, the number of useless basic cells will increase, the cell utilization rate will decrease, and the cost will increase. On the other hand, if you bring a base chip with the minimum number of basic cells and try to place a functional module in it, there is a risk that the number of cells will be insufficient due to the functional modules being placed. Since it is necessary to change the layout and redo the layout from the beginning, there is a problem that the design time becomes extra long.

Further, in the conventional design method, in order to determine a basic cell which becomes unusable by arranging the functional modules, each cell is vertically and horizontally four times in total, and the proximity rule and the proximity rule. Since it is necessary to judge whether or not the requirement (distance) called is satisfied, for example, in a gate array consisting of 667 k (km) cells, it is necessary to judge 10672 k (= 4 × 4 × 667 k) times. However, there is a problem that the determination takes a very long time. Here, the proximity rule refers to a rule that in designing a gate array, cells (including macro cells) and cells must be separated by a predetermined distance or more due to a connection margin between cells.

An object of the present invention is to provide a layout design method for a basic cell, which allows a base chip of a gate array incorporating a functional module to be developed in a short period of time.

Another object of the present invention is to provide a basic cell layout design method capable of designing a base chip of a gate array incorporating a functional module without using design data of the existing base chip of the gate array. It is in.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The typical ones of the inventions disclosed in the present application will be outlined below.

That is, first, the size (vertical width and horizontal width) of the basic cell arrangement area in which the basic cells are arranged is provisionally determined, and the functional module is arranged at an arbitrary position in the basic cell arrangement area. Then, the inside of the basic cell arrangement region is divided by a straight line including any two sides (for example, left and right two sides) of the outer shape of each functional module facing each other, and the basic cells are spread in each of the divided regions. It was done like this.

Further, after that, it is determined whether or not each functional module overlaps with a basic cell arranged in the periphery of the functional module and whether or not a proximity rule is violated. In this case, the arrangement position of the functional module may be finely adjusted so that at least any two sides orthogonal to each other coincide with the boundary line of the basic cell.

Further, the total sum of the spread basic cells is obtained, and it is determined whether or not the required number is satisfied. If the total number is insufficient, the basic cell arrangement area is expanded according to the insufficient amount, and the above-mentioned basic cell arrangement area is again set. The functional modules may be arranged and the basic cells may be spread according to the procedure.

[0013]

According to the above means, since the functional modules are first arranged and the basic cells are spread around the functional modules, the basic cells are not wasted and the chip size and the cost can be reduced. .

Further, the overlapping of the functional module and the basic cell and the determination of the violation of the proximity rule may be performed on the four sides of each functional module. Therefore, the number of determinations is much larger than the number of similar determinations in the conventional design method. Therefore, the time required for designing the base chip of the gate array can be shortened.

Further, since it is easy to optimize the number of cells, if the functional module to be incorporated has the peripheral portion provided or provided with the data, it should be arranged on the chip as it is. However, the chip size does not increase, and by arranging in such a manner, it is possible to reduce the total design cost and the development period by eliminating the need to process already designed data.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the designing method of the present invention will be described below with reference to the drawings. FIG. 1 shows an outline of the flow of the entire procedure of the design method according to the present invention. Hereinafter, a description will be given according to the flow of FIG.

First, referring to the size (vertical width and width) of the rectangular basic cell arrangement area in which the basic cells are spread, the number of required basic cells, the number of functional modules to be built in, and the area of each are referred to. Is provisionally determined (step S1). Specifically, find the number of basic cells required to fill the same area as the area of the functional module to be built in,
From the sum of the number and the number of basic cells originally required, the size of the occupied area when they are laid out in a tile is calculated to determine the approximate size of the basic cell arrangement area. Here, the basic cell is a group of a plurality of elements (MOSFETs) capable of forming a basic logic gate (for example, NAND gate) for forming a desired logic, and in the layout design of this embodiment, It is given as layout data that specifically represents the diffusion layer and electrode shape of those elements.

Next, as shown in FIG. 2, the functional modules M1, M2, ... Which are to be built in are temporarily arranged at arbitrary positions in the basic cell arrangement area 1 (step S2).
At this time, the location of each functional module is arbitrary, but depending on the type of functional module, there may be an appropriate location based on past design experience, so it is advisable to refer to it for such modules when making decisions. .

Then, each functional module M1, M2,
.. and basic cells arranged in the vicinity thereof and overlap violation rules are determined, and a virtual outline of each functional module is created (step S3). Next, the arrangement positions of the functional modules M1, M2, ... Are finely adjusted (step S4). The adjustment of the position of the functional module is performed for each functional module on the four sides of the upper, lower, left and right sides. Then, as shown in FIG. 5A, for example, when four sides (or three sides) of the functional module M overlap the basic cell or a proximity rule violation occurs, at least any two sides orthogonal to each other. As shown in FIG. 6A, the adjustment positions of the functional modules are finely adjusted so that (the left side and the lower side in the figure) match the boundary lines BL1 and BL2 of the basic cell BC. As a result, before the adjustment, the size of the area where the basic cell cannot be placed is considerably larger than the size of the module as shown in FIG. 5B, but after the adjustment, as shown in FIG. Can be reduced to almost the same size as.

Then, as shown in FIG. 3, any two of the outer shapes of the functional modules M1, M2, ...
The basic cell placement area 1 is divided by straight lines L1, L2, ... Containing sides (two sides on the right and left in the figure), and basic cells are spread in each of the divided areas B1, B2 ,. (Steps S5 to S7). Here, the orientation of the basic cells spread in each divided area is not particularly limited, but is set so that the longer side is in the vertical direction. This is because the number of cells that can be spread increases when the basic cell placement region is divided into the dividing direction and the longitudinal direction of the cells.

Next, the divided areas B1, B2, ...
The total sum of the basic cells spread inside is calculated, and it is determined whether the required number is satisfied (steps S8 and S).
9). When the number of cells is insufficient, the basic cell arrangement area 1 is enlarged according to the insufficient amount, and the functional modules are arranged and the basic cells are spread again according to the above procedure (steps S9-S1). On the other hand, when the total number of basic cells satisfies the requirement, as shown in FIG. 4, the input / output buffer cells I are arranged around the basic cell arrangement area 1.
/ O is arranged, and bonding pads are arranged around it (step S10). Even if the basic cell arrangement area is enlarged and the rearrangement is performed in this way, the design time can be shortened because the number of determinations is smaller than that in the conventional method.

In the above-described embodiment, the inside of the basic cell arrangement area 1 is defined by vertical straight lines L1, L2, ... The cells are divided and the basic cells are spread for each of the divided areas B1, B2, ... (Steps S3 to S).
5) As described above, each functional module M1, M2,
It is also possible to divide the inside of the basic cell arrangement area 1 by a horizontal straight line including the upper and lower sides of the outer shape of ... And spread the basic cells in each of the divided areas. In that case, the orientation of the basic cells to be spread may be set such that the longer side is in the horizontal direction.

As described above, in the above embodiment, the size of the basic cell placement area in which the basic cells are placed is provisionally determined, and the functional module is placed at an arbitrary position in the basic cell placement area. After that, the basic cell placement area is divided by a straight line including any two opposite sides of the outer shape of each functional module, and the basic cells are spread in each divided area. Therefore, there is an advantage that the chip size is reduced and the cost can be reduced.

Further, after laying basic cells in the divided areas, it is determined whether or not each functional module overlaps with a basic cell arranged in the periphery thereof and violation of a proximity rule. In the case of overlapping or violating the proximity rule, the position of the functional module is finely adjusted so that at least any two sides orthogonal to each other coincide with the boundary line of the basic cell. The number of determinations for overlapping with the basic cell and for violating the proximity rule is significantly smaller than the number of determinations similar to the conventional design method, and the period required for designing the base chip of the gate array can be shortened. The effect is that

Furthermore, when the lengths of the basic cells in the vertical direction and the horizontal direction are different from each other, the longitudinal direction of the basic cells and the dividing direction of the basic cell arrangement region are arranged so as to coincide with each other, so that the basic cells can be spread. This has the effect of increasing the number of cells and reducing the useless blank area.

Further, since it is easy to optimize the number of cells, when the data is constructed or provided in the form that the functional module to be incorporated has a peripheral portion, it is arranged as it is on the chip. However, the chip size does not increase, and by arranging in such a manner, it is possible to reduce the total design cost and the development period by eliminating the need to process already designed data.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the above embodiment, basic cells of the same type are spread over each of the divided areas S1, S2, ... However, a plurality of types of basic cells (for example, cells having different numbers of elements) are prepared and divided. The basic cells to be spread may be changed depending on the area. This makes it possible to reduce the blank area where the basic cell is not arranged.

In the above description, the invention made by the present inventor was mainly applied to the layout method of the basic cells in the basic module embedded type gate array, which is the field of application of the invention. It can also be used for designing a semiconductor integrated circuit in which variable logic composed of basic cells is desired to be incorporated.

[0029]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, it becomes possible to develop the base chip of the gate array incorporating the functional module in a short period of time, and the gate incorporating the functional module can be used without using the design data of the base chip of the existing gate array. The base chip of the array can be designed.

[Brief description of drawings]

FIG. 1 is a flowchart showing an embodiment of a method for designing a semiconductor integrated circuit according to the present invention.

FIG. 2 is a layout explanatory view showing a state where functional modules are provisionally arranged by the method for designing a semiconductor integrated circuit according to the present invention.

FIG. 3 is a layout explanatory view showing a state in which the basic cell placement region is divided by the method for designing a semiconductor integrated circuit according to the present invention.

FIG. 4 is a layout explanatory view showing a state after arrangement of basic cells and functional modules is completed by the method for designing a semiconductor integrated circuit according to the present invention.

FIG. 5 is a layout explanatory view showing a state after the basic cells are spread and before the functional module position is finely adjusted.

FIG. 6 is a layout explanatory view showing a state after fine adjustment of the functional module position.

[Explanation of symbols]

 1 Basic cell placement area M1, M2 Functional module B1, B2 Division area BC Basic cell BL1, BL2 Border line I / O Input / output buffer cell

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuo Kato 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Division

Claims (6)

[Claims] 1. A size of a basic cell placement area in which a basic cell is placed is provisionally determined, and a functional module is placed at an arbitrary position in the basic cell placement area. A method of designing a semiconductor integrated circuit, characterized in that the basic cell arrangement region is divided by a straight line including any two opposite sides, and the basic cells are spread in each divided region. 2. After laying basic cells in the divided areas, it is determined whether or not each functional module overlaps with a basic cell arranged in the periphery thereof and violation of a proximity rule, and the basic cells are defined as basic cells on three or more sides of the functional module. When overlapping or violating the proximity rule, at least any two sides orthogonal to each other are finely adjusted in the arrangement position of the functional module so that the two sides coincide with the boundary line of the basic cell. The method for designing a semiconductor integrated circuit according to claim 1. 3. After the basic cells are spread over the divided areas, the sum of the basic cells spread over the divided areas is calculated, and it is determined whether or not the required number is satisfied. 3. The method for designing a semiconductor integrated circuit according to claim 1, wherein the basic cell arrangement area is expanded according to the amount, and the functional modules are arranged and the basic cells are spread according to the procedure again. 4. When the lengths of the basic cell in the vertical direction and the horizontal direction are different, the longitudinal direction of the basic cell and the dividing direction of the basic cell arrangement region are made to coincide with each other. Item 4. A method for designing a semiconductor integrated circuit according to item 1, 2 or 3. 5. A basic cell of a different type is spread over each of the divided areas.
2. A method for designing a semiconductor integrated circuit according to 2, 3 or 4. 6. A semiconductor integrated circuit in which a plurality of basic cells are laid out in a tile shape on a semiconductor chip, and a functional module is disposed in a part of the basic cells. A semiconductor integrated circuit characterized in that the extension lines of the two sides coincide with any of the boundary lines of the basic cell.