JP2001306641A - Automatic arranging and wiring method for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that when two kinds of LSI layouts differing in wiring grid interval are combined, a nonconnection part is formed between a terminal and a wire to bring about the need to manually arrange a wire at the nonconnection part and there is the possibility of a long time needed for the layouts, large time loss, and an increase in chip area when the layouts are adjusted to one wiring grid interval. SOLUTION: Terminals 16 and 17 having x-directional length (x2+(L/2)) and y-directional length (y2+(L/2)) are arranged. Wires 11 and 12 of a necessary microblock are arranged along a wiring grid 10 and then wires 14 and 15 are automatically wired along a wiring grid 13 on a chip. When the terminals 16 and 17 are viewed on the wiring grid 13 of a higher chip, more than one wiring grid is crossed in the x direction and y direction without fail, so the wires 14 and 15 on the chip are connected to the wires 11 and 12 of the microblock through the terminals 16 and 17 without fail.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for automatically arranging and routing semiconductor integrated circuits, and more particularly to a computer aided design (C
AD) system for large-scale semiconductor integrated circuits (LS)
The present invention relates to a method for automatically arranging and routing semiconductor integrated circuits for designing layout I).

[0002]

2. Description of the Related Art When designing an LSI layout using a CAD system, for example, basic cells corresponding to logic gates such as NAND and NOR are arranged on an LSI chip, and wiring between the basic cells is arranged in a grid. Automatic placement along the grid is performed. In addition to the basic cells, there are cells such as a combination of transistors and resistors.

Also, wiring patterns for realizing several types of logical function units (blocks) such as gates and flip-flops, which are constructed using several basic cells, are designed in advance in layout and prepared as a library. Then, a necessary block wiring pattern is called from this library, and the blocks are automatically arranged and automatically wired.

[0004]

However, in recent years, LS
Various memories, multipliers, and AL
U and macro blocks such as CPU peripheral circuits have also been mounted on a single chip together with logic circuits. However, grid spacing in layout design differs for each technology due to differences in manufacturing processes. If one macro block is mounted on a chip for a logic circuit of another technology as it is, the grid intervals are different from each other, and automatic placement and wiring cannot be performed as it is.

For example, as shown in FIG. 4, when a macro block 1 is mounted on a chip 2 having a pattern outside the macro block 1, the wiring grid 3 of the macro block 1 and the wiring grid 4 of the chip 2 The grid spacing is different due to the difference in technology between each other. In this case, since the layout between the different grids cannot be basically performed by the automatic placement and routing, an unconnected portion is generated between the automatic wiring 5 arranged on the wiring grid 4 of the chip 2 and the terminal of the macro block 1. There is a problem that the wiring 6 must be manually arranged in the unconnected portion.

For automatic placement and wiring, the macro block 1 is automatically placed so that its wiring grid 8 has the same grid interval as the wiring grid 4 of the chip 2 as shown in FIG. It is also conceivable to use it after rewiring. However, in this case, the wiring grid of the macro block 1 cannot be used, and the work of correcting the cell layout, the layout of the macro block, and the like is required. In some cases, the chip area may increase.

[0007] The present invention has been made in view of the above points,
It is an object of the present invention to provide a method of automatically arranging and wiring a semiconductor integrated circuit which can easily combine a plurality of layouts having different wiring grid intervals and lay out the layout in a short time.

Another object of the present invention is to provide an automatic layout and wiring method for a semiconductor integrated circuit which can easily perform automatic layout and wiring at a wiring grid interval different from that of an existing layout using existing layout data. Is to provide.

[0009]

According to the present invention, in order to achieve the above object, after arranging macroblocks and terminals and performing desired first wiring along a first wiring grid, the grid spacing is determined. Is a method of automatically arranging and wiring a semiconductor integrated circuit for performing a desired second wiring including a wiring connected to at least the terminal along a second wiring grid which is equal to or larger than a grid interval of the first wiring grid, The distance x in the second wiring grid is larger than the distance in the x direction of the first wiring grid.
When the interval in the direction is longer, the length of the terminal in the x direction is set to a value which is larger than the interval in the x direction of the second wiring grid by 以上 or more times the wiring width of the second wiring. When the distance in the y direction of the second wiring grid is longer than the distance in the y direction of the first wiring grid, the length of the terminal in the y direction is set to the second distance in the y direction of the second wiring grid. 1 of wiring width of wiring
It is characterized in that the value is set to a value which is at least / 2 times larger and arranged.

According to the present invention, the length of the terminal of the lower macroblock in the x direction is 1/1 / the width of the second wiring in the x direction of the second wiring grid of the upper macroblock or chip. The length of the terminal of the lower macroblock in the y direction is set to be at least 倍 times the wiring width of the second wiring more than the interval of the second wiring grid in the y direction. Therefore, one or more terminals can cross the second wiring grid.

Here, the terminal is specifically set to a size of a length xp in the x direction and a length yp in the y direction.
The length xp is a distance x in the x direction of the second wiring grid.
2. When the interval in the y direction is y2 and the wiring width of the second wiring is L, and when the interval x2 is larger than the interval x1 of the first wiring grid in the x direction, {x2 + (L / 2)}. With the above length, when x2 = x1, the length is arbitrary, and the length y
p is the distance y2 in the y direction of the first wiring grid.
When it is larger than 1, the length is {y2 + (L / 2)} or more, and when y2 = y1, an automatic length is set as an arbitrary length.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a flowchart of an embodiment of a method for automatically arranging and wiring a semiconductor integrated circuit according to the present invention, and FIG. 2 shows an example of terminals and wiring laid out by the method of the present invention.

This embodiment will be described with reference to FIGS. As an example, it is assumed that macroblocks are first arranged and wired on a chip, and then wired as shown in FIG. 2 on a chip outside the macroblock (hereinafter, the above macroblock is referred to as a lower macro Block, the above chip is also referred to as an upper chip).

In FIG. 2, the wiring grid 10 of the lower macroblock has a grid spacing (length) of x1 in the x direction and a grid spacing (length) of y1 in the y direction. The width of 12 is L '. On the other hand, the wiring grid 13 of the upper chip has a grid spacing (length) of x2 in the x direction and a grid spacing (length) of y2 in the y direction.
And the width of the wirings 14 and 15 is L. As a premise of automatic placement and routing in this embodiment, x1 ≦ x
2. It is assumed that y1 ≦ y2.

Returning to FIG. 1, when layout is performed by CAD, information on a wiring grid of chips and macro blocks, position information of macro blocks to be arranged, wiring information, and the like are stored in a storage device (not shown). Are stored in advance. The layout device fetches the pattern data from the storage device (step S
1) It is determined whether the length x2 of the wiring grid of the chip in the x direction is longer than the length x1 of the wiring grid of the macroblock in the x direction (step S2). The length xp is set to a value satisfying the following inequality: xp ≧ x2 + (L / 2) (step S3).
Here, L in the expression (1) is the width of the wirings 14 and 15 on the chip shown in FIG.

On the other hand, when the condition of x2> x1 is not satisfied, x2 = x1. In this case, the length x1 of the macro grid wiring grid in the x direction is equal to the length x2 of the chip wiring grid x2. Since they are equal, the length of the macroblock terminal in the x direction is set to an arbitrary length (step S4).

Subsequently, it is determined whether or not the length y2 of the wiring grid of the chip in the y direction is longer than the length y1 of the wiring grid of the macroblock in the y direction (step S5). The length yp in the y direction is set to a value that satisfies the following inequality: yp ≧ y2 + (L / 2) (step S6).

On the other hand, when the condition of y2> y1 is not satisfied, y2 = y1. In this case, the length y2 of the wiring grid of the macroblock in the y direction is equal to the length y1 of the wiring grid of the chip in the y direction. Since they are equal, the length of the terminal of the macroblock in the y direction is set to an arbitrary length (step S7).

After the processing in step S6 or S7, the length in the x direction set in step S3 or S4
The terminal of the macroblock having the length in the y direction set in 6 or S7 is arranged together with the macroblock on the chip (step S8). In FIG. 2, as the terminals, the length in the x direction {x2 + (L / 2)} and the length in the y direction {y2 + (L
/ 2) Terminals 16 and 17 of｝ are arranged.

Subsequently, the wiring grid 1 of the macro block
The wiring of the required macroblocks along 0 is arranged as shown at 11 and 12 in FIG. 2 and then automatically routed on the chip along the wiring grid 13 of the chip as shown at 14 and 15 in FIG. (Step S9).

In this embodiment, when the terminals 16 and 17 are viewed from the wiring grid 13 of the upper chip, they always become 1
Since more than one wiring grid crosses both the x direction and the y direction, the wirings 14 and 15 on the chip
17 are always connected to the wirings 11 and 12 of the macro block.

Next, the operation and effect of this embodiment will be described.
This will be described in more detail with reference to FIG. The wiring grid 10 of the macro block and the wiring grid 13 of the chip have different lengths (grid intervals) in the x direction and the y direction due to the difference in technology as described above, and as shown in FIG. After arranging the terminals 19 and 20 in the macro block and performing the wirings 11 and 12 connected thereto, the wiring on the chip connected to the terminals 19 and 20 of this macro block is automatically arranged along the wiring grid 13 conventionally. Since the sizes of the terminals 19 and 20 are determined corresponding to the wiring grid 10, when the wiring grid 10 is smaller than the wiring grid 13, unconnected wires such as 23 shown in FIG. As shown, a design rule error with a very narrow wiring width may occur.

On the other hand, in the present embodiment, the size of the terminal of the macroblock in the x direction is set to a value that satisfies the inequality expression (1), and the size in the y direction is the inequality expression (2). 3 is set to a value that satisfies
As shown in (B), terminals 25 and 2 of the macroblock
6 is larger in size than the wiring grid 13, so that the wiring 21 on the chip is connected to the terminal 25,
The wiring 22 on the chip is connected to the terminal 26.

Therefore, unlike the related art, the manual wiring of the unconnected portion can be eliminated, so that the time for the layout work and the like can be reduced, and the conventional layout data can be used. Furthermore, there is no need to automatically re-arrange the wiring grid of the lower macro block so as to have the same grid interval as the wiring grid of the upper chip.
There is no need to correct the cell layout, the layout of the macro blocks, and the like, and the chip area can be reduced in some cases.

The present invention is not limited to the above-described embodiment. For example, the present invention can be applied to a case where wiring is performed between a higher-order macroblock and a lower-order macroblock instead of a higher-order chip. The present invention is applicable to various LSIs other than the array LSI.

[0026]

As described above, according to the present invention,
The length of the terminal of the lower macroblock in the x direction and the length of the y direction is set to １ ／ of the wiring width of the wiring of the macroblock or chip higher than the spacing in each direction of the wiring grid of the upper macroblock or chip. By making it more than twice as large,
Since the terminal of the lower macroblock crosses at least one wiring grid of the upper macroblock or the chip, the second wiring can be connected to the terminal without fail.
Unlike the related art, manual wiring of an unconnected portion can be omitted, so that the time for layout work and the like can be reduced.

Further, according to the present invention, there is no need to change the arrangement and wiring of the macro blocks, so that the existing layout data can be used as it is.

Further, according to the present invention, it is not necessary to automatically re-arrange the first wiring grid of the lower macro block so as to have the same grid interval as the second wiring grid. It is not necessary to correct the block layout and the like.

Further, according to the present invention, since only the outer shape of the terminal is changed, the chip area can be reduced in some cases.

[Brief description of the drawings]

FIG. 1 is a flowchart of an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship among terminals, wiring, and a wiring grid according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram of the operation and effect of the embodiment of the present invention.

FIG. 4 is an explanatory diagram of wiring according to an example of a conventional method.

FIG. 5 is an explanatory diagram of wiring according to another example of the conventional method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Wiring grid of macroblock 11, 12 Wiring of macroblock 13 Wiring of chip 14, 15, 21, 22 Wiring of chip 16, 17, 25, 26 Terminal of macroblock by the method of the present invention 19, 20 Macro by conventional method Block terminal 23 Unconnected part 24 Design rule error

Claims (2)

[Claims] After arranging macroblocks and terminals and performing desired first wiring along a first wiring grid, a second grid having a grid spacing equal to or greater than the grid spacing of the first wiring grid is provided. A method for automatically arranging and routing a semiconductor integrated circuit that performs a desired second wiring including a wiring connected to at least the terminal along a wiring grid, the method comprising: 2
When the spacing in the x direction of the wiring grid is longer, the length of the terminal in the x direction is at least 1/2 times the wiring width of the second wiring as compared with the spacing in the x direction of the second wiring grid. If the distance in the y direction of the second wiring grid is longer than the distance in the y direction of the first wiring grid, the length of the terminal in the y direction is set to the second value. The wiring width of the second wiring is set to 1
A method for automatically arranging and routing semiconductor integrated circuits, wherein the semiconductor integrated circuit is arranged and set to a value which is at least twice as large. 2. The terminal is set to have a size of a length xp in the x direction and a length yp in the y direction, wherein the length xp is a distance between the second wiring grid in the x direction and x2. Where y2 is the width of the second wiring and L is the width of the second wiring, the distance x2 is the distance x in the x direction of the first wiring grid.
When it is larger than 1, the length is {x2 + (L / 2)} or more, and when x2 = x1, it is an arbitrary length. The length yp is such that the interval y2 is equal to y of the first wiring grid. When the distance y in the direction is larger than y1, the distance Δy2 + (L /
2) The automatic placement and routing method for a semiconductor integrated circuit according to claim 1, wherein when the length is not less than｝ and y2 = y1, the length is automatically set to an arbitrary length.