JP2000057175A - Automatic wiring method for semiconductor integrated circuit devices - Google Patents

Abstract

(57) [Summary] (with correction) [PROBLEMS] To automatically wire terminals of two functional blocks without generating a capacitance between the terminals of a circuit unit in an intermediate functional block. SOLUTION: Layout data of each functional block is stored in a database, and a mask layout layer of rectangular data C defining a wiring prohibited area in an intermediate functional block is stored in the database. The CPU reads the arrangement information, terminal information, and wiring rules of each functional block from the database, and connects the terminals A and A 'to be connected between the two functional blocks and B and B' in accordance with the information and rules. The routes of all the virtual wires that can be routed are generated, the virtual wires in the routing prohibited area specified by the rectangular data C are excluded, and the wiring distance becomes the shortest from the route of the remaining excluded virtual wires. Calculate the route and perform automatic wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for automatically wiring terminals of two functional blocks in a semiconductor integrated circuit device via another functional block between the two functional blocks. In the present specification, the expressions “wiring” and “connection” do not mean wiring and connection in a physical sense, but are premised on performing such physical connection. This is used to mean "acquire data."

[0002]

2. Description of the Related Art In recent years, as devices have become smaller and more sophisticated, it has been demanded that many functions required of the devices be realized by a single-chip semiconductor integrated circuit. 2. Description of the Related Art A semiconductor integrated circuit in which many functions are integrated into one chip is required to operate at high speed with the advancement of functions of a device, and the scale of the device is also increasing.
In such a background, connection and wiring between functional blocks constituting a semiconductor integrated circuit are automatically performed using a computer-aided design (CAD) system. Since the increase in the chip area due to the inter-wiring region is greatly affected, this is one important issue in realizing a semiconductor integrated circuit.

FIG. 25 is a block diagram showing a configuration of a conventional automatic wiring system of a semiconductor integrated circuit device.
Reference numerals 2 and 103 denote databases, 104 denotes a CPU (central processing unit), 105 denotes an external input device such as a keyboard and a mouse, and 106 denotes a data bus. A ROM storing a program for control and calculation by the CPU.
(Read only memory) and a RAM (random access memory) for assisting control and calculation and storing data are not shown.

[0004] The database 101 stores the arrangement information of functional blocks, and has information such as where the functional blocks constituting the semiconductor integrated circuit are arranged on the semiconductor integrated circuit. The database 102 stores terminal information. The database 102 stores information such as the position of each terminal of each functional block and the terminal to which each terminal is connected to another functional block. It has priority information such as which terminal to connect and connect. The database 103 stores wiring rules. The database 103 stores information defining wiring layers used in the X direction and wiring layers used in the Y direction for connecting and wiring between functional blocks, and the widths and widths of the wiring layers in the X direction and the Y direction. It consists of information defining intervals, information defining the size of via holes connecting and connecting the wiring layers in the X direction and the wiring layers in the Y direction, and the positional relationship between the wiring layers and the via holes. In this example, the wiring layer in the X direction is defined by a two-layer wiring (second-layer wiring), and the wiring layer in the Y direction is defined by a three-layer wiring (third-layer wiring).

[0005] The CPU 104 transmits the arrangement information of the database 101 and the database 1 via the data bus 106.
It has a function of reading the terminal information 02 and the wiring rules of the database 103 and automatically connecting and wiring the terminals of the functional blocks.

FIG. 26 shows functional blocks 121, 122, 1
23 is a schematic diagram of a semiconductor integrated circuit including 23. The function block 121 has a terminal A and a terminal B, and the function block 12
3 has a terminal A 'and a terminal B', and the terminal A
And the terminal A ′ are connected and connected, and the terminal B and the terminal B ′ are connected and connected. The terminals A and B on the functional block 121 side and the terminals A ′ and B ′ on the functional block 123 side are upside down. The function blocks 121, 122,
The wiring in 123 is designed as a single-layer wiring.

The operation of the CPU 104 is controlled by the external input device 10
It starts based on the input from 5. The function of the CPU 104 will be described with reference to FIG. FIG. 27 shows C
5 is a flowchart illustrating a process performed by a PU 104. The processing is started in order from step 111 based on the input from the external input device 105. In step 111, arrangement information of each functional block is read from the database 101. In step 112, terminal information is read from the database 102. At step 113, the wiring rules are read from the database 103.

Steps 114 to 116 correspond to step 11
This is a step of connecting and wiring each terminal based on the information and rules read by 1, 112 and 113, which will be described with reference to FIGS. In step 114, in accordance with the wiring rules read in step 113, all routes that allow connection wiring between the terminal A and the terminal A 'and between the terminal B and the terminal B' are generated as virtual wiring. FIG. 28 is a schematic diagram of the virtual wiring in step 114. Two-layer wiring data is virtually generated in the X direction from each of the terminals A, A ', B, and B' to be connected between the functional block 121 and the functional block 123. Next, step 113
In accordance with the wiring rules of the database 103 read in step (1), a plurality of two-layer wiring data are virtually generated in a direction parallel to the virtually generated two-layer wiring data. Furthermore, a plurality of three-layer wiring data are virtually generated in the direction orthogonal to the two-layer wiring data according to the wiring rule of the database 103. In FIG. 28, virtual two-layer wiring data is indicated by a horizontal broken line on the lower surface side of the functional block 122, and virtual three-layer broken line data is indicated by a vertical solid line on the upper surface side.

In step 115, the aforementioned step 114
Is calculated from the virtual wiring data generated in step 112 in accordance with the connection order in the terminal information read in step 112. In this example, it is assumed that the connection between the terminal A and the terminal A ′ is defined as the first place, and the connection between the terminal B and the terminal B ′ is defined as the second place. First, from the wiring route virtually generated in step 114, the terminal A
And a wiring route for connecting and wiring the terminal A ′ with the shortest distance is arbitrarily calculated and determined. Next, a wiring path for connecting and wiring the terminal B and the terminal B ′ with the shortest distance except for the wiring path used for the connection wiring between the terminal A and the terminal A ′ is arbitrarily calculated and determined.

In step 116, the above-mentioned step 115
29, two-layer wiring data along the X-direction and three-layer wiring data along the Y-direction are generated, as shown in the schematic diagram of FIG. Via hole data is generated at the intersection based on the wiring rules of the database 103 read in step 113. In FIG. 29, via holes are indicated by black dots. The four terminals A, A ', B, B' are all located on the second layer. First, a path extends in the X direction as a two-layer wiring (broken line) from the terminal A, a path extends in the Y direction as a three-layer wiring (solid line) through a via hole, and further as a two-layer wiring (dashed line) through the via hole. The path extends in the X direction and is connected to the terminal A ′. Similarly, a path extends from terminal B in the X direction as a two-layer wiring (broken line), a path extends in the Y direction as a three-layer wiring (solid line) via a via hole, and a two-layer wiring ( The path extends in the X direction (broken line) and is connected to the terminal B ′. The Y-direction portion in the wiring route between the terminal B and the terminal B 'three-dimensionally intersects the X-direction portion in the wiring route between the terminal A and the terminal A'. The reason why the portion in the Y direction in the wiring path of the terminals A and A ′ is formed as a three-layer wiring via a via hole is to avoid a short circuit with another wiring not shown.

In this conventional automatic wiring method, as shown in FIG. 29, the connection wiring between the function block 121 and the function block 123 arranged with the function block 122 interposed therebetween is performed on the function block 122. Wiring can be performed at the shortest distance, wiring delay can be suppressed, and connection wiring can be realized in which the area of only the connection wiring is not required and the increase in area is suppressed.

[0012]

However, in the above-described conventional automatic wiring system, the function block 121 is used.
The wiring that connects and connects the function block 123 and the function block 123 causes a capacitance between the wiring and the wiring (not shown) in the function block 122 that passes thereunder. Therefore, the function block 121
When the wiring that connects and connects the function block 123 and the wiring transitions, the wiring in the functional block 122 below the wiring may be affected by noise due to coupling, causing a malfunction, or the capacity of the wiring in the functional block 122 may be changed. Is increased more than expected, causing a malfunction due to a signal delay.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to enable automatic wiring without generating a capacitance between the wiring of a circuit portion itself in a functional block.

[0014]

In an intermediate functional block, an area where a signal delay or a malfunction may occur when a wiring passes through an upper layer is known in advance. Therefore, in the automatic wiring method of the semiconductor integrated circuit device according to the present invention, by preparing the wiring prohibition information for designating the wiring prohibition area, and incorporating the wiring prohibition information into the automatic wiring flow, Automatic wiring is performed in the area excluding the wiring prohibited area. As a result, the connection wiring between the distant function block terminals does not generate a capacitance that causes a signal delay with the wiring of the circuit unit itself in the function block, and also malfunctions due to the influence of noise due to coupling. Does not occur.

[0015]

According to the first aspect of the present invention, there is provided an automatic wiring method for a semiconductor integrated circuit device, wherein terminals of two functional blocks are automatically wired via another functional block between these two functional blocks. A wiring prohibition information for setting a wiring prohibition area in the another functional block, and excluding a virtual wiring in the wiring prohibition area based on the wiring prohibition information among virtual wirings appearing during automatic wiring. Then, automatic wiring is performed based on the remaining virtual wiring data. As a result, automatic wiring can be performed between the terminals of the two separate functional blocks without generating a capacitance between the terminals of the circuit unit itself in the functional blocks.

According to a second aspect of the present invention, there is provided an automatic wiring system for a semiconductor integrated circuit device, wherein terminals of two functional blocks are automatically wired via another functional block between the two functional blocks. In addition, rectangular data that defines a wiring prohibited area in the another functional block is set, and virtual wiring in the wiring prohibited area based on the rectangular data is excluded from virtual wiring appearing during automatic wiring, and the remaining virtual wiring data is set. Is configured to perform automatic wiring based on the Rectangular data may be set in order to determine, as a wiring prohibited area, an area where a signal delay or malfunction may occur if wiring passes through an upper layer in an intermediate functional block. As a result, automatic wiring is performed between the terminals of the two separate functional blocks without generating a capacitance between the terminals of the circuit unit itself in the functional blocks.

According to a third aspect of the present invention, there is provided an automatic wiring system for a semiconductor integrated circuit device, wherein terminals of two functional blocks are automatically wired via another functional block between the two functional blocks. Setting a cell data name corresponding to the cell data defining the wiring prohibited area in the another functional block, and excluding the virtual wiring in the wiring prohibited area based on the cell data name among the virtual wirings appearing during the automatic wiring. Then, automatic wiring is performed based on the remaining virtual wiring data. If an area where signal delay or malfunction may occur if wiring passes through the upper layer in an intermediate functional block is defined as a wiring prohibited area, if a cell data name corresponding to the cell data in that area is set Good. As a result, automatic wiring is performed between the terminals of the two separate functional blocks without generating a capacitance between the terminals of the circuit unit itself in the functional blocks.

According to a fourth aspect of the present invention, there is provided an automatic wiring system for a semiconductor integrated circuit device, wherein terminals of two functional blocks are connected to a ROM or a RAM between the two functional blocks.
This is a method in which wiring is automatically performed via a memory function block having a function, in which a region of a memory cell array section in the memory function block and a direction of a bit line in the memory cell array section are set, and virtual lines appearing during automatic wiring are set. The configuration is such that, of the wirings, virtual wirings parallel to the bit line direction in the memory cell array section are excluded, and automatic wiring is performed based on the remaining virtual wiring data. In order to define a signal line area that may cause a signal delay or malfunction due to an increase in bit line capacity when a wiring passes through an upper layer in an intermediate memory functional block, a memory cell array area and this memory are used. The direction of the bit line in the cell array may be set. As a result, automatic wiring is performed between the terminals of the two separate functional blocks without generating a capacitance between the terminals of the circuit unit itself in the functional blocks.

According to a fifth aspect of the present invention, there is provided an automatic wiring system for a semiconductor integrated circuit device, wherein terminals of two functional blocks are automatically wired via another functional block between the two functional blocks. A signal line name corresponding to signal line data defining a wiring prohibited area in the another functional block is set, and a virtual wiring in the wiring prohibited area based on the signal line name among virtual wirings appearing during automatic wiring is set. The configuration is such that automatic wiring is performed based on the remaining virtual wiring data. To define a region where signal delay or malfunction may occur if wiring passes through the upper layer in an intermediate functional block as a wiring prohibited region, set the signal line name corresponding to the signal line data in that region. I just need. As a result, automatic wiring is performed between the terminals of the two separate functional blocks without generating a capacitance between the terminals of the circuit unit itself in the functional blocks.

An automatic wiring system for a semiconductor integrated circuit device according to a sixth aspect of the present invention has the following configuration. A method of automatically wiring terminals of two functional blocks via another functional block between the two functional blocks, wherein a means for storing arrangement information of each functional block, and a terminal position of the two functional blocks And means for storing terminal information about the terminal of the connection destination, means for storing wiring rules of via holes for connecting and wiring a wiring layer for connecting and wiring between functional blocks and a wiring layer different therefrom,
Means for storing rectangular data defining a wiring prohibition area in the another functional block, and routes of all virtual wiring that can be connected and wired between terminals to be connected between the two functional blocks in accordance with the information and rules. Means for generating, a means for excluding the virtual wiring in the wiring prohibition area specified by the rectangular data from the path of the generated virtual wiring, and a wiring distance from the path of the remaining virtual wiring which has been excluded. Means for calculating the shortest path. Rectangular data may be set in order to determine, as a wiring prohibited area, an area where a signal delay or malfunction may occur if wiring passes through an upper layer in an intermediate functional block. As a result, automatic wiring is performed between the terminals of the two separate functional blocks without generating a capacitance between the terminals of the circuit unit itself in the functional blocks.

An automatic wiring system for a semiconductor integrated circuit device according to a seventh aspect of the present invention has the following configuration. A method of automatically wiring terminals of two functional blocks via another functional block between the two functional blocks, wherein a means for storing arrangement information of each functional block, and a terminal position of the two functional blocks And means for storing terminal information about the terminal of the connection destination, means for storing wiring rules of via holes for connecting and wiring a wiring layer for connecting and wiring between functional blocks and a wiring layer different therefrom,
Means for storing a cell data name designating cell data defining a wiring prohibited area in said another functional block;
Means for generating paths of all virtual wirings that can connect and connect the terminals to be connected of one functional block in accordance with the information and rules, and wherein the cell data name is obtained from the generated virtual wiring paths. There are provided means for excluding the virtual wiring in the wiring prohibition area corresponding to the designated cell data, and means for calculating a path having the shortest wiring distance from the path of the remaining virtual wiring excluded. If an area where signal delay or malfunction may occur if wiring passes through the upper layer in an intermediate functional block is defined as a wiring prohibited area, if a cell data name corresponding to the cell data in that area is set Good. As a result, the distance 2
Automatic wiring is performed between the terminals of one functional block without generating a capacitance between the terminals of the circuit unit in the functional block.

The automatic wiring system for a semiconductor integrated circuit device according to claim 8 of the present invention has the following configuration. A method of automatically wiring terminals of two functional blocks via a memory functional block having a ROM or RAM function between the two functional blocks, wherein a means for storing arrangement information of each functional block; Means for storing terminal information about terminal positions and connection destination terminals of the functional blocks, means for storing wiring rules for via holes for connecting and wiring wiring layers for connecting and wiring between functional blocks, and wiring layers different therefrom, Means for storing the area of the memory cell array section in the memory functional block and the bit line direction in the memory cell array section, and connecting wiring between the terminals to be connected between the two functional blocks can be performed according to the information and rules. Means for generating paths for all virtual wirings, and the memory cell array from the generated virtual wiring paths. Parts and excluding unit bit line direction and parallel to the virtual line in the region of the remaining wiring distance from the path of the virtual wirings exclusion was made of the is provided with means for calculating the route the shortest. In order to define a signal line area that may cause a signal delay or malfunction due to an increase in bit line capacity when a wiring passes through an upper layer in an intermediate memory functional block, a memory cell array area and this memory are used. The direction of the bit line in the cell array may be set. As a result, the distance 2
Automatic wiring is performed between the terminals of one functional block without generating a capacitance between the terminals of the circuit unit in the functional block.

An automatic wiring system for a semiconductor integrated circuit device according to a ninth aspect of the present invention has the following configuration. A method of automatically wiring terminals of two functional blocks via another functional block between the two functional blocks, wherein a means for storing arrangement information of each functional block, and a terminal position of the two functional blocks And means for storing terminal information about the terminal of the connection destination, means for storing wiring rules of via holes for connecting and wiring a wiring layer for connecting and wiring between functional blocks and a wiring layer different therefrom,
Means for storing a signal line name of a signal line corresponding to a wiring prohibited area among signal lines in said another functional block;
Means for generating paths of all virtual wirings capable of connecting and wiring terminals to be connected between the three functional blocks in accordance with the information and rules, and wherein the signal line names are obtained from the generated virtual wiring paths. There are provided means for excluding the virtual wiring in the wiring prohibition area corresponding to the designated signal line, and means for calculating a path having the shortest wiring distance from the remaining virtual wiring excluded. To define a region where signal delay or malfunction may occur if wiring passes through the upper layer in an intermediate functional block as a wiring prohibited region, set the signal line name corresponding to the signal line data in that region. I just need. As a result, automatic wiring is performed between the terminals of the two separate functional blocks without generating a capacitance between the terminals of the circuit unit itself in the functional blocks.

Hereinafter, a specific embodiment of an automatic wiring system for a semiconductor integrated circuit device according to the present invention will be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of an automatic wiring system of a semiconductor integrated circuit device according to Embodiment 1 of the present invention.
Reference numerals 2 and 103 denote databases, 104 denotes a CPU (central processing unit), 105 denotes an external input device such as a keyboard and a mouse, and 106 denotes a data bus. A ROM storing a program for control and calculation by the CPU.
(Read only memory) and a RAM (random access memory) for assisting control and calculation and storing data are not shown. As in the case of the above-described conventional automatic wiring method, the database 101 stores the arrangement information of the functional blocks, and the position of each functional block constituting the semiconductor integrated circuit on the semiconductor integrated circuit is determined. With such information. Database 10
Reference numeral 2 denotes a terminal information storage unit that stores information such as the position of each terminal of each functional block, the terminal to which each terminal is connected to another functional block, and which of a plurality of wirings to be connected and connected. It has priority information such as whether to connect and connect from the wiring between terminals. The database 103 stores wiring rules. The database 103 stores information defining wiring layers used in the X direction and wiring layers used in the Y direction for connecting and wiring between functional blocks, and the widths and widths of the wiring layers in the X direction and the Y direction. It consists of information defining intervals, information defining the size of via holes connecting and connecting the wiring layers in the X direction and the wiring layers in the Y direction, and the positional relationship between the wiring layers and the via holes.
The wiring layer in the X direction is defined by the second layer wiring, and the wiring layer in the Y direction is defined by the third layer wiring. The database 11 stores layout data of each functional block constituting the semiconductor integrated circuit device. The database 12 stores a mask layout layer (wiring prohibition information) that prohibits connection wiring between functional blocks described later. C
The PU 104 reads the arrangement information of the database 101, the terminal information of the database 102, and the wiring rules of the database 103 via the data bus 106, reads the layout data of each functional block from the database 11, and reads the rectangular data C from the database 12. It has a function of reading the mask layout layer, performing wiring prohibition processing as described later, and automatically connecting and wiring between terminals of the functional blocks.

FIG. 2 is a schematic diagram of a semiconductor integrated circuit according to the first embodiment, which is composed of the same functional blocks 121, 122, and 123 as in FIG. 26 of the conventional example, and has the same terminal and wiring definitions as in FIG. However, inside the functional block 122, wiring is prohibited by a mask layout layer of rectangular data C provided to include a circuit part that may cause a malfunction when the connection wiring between the functional blocks passes through the upper layer. The area (hatched area) is newly set.

The function of the CPU 104 according to the first embodiment will be described with reference to FIG. Figure 3 shows the CPU
4 is a flowchart illustrating a process performed by the control unit 104. As in the case of the conventional example, the processes are sequentially started from step 111 based on the input from the external input device 105. In step 111, arrangement information of each functional block is read from the database 101. In step 112, the database 1
02 is read from the terminal information. At step 113, the wiring rules are read from the database 103. Step 11
In step 4, according to the wiring rules read in step 113, terminals A and A 'and all the routes that allow connection between terminal B and terminal B' are generated as virtual wiring (see FIG. 4). ).

In step 14, the layout data of each functional block is read from the database 11. In step 15, the mask layout layer of the rectangular data C is read from the database 12. In step 16, the layout and area of the rectangular data C defining the wiring prohibited area on the semiconductor integrated circuit are detected based on the layout data read in step 14 and the mask layout layer read in step 15. FIG. 4 is a schematic diagram of the virtual wiring up to step 16.

In step 17, a portion included in the rectangular data C corresponding to the wiring prohibited area detected in step 16 is excluded from the wiring route from the wiring route virtually generated in step 114. FIG. 5 is a schematic diagram showing a state in which it is excluded. In FIG. 4, among the virtual wirings in the X and Y directions, some virtual wirings in the X and Y directions displayed in the wiring prohibition area indicated by the rectangular data C are deleted in FIG.

In step 115, step 114
From the remaining virtual wiring data excluded in step 17 from the virtual wiring data generated in step, a route for connecting and wiring with the shortest distance is calculated according to the connection order of the terminal information read in step 112. In this example, it is assumed that the connection between the terminal A and the terminal A ′ is defined as the first place, and the connection between the terminal B and the terminal B ′ is defined as the second place. First, a wiring route for connecting and wiring the terminal A and the terminal A ′ with the shortest distance is arbitrarily calculated and determined from the wiring route based on the remaining virtual wiring data. Next, a wiring path for connecting and wiring the terminal B and the terminal B ′ with the shortest distance except for the wiring path used for the connection wiring between the terminal A and the terminal A ′ is arbitrarily calculated and determined.

Step 18 is a step of judging whether or not the connection wiring route has been calculated or not as a result of step 115. If the connection wiring path could not be calculated, the processing is temporarily stopped and the arrangement of the functional blocks is changed. After that, the processing needs to be performed again from START (step 111).

In step 116, the above-mentioned step 115
As shown in the schematic diagram of FIG. 6, two-layer wiring data along the X-direction and three-layer wiring data along the Y-direction are generated according to the wiring path calculated in the step (b). Via hole data (see black dots) is generated at the intersection based on the wiring rules of the database 103 read in step 113. The four terminals A, A ',
Both B and B 'are located in the second layer. First, a path extends from the terminal A in the X direction as a two-layer wiring (broken line) to a three-layer wiring (solid line) via a via hole. This three-layer wiring is a wiring prohibited area (hatched part) indicated by rectangular data C. ), The path extends in the Y direction, and further extends as a two-layer wiring (broken line) in the X direction via a via hole, and is connected to the terminal A ′. Similarly, a path extends from the terminal B to a position avoiding the wiring prohibited area indicated by the rectangular data C along the X direction as a two-layer wiring (broken line), and a three-layer wiring (solid line) in the Y direction via a via hole. The path extends, and further extends in the X direction as a two-layer wiring (broken line) via the via hole, and is connected to the terminal B ′. The Y-direction portion in the wiring route between the terminal A and the terminal A 'three-dimensionally intersects the X-direction portion in the wiring route between the terminal B and the terminal B'. The reason why the portion in the Y direction in the wiring path of the terminals B and B 'is formed as a three-layer wiring via a via hole is to avoid a short circuit with another wiring not shown. The function block 1
The terminals A and B on the 21 side and the terminals A ′ and B ′ on the functional block 123 are in an up-down relationship.

According to the first embodiment, rectangular data for inhibiting connection wiring in the upper layer is input into the function block, and the wiring inhibition information based on the rectangular data is newly incorporated into the automatic wiring method, thereby achieving the function. When the upper layer becomes a wiring path inside the block, connection and wiring between functional blocks can be performed without excluding circuit parts that cause malfunction and performance degradation. Connection wiring becomes possible.

(Embodiment 2) FIG. 7 is a block diagram showing a configuration of an automatic wiring system of a semiconductor integrated circuit device according to Embodiment 2, which is different from the configuration of FIG. Instead, the configuration is such that a database 20 is added. The database 20 contains, for the cell data constituting the functional block, the cell data corresponding to the circuit section in the functional block which may malfunction if the connection wiring between the functional blocks passes through the upper layer. The name of the cell data is stored. That is, the cell data in the wiring prohibited area can be determined based on the designation of the cell data name. Other configurations are the same as those of the first embodiment (FIG. 1), and therefore, the same portions are denoted by the same reference characters and description thereof will not be repeated.

FIG. 8 is a schematic diagram of a semiconductor integrated circuit according to the second embodiment, which is composed of the same functional blocks 121, 122, and 123 as in FIG. 2 of the first embodiment. Same as 2. In the second embodiment, a rectangular wiring prohibition area provided inside the functional block 122 to include a circuit unit that may cause a malfunction when the connection wiring between the functional blocks passes through the upper layer. Is the cell data name D which is the name of the cell data.

The function of the CPU 104 according to the second embodiment will be described with reference to FIG. FIG. 9 shows the CPU
4 is a flowchart illustrating a process performed by the control unit 104. As in the case of the first embodiment, the processing is started in order from step 111 based on the input of the external input device 105. In step 111, arrangement information of each functional block is read from the database 101, in step 112 terminal information is read from the database 102, and in step 113 wiring rules are read from the database 103. Step 11
In step 4, in accordance with the wiring rule read in step 113, all the routes that allow connection between the terminals A and A 'and between the terminals B and B' are generated as virtual wiring (see FIG. 10). ).

In step 14, the layout data of each functional block is read from the database 11. In step 21, the cell data name D is read from the database 20. In step 22, based on the layout data read in step 14 and the cell data name D read in step 21, the arrangement and the area of the cell data of the wiring prohibited area on the semiconductor integrated circuit are detected. FIG. 10 shows step 2
FIG. 2 is a schematic diagram of virtual wiring up to 1.

In step 23, the part corresponding to the cell data indicated by the cell data name D corresponding to the wiring prohibited area detected in step 22 is excluded from the wiring path from the wiring path virtually generated in step 114. FIG. 11 is a schematic diagram showing a state in which it is excluded. In FIG. 10, among the virtual wirings in the X and Y directions, the cell data name D
In FIG. 11, some virtual wirings in the X and Y directions displayed in the wiring prohibition area indicated by are deleted.

In step 115, step 114
Then, from the remaining virtual wiring data excluded in step 23 from the virtual wiring data generated in step 23, a route for connecting and wiring with the shortest distance is calculated according to the connection order of the terminal information read in step 112. In this example, it is assumed that the connection between the terminal A and the terminal A ′ is defined as the first place, and the connection between the terminal B and the terminal B ′ is defined as the second place. First, a wiring route for connecting and wiring the terminal A and the terminal A ′ with the shortest distance is arbitrarily calculated and determined from the wiring route based on the remaining virtual wiring data. Next, a wiring path for connecting and wiring the terminal B and the terminal B ′ with the shortest distance except for the wiring path used for the connection wiring between the terminal A and the terminal A ′ is arbitrarily calculated and determined.

In step 18, it is determined whether or not the connection wiring route has been calculated or not as a result of step 115. If not, stop processing,
After taking measures such as changing the functional block arrangement, it is necessary to perform the processing again from START (step 111).

In step 116, step 115
As shown in the schematic diagram of FIG. 12, two-layer wiring data along the X-direction and three-layer wiring data along the Y-direction are generated in accordance with the wiring path calculated in the step (b). Via hole data (see black dots) is generated at the intersection based on the wiring rules of the database 103 read in step 113. The four terminals A, A ',
Both B and B 'are located in the second layer. First, a path extends in the X direction from the terminal A as a two-layer wiring (broken line) in the X direction, and continues to a three-layer wiring (solid line) via a via hole. This three-layer wiring is a wiring prohibited area (cell data name D). The path extends in the Y direction so as to avoid the hatched portion), and further extends in the X direction as a two-layer wiring (broken line) via a via hole, and is connected to the terminal A ′. Similarly, a path extends from the terminal B as a two-layer wiring (broken line) to a position avoiding the wiring prohibited area along the X direction, and a path extends in the Y direction as a three-layer wiring (solid line) via a via hole. Two-layer wiring via a via hole (broken line)
The path extends in the X direction and is connected to the terminal B ′. Others are the same as in the first embodiment.

According to the second embodiment, a cell data name for designating cell data is input to a circuit section in which connection wiring in an upper layer is prohibited inside a functional block, and wiring is prohibited by the cell data name. By incorporating new information into the automatic wiring method, it is possible to connect and connect functional blocks with the exception of circuit parts that may cause malfunctions and performance degradation if the upper layer becomes a wiring path inside the functional block Therefore, automatic connection wiring in consideration of the circuit operation of the functional block becomes possible.

(Embodiment 3) FIG. 13 is a block diagram showing a configuration of an automatic wiring system of a semiconductor integrated circuit device according to Embodiment 3, which differs from the configuration of FIG. 12 is removed, and a database 40 is added instead. The database 40 includes ROM, RA among functional blocks.
For storing memory function block information such as M
It has information on the arrangement and area of the memory function block 124 (see FIG. 14) on the semiconductor integrated circuit device, and information on the arrangement and bit line direction of the memory cell array section inside the memory function block. Other configurations are the same as those of the first embodiment (FIG. 1), and therefore, the same portions are denoted by the same reference characters and description thereof will not be repeated.

FIG. 14 is a schematic diagram of a semiconductor integrated circuit comprising a memory function block 124 and the same function blocks 121 and 123 as in FIG. 2 of the first embodiment. MEM is a memory cell array unit in which a plurality of memory cells are arranged in a matrix, and the bit line BL is connected to the memory cell array unit MEM.
In the case of the illustrated example, the upper layer crosses in the Y direction. The definitions of the terminals and wirings are the same as those in FIG.

The function of the CPU 104 according to the third embodiment will be described with reference to FIG. FIG. 15 shows C
5 is a flowchart illustrating a process performed by a PU 104. As in the case of the first embodiment, the processing is started in order from step 111 based on the input of the external input device 105. In step 111, arrangement information of each functional block is read from the database 101, and in step 112, terminal information is read from the database 102, and in step 113
Reads the wiring rules from the database 103. In step 114, in accordance with the wiring rule read in step 113, all routes that allow connection wiring between the terminal A and the terminal A 'and between the terminal B and the terminal B' are generated as virtual wiring (FIG. 16). reference).

At step 41, the memory function block 124 in the semiconductor integrated circuit device is
Of the memory cell array unit MEM in the memory function block 124, and the direction of the bit line BL. In step 42, the arrangement and area of the memory cell array unit MEM and the direction of the bit line BL on the semiconductor integrated circuit shown in FIG. 14 are detected based on the information in step 41. FIG. 16 is a schematic diagram of the virtual wiring up to step 42.

In step 43, the wiring parallel to the Y direction which is the direction of the bit line BL in the area of the memory cell array portion MEM on the semiconductor integrated circuit detected in step 42 from the wiring path virtually generated in step 114. Exclude routes. FIG. 17 is a schematic diagram showing a state in which it is excluded. In FIG. 16, among the virtual wirings in the X direction and the Y direction, some virtual wirings in the Y direction displayed along the direction of the bit line BL (Y direction) in the region of the memory cell array unit MEM are shown in FIG. Has been erased.

In step 115, step 114
From the virtual wiring data excluded in step 43 from the virtual wiring data generated in step 3, a route for connecting and wiring the shortest distance is calculated according to the connection order of the terminal information read in step 112. In this example, it is assumed that the connection between the terminal A and the terminal A ′ is defined as the first place, and the connection between the terminal B and the terminal B ′ is defined as the second place. First, a wiring route for connecting and wiring the terminal A and the terminal A ′ with the shortest distance is arbitrarily calculated and determined from the wiring route based on the remaining virtual wiring data. Next, a wiring path for connecting and wiring the terminal B and the terminal B ′ with the shortest distance except for the wiring path used for the connection wiring between the terminal A and the terminal A ′ is arbitrarily calculated and determined. In this case, it is possible to pass through the area of the memory cell array section MEM along the X direction, but is prohibited from passing through the area of the memory cell array section MEM along the Y direction.

In step 18, it is determined whether or not the connection wiring path has been calculated or not as a result of step 115. If not, stop processing,
After taking measures such as changing the functional block arrangement, it is necessary to perform the processing again from START (step 111).

In step 116, the above-mentioned step 115
As shown in the schematic diagram of FIG. 18, two-layer wiring data along the X direction and three-layer wiring data along the Y direction are generated in accordance with the wiring path calculated in the step (b). Via hole data (see black dots) is generated at the intersection based on the wiring rules of the database 103 read in step 113. The four terminals A, A ',
Both B and B 'are located in the second layer. First, a path extends from the terminal A in the X direction within the region of the memory cell array portion MEM as a two-layer wiring (broken line).
Since the three-layer wiring extends in the Y direction, the path extends in the Y direction so as to avoid the wiring prohibited area, which is the memory cell array portion MEM, and further extends through the second layer via via holes. A route extends in the X direction as a wire (broken line) and is connected to a terminal A ′. Similarly,
First, a path extends from the terminal B as a two-layer wiring (broken line) along the X direction to a position avoiding the wiring prohibited area as the memory cell array unit MEM, and a path in the Y direction as a three-layer wiring (solid line) via a via hole. At this time, the path extends in the Y direction so as to avoid the wiring prohibited area that is the memory cell array section MEM, and further extends through the via hole.
The path extends in the X direction as a layer wiring (broken line), and the terminal B ′
It is connected and wired to. Note that, in the wiring path connecting the terminal B and the terminal B ′, the wiring portion in the X direction indicated by the broken line may pass through the area of the memory cell array unit MEM. that is,
This is because the direction of the bit line BL is the Y direction.
Others are the same as in the first embodiment. When the direction of the bit line is the X direction, the entire area of the memory cell array unit MEM becomes a wiring prohibited area.

According to the third embodiment, the arrangement of the memory cell array section in the memory function block and the direction of the bit line in the memory cell array section are newly incorporated into the automatic wiring method as the wiring prohibition information. The connection wiring between the blocks does not pass in parallel on the bit lines in the functional blocks of the memory. Therefore, automatic wiring can be performed without increasing the bit line capacity, and automatic connection wiring can be performed in consideration of the circuit operation of the memory function block.

(Embodiment 4) FIG. 19 is a block diagram showing a configuration of an automatic wiring system of a semiconductor integrated circuit device according to a fourth embodiment. In the configuration shown in FIG. The database 11 is kept as it is, the database 12 is removed, and a database 50 is added instead. This database 50 stores signal line names corresponding to signal lines in a functional block that may malfunction if the connection wiring between the functional blocks passes through an upper layer. Other configurations are the same as those of the first embodiment (FIG. 1), and therefore, the same portions are denoted by the same reference characters and description thereof will not be repeated.

FIG. 20 is a schematic diagram of a semiconductor integrated circuit according to the fourth embodiment, and is composed of the same functional blocks 121, 122, and 123 as in FIG. 2 of the first embodiment. Each of the signal lines indicated by the signal line names E and F is a signal line that may cause a malfunction if the connection wiring between the functional blocks passes through the upper layer, and the mask layout data of the functional block 122 is generated. At times, signal line names E and F are added as text data on the mask layout. The definitions of the terminals and wiring are the same as in FIG.

The function of CPU 104 in the fourth embodiment will be described with reference to FIG. FIG. 21 shows C
5 is a flowchart illustrating a process performed by a PU 104. As in the case of the first embodiment, the processing is started in order from step 111 based on the input of the external input device 105. In step 111, arrangement information of each functional block is read from the database 101, and in step 112, terminal information is read from the database 102, and in step 113
Reads the wiring rules from the database 103. In step 114, in accordance with the wiring rules read in step 113, all routes that allow connection wiring between the terminal A and the terminal A 'and between the terminal B and the terminal B' are generated as virtual wiring (FIG. 22). reference).

In step 14, the layout data of each functional block is read from the database 11. In step 51, the signal line names E and F are read from the database 50. In step 52, the arrangement and the area of the signal line data of the wiring prohibited area on the semiconductor integrated circuit are detected based on the layout data read in step 14 and the signal line names E and F read in step 51. FIG. 22 is a schematic diagram of the virtual wiring up to step 52. Signal line name E, F
The area of the signal line data indicated by overlaps the virtual wiring in the X direction indicated by the broken line.

In step 53, a part corresponding to the signal line data indicated by the signal line names E and F corresponding to the wiring prohibited area detected in step 52 from the wiring path virtually generated in step 114 is changed from the wiring path. exclude.
FIG. 23 is a schematic view showing a state in which it is excluded. In FIG. 22, among the virtual wirings in the X direction and the Y direction, signal line names E,
The two virtual wirings in the X direction displayed in the wiring prohibited area indicated by F are deleted in FIG.

In step 115, step 114
From the remaining virtual wiring data excluded in step 53 from the virtual wiring data generated in step, a route for connecting and wiring with the shortest distance is calculated according to the connection order of the terminal information read in step 112. In this example, it is assumed that the connection between the terminal A and the terminal A ′ is defined as the first place, and the connection between the terminal B and the terminal B ′ is defined as the second place. First, a wiring route for connecting and wiring the terminal A and the terminal A ′ with the shortest distance is arbitrarily calculated and determined from the wiring route based on the remaining virtual wiring data. Next, a wiring path for connecting and wiring the terminal B and the terminal B ′ with the shortest distance except for the wiring path used for the connection wiring between the terminal A and the terminal A ′ is arbitrarily calculated and determined.

In step 18, it is determined whether or not the connection wiring route has been calculated or not as a result of step 115. If not, stop processing,
After taking measures such as changing the functional block arrangement, it is necessary to perform the processing again from START (step 111).

In step 116, step 115
24, two-layer wiring data along the X direction and three-layer wiring data along the Y direction are generated, as shown in the schematic diagram of FIG. Via hole data (see black dots) is generated at the intersection based on the wiring rules of the database 103 read in step 113. The four terminals A, A ',
Both B and B 'are located in the second layer. First, a path extends in the X direction as a two-layer wiring (broken line) from the terminal A, and continues to a three-layer wiring (solid line) via a via hole. The three-layer wiring is prohibited from wiring indicated by signal line names E and F. The path extends in the Y direction so as to avoid the region, and further extends in the X direction as a two-layer wiring (broken line) via a via hole, and is connected to the terminal A ′. Similarly, a path extends from the terminal B to a position avoiding the wiring prohibition area along the X direction as a two-layer wiring (broken line).
The path extends in the Y direction as a layer wiring (solid line), and further extends in the X direction as a two-layer wiring (dashed line) via a via hole, and is connected to the terminal B ′. Others are the same as in the first embodiment. The signal line to be removed from the virtual wiring may be a signal line along the Y direction, a combination of a signal line along the X direction and a signal line along the Y direction, And X
There may be a case where the signal line is bent in the direction and the Y direction. Each case can be addressed.

According to the fourth embodiment, the signal line name for designating the signal line data for the circuit section in which the connection wiring in the upper layer is prohibited inside the functional block is described in the text in the mask layout data of the functional block. By inputting data as data and incorporating wiring prohibition information based on the signal line name into the automatic wiring method, signal lines that may malfunction or degrade performance if the upper layer becomes a wiring path inside a functional block Since the connection wiring between the functional blocks can be performed in a state excluding, the automatic connection wiring in consideration of the circuit operation of the functional block can be performed.

Although some embodiments have been described above, it is assumed that the technology of each embodiment may be combined with any other embodiment in a hybrid manner as long as there is no logical contradiction.

[0062]

According to the first aspect of the present invention, there is provided an automatic wiring system for a semiconductor integrated circuit device, wherein an area where a signal delay or a malfunction may occur when wiring passes through an intermediate functional block is defined as a wiring prohibited area. By setting the wiring prohibition information defined as, and excluding the virtual wiring in the wiring prohibition area among the virtual wirings appearing during the automatic wiring, and performing automatic wiring based on the remaining virtual wiring data, Automatic wiring can be performed between terminals of one functional block without generating a capacitance between the terminals of the circuit unit in the functional block. As a result, the connection wiring between the terminals can avoid generating a capacitance that causes a signal delay with the wiring of the circuit unit itself in the function block, and also malfunction due to the influence of noise due to coupling. Can be avoided.

According to the second or sixth aspect of the automatic wiring method for a semiconductor integrated circuit device, an area where a signal delay or a malfunction may occur if the wiring passes through an intermediate functional block. Rectangle data is set in order to determine the area as a prohibited area, and among the virtual wiring appearing during the automatic wiring, the virtual wiring in the wiring prohibited area specified by the rectangular data is excluded, and the automatic wiring is performed based on the remaining virtual wiring data. Is performed without causing a capacitance that causes signal delay or malfunction between the terminals of two separate functional blocks and the wiring of the circuit unit itself in the functional block, and therefore, the intermediate functional block Automatic wiring can be performed in consideration of the operation of the circuit.

According to the third or seventh aspect of the present invention,
In order to determine a region where signal delay or malfunction may occur when wiring passes through an intermediate functional block as a wiring prohibited region, a cell data name corresponding to the cell data of the wiring prohibited region is set, By excluding the virtual wiring in the wiring prohibited area based on the cell data name among the virtual wirings appearing during the automatic wiring, the automatic wiring is performed based on the remaining virtual wiring data, so that the terminals of two separated functional blocks are separated. Can be automatically wired without causing a capacitance that causes signal delay or malfunction between the wiring of the circuit portion itself in the functional block and therefore taking into account the circuit operation of the intermediate functional block.

According to the invention of claim 4 or claim 8,
In order to determine a region where a signal delay or malfunction may occur when wiring passes through a memory function block having a ROM or RAM function as a wiring prohibition region, a region of a memory cell array portion and a bit line in the memory cell array portion are defined. The direction is set in advance, and among the virtual wirings appearing during the automatic wiring, virtual wirings parallel to the bit line direction in the memory cell array portion are excluded, and automatic wiring is performed based on the remaining virtual wiring data, so that the distance is increased. Between the terminals of the two functional blocks, there is no increase in the bit line capacity that causes a signal delay or malfunction in the memory cell array portion in the memory functional block, and therefore, the write / read operation of the intermediate memory functional block Automatic wiring can be performed in consideration of

According to the fifth or ninth aspect of the present invention,
In order to determine the area where signal delay or malfunction may occur if wiring passes through the intermediate function block as a wiring prohibited area, set the signal line name corresponding to the signal line data and set it during automatic wiring. By excluding the virtual wiring in the wiring prohibition area based on the signal line name among the appearing virtual wirings and performing automatic wiring based on the remaining virtual wiring data, the function blocks between two separated functional blocks are separated. The automatic wiring can be performed in a state in which a capacitance that causes a signal delay or a malfunction is not generated between the internal wiring and the wiring of the circuit unit itself, and therefore, the circuit operation of the intermediate functional block is considered.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an automatic wiring system of a semiconductor integrated circuit device according to a first embodiment of the present invention;

FIG. 2 is a schematic diagram of a semiconductor integrated circuit in Embodiment 1.

FIG. 3 is a flowchart showing the operation of the automatic wiring method according to the first embodiment;

FIG. 4 is a schematic diagram of a virtual wiring according to the first embodiment;

FIG. 5 is a schematic diagram of the remaining virtual wiring after the virtual wiring in the wiring prohibited area is deleted in the first embodiment;

FIG. 6 is a schematic diagram of wiring in a state where automatic wiring is completed in the first embodiment;

FIG. 7 is a block diagram showing a configuration of an automatic wiring system of a semiconductor integrated circuit device according to a second embodiment of the present invention;

FIG. 8 is a schematic diagram of a semiconductor integrated circuit in Embodiment 2.

FIG. 9 is a flowchart showing the operation of the automatic wiring method according to the second embodiment;

FIG. 10 is a schematic diagram of a virtual wiring according to the second embodiment.

FIG. 11 is a schematic diagram of the remaining virtual wiring after the virtual wiring in the wiring prohibited area is deleted in the second embodiment;

FIG. 12 is a schematic diagram of wiring in a state where automatic wiring is completed in the second embodiment;

FIG. 13 is a block diagram showing a configuration of an automatic wiring system of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 14 is a schematic diagram of a semiconductor integrated circuit in Embodiment 3

FIG. 15 is a flowchart showing the operation of the automatic wiring method according to the third embodiment;

FIG. 16 is a schematic view of a virtual wiring according to the third embodiment.

FIG. 17 is a schematic diagram of a remaining virtual wiring in Embodiment 3 in which a virtual wiring along a bit line direction is erased in a region of a memory cell array portion;

FIG. 18 is a schematic diagram of wiring in a state where automatic wiring is completed in the third embodiment;

FIG. 19 is a block diagram showing a configuration of an automatic wiring system of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 20 is a schematic diagram of a semiconductor integrated circuit in Embodiment 4.

FIG. 21 is a flowchart showing the operation of the automatic wiring method according to the fourth embodiment;

FIG. 22 is a schematic view of a virtual wiring according to the fourth embodiment.

FIG. 23 is a schematic diagram of a virtual wiring remaining after the virtual wiring in the wiring prohibited area is deleted in the fourth embodiment.

FIG. 24 is a schematic diagram of wiring in a state where automatic wiring is completed in the fourth embodiment.

FIG. 25 is a block diagram showing a configuration of an automatic wiring system of a semiconductor integrated circuit device according to a conventional technique.

FIG. 26 is a schematic diagram of a semiconductor integrated circuit according to a conventional technique.

FIG. 27 is a flowchart showing the operation of the conventional automatic wiring method.

FIG. 28 is a schematic view of a virtual wiring according to a conventional technique.

FIG. 29 is a schematic diagram of wiring in a state where automatic wiring is completed in the conventional technology.

[Explanation of symbols]

 11 Layout Data Database 12 Excluded Area Mask Layout Layer Database 20 Excluded Area Cell Data Name Database 40 Memory Function Block Information Database 50 Excluded Area Signal Line Name Database 101 Placement Information Database 102 Terminal Information Database 103 Wiring Rules Database 104 CPU 105 External input device 106 Data bus 121 Function block 122 Function block 123 Function block 124 Memory function block A, A 'terminal to be connected and wired B, B' terminal to be connected and wired C Rectangular data D Cell data name E, F signal line name MEM memory cell array section BL bit line

Claims (9)

[Claims] 1. A method of automatically wiring terminals of two function blocks via another function block between the two function blocks, wherein wiring prohibition information for defining a wiring prohibition area in the another function block is provided. It is configured such that virtual wiring in a wiring prohibited area is excluded based on the wiring prohibition information among virtual wirings appearing during automatic wiring, and automatic wiring is performed based on remaining virtual wiring data. Automatic wiring method for semiconductor integrated circuit devices. 2. A method for automatically wiring terminals of two function blocks via another function block between the two function blocks, wherein rectangular data defining a wiring prohibited area in the another function block is set. In addition, a semiconductor integrated circuit configured to exclude a virtual wiring in a wiring prohibited area based on the rectangular data among virtual wirings appearing in the automatic wiring and to perform automatic wiring based on the remaining virtual wiring data Automatic wiring system for equipment. 3. A method of automatically wiring terminals of two functional blocks via another functional block between the two functional blocks, and corresponding to cell data defining a wiring prohibited area in the another functional block. The cell data name is set in advance, and among the virtual wirings appearing during the automatic wiring, the virtual wiring in the wiring prohibited area based on the cell data name is excluded, and the automatic wiring is performed based on the remaining virtual wiring data. Automatic wiring method for the configured semiconductor integrated circuit device. 4. A method of automatically wiring terminals of two function blocks via a memory function block having a ROM or RAM function between the two function blocks, wherein a region of a memory cell array section in the memory function block is provided. And the direction of the bit line in the memory cell array portion are set, and the virtual wires parallel to the bit line direction in the memory cell array portion are excluded from the virtual wires appearing during the automatic wiring, and the remaining virtual wire data is set. An automatic wiring method for a semiconductor integrated circuit device configured to perform automatic wiring based on the following. 5. A method of automatically wiring terminals of two function blocks via another function block between the two function blocks, wherein the signal line data defining a wiring prohibited area in the another function block is provided. A corresponding signal line name is set, a virtual wiring in a wiring prohibited area based on the signal line name is excluded from virtual wirings appearing during automatic wiring, and automatic wiring is performed based on remaining virtual wiring data. Automatic wiring method for a semiconductor integrated circuit device configured as described above. 6. A method of automatically wiring terminals of two functional blocks via another functional block between the two functional blocks, wherein: means for storing arrangement information of each functional block; Means for storing terminal information about the terminal positions and connection destination terminals of the functional blocks; means for storing wiring rules for via holes for connecting and wiring wiring layers for connecting and wiring between functional blocks; and Means for storing rectangular data that defines a wiring prohibited area in the another functional block; and information between the terminals to be connected between the two functional blocks.
Means for generating routes of all virtual wires that can be connected and routed according to rules; means for excluding virtual wires in a wire-prohibited area specified by the rectangular data from the generated routes of virtual wires; Means for calculating a path having the shortest wiring distance from the paths of the remaining virtual wirings excluded from the above. 7. A method for automatically wiring terminals of two function blocks via another function block between the two function blocks, wherein: means for storing arrangement information of each function block; Means for storing terminal information about the terminal positions and connection destination terminals of the functional blocks; means for storing wiring rules for via holes for connecting and wiring wiring layers for connecting and wiring between functional blocks; and Means for storing a cell data name for designating cell data defining a wiring prohibited area in the another functional block;
Means for generating routes of all virtual wires that can be connected and routed in accordance with rules; and generating a virtual wire of a wire prohibited area corresponding to the cell data specified by the cell data name from the generated virtual wire route. An automatic wiring method for a semiconductor integrated circuit device, comprising: means for excluding; and means for calculating a path having the shortest wiring distance from the paths of the remaining virtual wirings excluded. 8. A method of automatically wiring terminals of two function blocks via a memory function block having a ROM or RAM function between the two function blocks, wherein means for storing arrangement information of each function block is provided. Means for storing terminal information about the terminal positions and connection destination terminals of the two functional blocks; wiring layers for connecting and wiring between the functional blocks and wiring rules for via holes for connecting and wiring different wiring layers. Means for storing the area of the memory cell array portion in the memory functional block and the bit line direction in the memory cell array portion;
Means for generating paths of all virtual wirings that can be connected and wired in accordance with rules; and excluding virtual wirings parallel to the bit line direction in the memory cell array area from the generated virtual wiring paths. An automatic wiring method for a semiconductor integrated circuit device, comprising: means for calculating a path with the shortest wiring distance from the remaining virtual wiring paths excluded from the above. 9. A method of automatically wiring terminals of two function blocks via another function block between the two function blocks, wherein: means for storing arrangement information of each function block; Means for storing terminal information about the terminal positions and connection destination terminals of the functional blocks; means for storing wiring rules for via holes for connecting and wiring wiring layers for connecting and wiring between functional blocks; and Means for storing a signal line name of a signal line corresponding to a wiring prohibited area among signal lines in the another functional block;
Means for generating paths of all virtual wirings that can be connected and wired according to rules; and generating a virtual wiring of a wiring prohibited area corresponding to the signal line specified by the signal line name from the generated virtual wiring path. An automatic wiring method for a semiconductor integrated circuit device, comprising: means for excluding; and means for calculating a path having the shortest wiring distance from the paths of the remaining virtual wirings excluded.