JPH08307057A - Multilayer printed circuit board and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] A multilayer high-density wiring circuit board capable of significantly improving wiring density without lowering reliability by achieving at least landing of via holes and surface flattening of each layer, and manufacturing thereof. Realize the method. [Structure] By alternately stacking a plurality of wiring layers and insulating layers, at least the first wiring layer 9 is provided on the insulating base material 2.
Further, the multilayer wiring circuit board has a laminated body structure 4 in which the second wiring layer 10 is laminated on the first wiring layer 9 via the interlayer insulating layer 16, and the through hole 6 penetrating each layer is formed in the laminated body 4. And an interlayer insulating layer 16 provided on the first wiring layer 9 and having a flat surface, and a surface formed in the groove 15 provided in the insulating layer is the same flat surface as the surface of the interlayer insulating layer 16. And a second wiring layer 10 plated and a via hole 8 having no land portion for connecting one end of the second wiring layer 10 to the first wiring layer 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring circuit board and a method for manufacturing the same, and more particularly to a multilayer wiring circuit board and a method for manufacturing the same which are suitable for increasing the density of wiring and simplifying the manufacturing process.

[0002]

2. Description of the Related Art An example of a conventional manufacturing process of a multilayer wiring circuit board will be described with reference to the manufacturing process chart of FIG. First, as shown in step (1) of FIG. 2, a glass / epoxy substrate 2 (common name for an insulating substrate obtained by impregnating glass fiber with an epoxy resin) is prepared, and then a glass / epoxy substrate 2 having copper layers 1 attached to both surfaces is prepared. As shown in the step (2), the copper layer 1 is patterned by the photo-etching step to form the first wiring layer 9 on both surfaces.

Then, as shown in step (3) of FIG. 2, a plurality of layers of the substrate on which the first wiring layer 9 is formed are stacked with the adhesive layer 3 interposed therebetween, and the adhesive layer 3 is further formed on both surfaces of the laminate. The surface on which the second wiring layer 10 is formed on the inside and the copper layer surface on which the surface circuit is formed on the outside.
The substrates are stacked, and these laminates are thermocompression bonded and integrated to form a laminate 4, as shown in step (4) of FIG.

Thereafter, as shown in step (5) of FIG.
The surface layer circuit 5 and the through holes 6 are formed through the steps such as drilling for forming through holes, copper plating, circuit formation, solder resist formation, and the multilayer wiring circuit board is completed.

In the conventional process, since the connection of each inner layer is made by the through holes 6, the presence of the through holes having a relatively large hole diameter (for example, the diameter of 0.3 to 0.9 mm) increases the wiring density. It's getting harder. In addition, since each layer is laminated in a lump, misalignment occurs in each layer during lamination, which is a bottleneck in increasing the positioning accuracy.

In order to solve these problems, a build-up method has been proposed in which a micro via hole (for example, 0.1 mm) is formed in an interlayer insulating layer by a photoetching method, and a wiring layer and an insulating layer are sequentially stacked. For example, JP-A-4-148590 can be cited.

In this process, as shown in the manufacturing process charts in FIGS. 3A and 3B, first, in the step (1), the copper layer of the glass / epoxy substrate 2 having the copper layers 1 adhered on both sides is Patterning by photo etching process,
The first wiring layer 9 including the land 12 is formed, and then (2)
Photosensitive resin insulator 7 on the surface etched in the process
Is applied, exposed and developed, and a via hole 8 is formed by a photo-etching process.

Subsequently, in step (3), electroless copper plating 13 is performed on the entire surface through a catalyst applying step, and then (4)
In the step, patterning is performed by photoetching to form the second wiring layer 10 including the land 12. Similarly, the photosensitive resin insulating layer 7 is formed in the step (5), the through holes 6 are formed in the step (6), the electroless copper plating is performed in the step (7) through the catalyst application step, and the step (8). At land 12
The third printed wiring board is completed by forming the third wiring layer 14 including, and forming the photosensitive resin insulating layer 7 in the step (9).

However, even in this process, the land 12 is required to absorb the deviation between the negative mask 11 and the through hole 6 and the via hole 8 as shown in FIG. In order to do so, the existence of the land 12 becomes a bottleneck. Further, since copper plating is performed on the entire surface of each layer, unnecessary portions other than the circuit are also copper-plated, which is not preferable in terms of cost because of economical reasons.

Furthermore, since the multilayer wiring circuit board of this type has an alternating laminated structure of a wiring layer including lands and a photosensitive resin insulating layer, the uneven pattern of the underlying wiring layer is increased as the number of laminated layers increases. Are emphasized on the surface of the insulating layer. As a result, in the high-density wiring in which the thickness of the wiring layer is thin, this unevenness causes a disconnection, which reduces reliability.

Further, in order to prevent copper plating on unnecessary portions other than the circuit, a groove corresponding to the circuit pattern is formed in the insulating layer by press molding using a mold, and a catalyst is provided in the groove. A method of embedding wiring by electroless copper plating has also been proposed.

However, although this method can be applied to a single-layer wiring, it is not suitable for a high-density multi-layer wiring structure. The reason is that when forming multiple layers, press molding with a mold is repeated to form the groove, and as a result of applying unnecessary pressure to the underlying circuit pattern, an accident such as disconnection or deformation may be caused. is there. Incidentally, as a technique related to this type of technology, for example, Japanese Patent Laid-Open No. 62-290194
Publication.

[0013]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned problems caused by the conventional build-up method, and the first object is at least a landing of via holes and an inner layer wiring structure. Is to provide a multilayer wiring circuit board in which the wiring density is remarkably improved without lowering the reliability by flattening the surface of each layer constituting the substrate. A second object is to reduce the cost by simplifying the process. It is an object of the present invention to provide a method for manufacturing a multilayer printed circuit board that can be reduced.

[0014]

The first object is to stack a plurality of wiring layers and insulating layers alternately so that at least the first wiring layer on the insulating base material and further on the first wiring layer. A multilayer wiring circuit board having a laminated body structure in which a second wiring layer is laminated via an interlayer insulating layer, in which a through hole penetrating each layer and a first wiring layer are provided. An interlayer insulating layer having a flat surface; a second wiring layer plated so that the surface forms the same flat surface as the surface of the interlayer insulating layer in a groove provided in the interlayer insulating layer; And a via hole having no land portion connecting one end to the first wiring layer.

Explaining the terms of the through hole and the via hole used herein, the through hole means a conductor hole penetrating each layer of the multilayer wiring circuit board, that is, a through hole having a conductor layer formed on the inner wall of the hole. On the other hand, a via hole is a conductor hole provided in an interlayer insulating layer that forms a multilayer wiring circuit board, and is mainly intended for connection between upper and lower wiring layers that form an inner layer wiring structure. In addition, it does not pass through the entire laminated body, but is a conduction hole provided in a specific insulating layer, and the bottom portion means a portion that constitutes a connection portion with a lower wiring layer.

As a preferred example of the first wiring layer and the insulating base material, for example, an insulating base material obtained by impregnating glass fiber with an epoxy resin (commonly called a glass / epoxy substrate) is used.
A double-sided copper-clad insulating substrate having copper foils laminated on both sides thereof is used, a through-hole is formed in the double-sided copper-clad insulating substrate, and a first wiring layer is formed by a well-known photo-etching process.

Further, it is desirable that both the first and second wiring layers have a thickness smaller than that of the interlayer insulating layer. As the interlayer insulating layer forming the inner layer wiring structure, a well-known heat-resistant organic insulating layer such as polyimide is usually used, but preferably a photosensitive solder resist is used. Further, it is desirable that the second wiring layer including the via hole having no land portion is formed of a copper plating layer.

The second object is to prepare a substrate having a conductor layer formed on at least one surface of an insulating base material and form a through hole in the substrate, and to form a through hole in the conductor layer.
A step of forming a circuit pattern to be a wiring layer, a step of forming an interlayer insulating layer having a thickness larger than that of the circuit pattern on a substrate including the circuit pattern, and a step of forming a first wiring layer in the interlayer insulating layer. Forming a concave portion including a corresponding groove pattern and a via hole penetrating the interlayer insulating layer and having the first wiring layer as a bottom portion, and removing the insulating layer attached in the through hole to expose the conductor layer; A step of applying a catalyst layer to the entire surface of the substrate including the inside of the through hole and the concave portion, and a step of polishing the substrate surface to remove the catalyst layer on the surface of the substrate excluding the inside of the through hole and the concave portion,
And a step of forming a conductor layer serving as a second wiring layer in the through hole and the recess by electroless plating.

When laminating a large number of wiring layers, the above steps to steps are repeated a plurality of times until the required number of layers is reached, and a multilayer step is formed, and following this repeating step, the final step. As a result, after the step, it is desirable to perform a step of covering the through hole and the other area on the surface of the substrate other than the connection terminal to be the external terminal with the solder resist.

When the groove pattern is filled with a plating layer in the plating step, the thickness of the plating layer is set to a thickness corresponding to the depth of the groove, and the surface thereof is flush with the surface of the interlayer insulating layer. The step is to form a planar state without steps.

The first wiring layer is a copper foil pattern and the second wiring layer is
It is practical and desirable to form the wiring layer by electroless plating.

A groove pattern corresponding to the first wiring layer and a concave portion including a via hole penetrating the interlayer insulating layer and having the first wiring layer as a bottom portion are formed in the interlayer insulating layer in the above step, and the through hole is formed in the through hole. All the steps of removing the attached insulating layer and exposing the conductor layer are processing of the insulating layer,
It can be easily performed by a fine processing method such as laser processing or end mill processing. Particularly, in the case of laser processing, it is preferable to form a high-density fine pattern because it is based on a pattern forming step in which a laser beam is converged optically and irradiated finely.

As the final step, which is a step, after the step, in the step of covering the through hole and the area other than the connection terminal to be the external terminal on the surface of the substrate with the solder resist, the solder resist is composed of a photosensitive solder resist. Then, it is desirable to form the resist film by photolithography by exposing and developing it through a predetermined mask. As a result, it is possible to expose only the connecting portion necessary for connecting the electronic components and easily cover the other portion with the resist.

[0024]

By using the structure and the manufacturing method of the multilayer wiring circuit board as described above, it is not necessary to align the mask when forming the conductor circuit, so that at least the via holes can be made landless, thereby the wiring density of the pattern. Can be improved. This landless method is also possible for through holes, and lands are formed for the through holes of the first wiring layer, but for the through holes of the second wiring layer formed by plating the second or more layers. Structurally landless.

Further, the electroless plating at the time of forming the wiring layer can be formed only in the region inside the recess necessary for forming the circuit, and furthermore, by adjusting the plating conditions such as the plating time, the recessed portion can be formed. A plating layer corresponding to the depth can be easily formed, and the surface of the plating layer can be made flush with the surface of the surrounding flat insulating layer. Therefore, when the insulating layer and the wiring layer are formed into multiple layers, the surfaces thereof become flat, so that a multilayer wiring circuit board having extremely high reliability can be obtained.

Further, since the solder resist formed on the outermost peripheral surface can use a thermosetting type, it is possible to realize an inexpensive high-density wiring board and an inexpensive mounting board for a multi-chip module. You can

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in more detail below with reference to the drawings. FIG. 1 shows a manufacturing process diagram by a sectional perspective view showing a manufacturing method by a build-up method and a structure of a multilayer wiring circuit board obtained by the method. Hereinafter, the steps will be sequentially described according to the order of the illustrated steps.

Step (a): First, the thickness is 18 to 35 μm on both sides.
A through hole 6 is formed by drilling a hole in a glass / epoxy insulating base material 2 having a copper foil 1 of m.

Step (b): The copper foil 1 is patterned by using a well-known photo etching method, and the first wiring layer 9 including the land 12 of the through hole opening and the via hole bottom 8a is formed.
To form.

Step (c): An insulating layer 16 is formed on the entire surface of the base material 2 on which the wiring layer 9 and the through holes 6 are formed by using an insulating resin (for example, an epoxy resin as a thermosetting solder resist). At this time, the thickness of the insulating layer 16 is 40 μm.
m (usually about 40 to 70 μm), which is thicker than the height of the wiring 9.

Step (d): The solder resist 16 is processed to form the via hole 8 and the wiring groove 15, and the resin layer attached to the through hole 6 is removed to remove the conductor 1.
2 expose the surface. In forming the pattern of the via hole 8, a cylindrical hole having a diameter of 100 μm is formed to expose the bottom conductor 8a. In patterning the wiring groove 15, a groove having a width of 100 μm and a depth of 35 μm is formed according to a shape corresponding to the circuit wiring pattern, and one end of the specific groove reaches the through hole 6 or the via hole 8. .

Such processing of the resist 16 was carried out by a laser processing apparatus provided with a stage capable of moving the sample substrate in two-dimensional XY directions and capable of narrowing the laser beam with a lens according to the processing width. Although end mill processing can be used instead of laser processing, laser processing is suitable for precise pattern formation.

Step (e): A catalyst 17 for electroless copper plating is applied to the entire substrate including the through holes 6, the via holes 8 and the wiring grooves 15. The catalyst 17 was applied according to a known method of immersing the substrate in a commercially available catalyst solution, pulling it up, and drying it.

Step (f): The surface of the insulating layer 16 is polished to about 5 μm (usually about 1 to 5 μm) using a polishing device, the catalyst 17 on the insulating layer 16 is removed, and plating is required. The catalyst 17 is left only in the through hole 6, the via hole 8 and the groove 15.

Step (g): The electroless copper plating layer 13 is formed in the region where the catalyst 17 remains. That is, copper is attached only to the conductor circuits of the through holes 6, the via holes 8 and the wiring grooves 15. Thereby, the laminated body 4 having the second wiring layer 10 formed thereon is completed.

The copper plating layer 1 to be the second wiring layer 10
3 is formed by a depth corresponding to the depth of the groove 15, and its surface is made the same flat surface as the surface of the insulating layer 16. In this example, the initial groove depth of 35 μm in step (d) was 5 μm in the surface polishing step in step (f), so the remaining groove depth was 30 μm.
And the second wiring layer 10 made of a copper plating layer has a thickness of 30
The wiring layer has a line width of 100 μm and a line width of 100 μm.

Step (h): An inner layer wiring structure having the same shape as the laminate obtained by the step (g) by repeating the steps (c) to (g) a plurality of times to alternately stack the insulating layers and the wiring layers. Body (but
Required for mounting electronic components by forming a photo-sensitive solder resist 16a after forming (the number of laminated layers is different) and selectively removing the resist on the through holes 6 and the external connection terminals (not shown) by a photo-etching process. The desired multilayer wiring circuit board is completed by exposing the various connecting portions. In this example, steps (c) to (g) were repeated 5 times to manufacture a high-density wiring board having 12 wiring layers.

The characteristics of the multilayer wiring circuit board thus obtained are that the land is not formed in the via hole 8 and the through hole 6 is the second layer except the land 12 at the time of forming the first wiring layer. No land is formed in the formation of the wiring layer, and the wiring layer (second wiring layer 10) formed from the second layer is buried in the groove 15 of the insulating layer 16, and its surface is flattened by polishing. That is, there is no step because it forms the same plane as the surface of the insulating layer 16 thus formed. Therefore, the wiring area can be expanded as much as the land is eliminated, and high-density wiring is possible, and the flat surface of the substrate makes it suitable for mounting imposition mounting components such as LSI flip chips. Highly reliable component connection is possible.

Further, the manufacturing method by the build-up method of the present embodiment is characterized in that positioning is easy at the time of pattern formation of each layer (no land is required), and in the wiring pattern forming step by copper plating, Copper plating is formed only in the recesses that correspond to the wiring pattern formed in the insulating layer, so the minimum necessary plating process is sufficient and it is economically superior. There is no significant increase in the number of processes, and it is rather simplified.

[0040]

As described above in detail, according to the present invention, the intended purpose can be achieved. That is, the multilayer printed circuit board of the present invention achieves landless landing of via holes, landless landing of through-hole openings in stacked wiring layers, and flattening of the surface of each layer, thereby reducing reliability. It is possible to significantly improve the wiring density without doing so.

Further, in the method for manufacturing a multilayer printed circuit board according to the present invention, the positioning of each layer during pattern formation becomes easy, and the conductor plating layer is formed only in the recesses corresponding to the wiring pattern. Plating process, no special process increase compared to the past even during the entire manufacturing process, and rather simplified, it is possible to economically and easily manufacture highly reliable circuit boards. It has an excellent effect.

[Brief description of drawings]

FIG. 1 is a sectional perspective view showing a manufacturing process of a multilayer printed circuit board according to an embodiment of the present invention.

FIG. 2 is a sectional perspective view showing a manufacturing process of a multilayer printed circuit board by a conventional laminated bonding method.

FIG. 3A is a sectional perspective view showing a manufacturing process of a multilayer printed circuit board by a conventional build-up method.

FIG. 3B is a sectional perspective view showing a manufacturing process of a multilayer printed circuit board by a conventional build-up method.

FIG. 4 is a cross-sectional view showing a problem of a multilayer wiring circuit board according to a conventional build-up method.

[Explanation of symbols]

 1 ... Copper foil, 2 ... Glass / epoxy base material, 3 ... Adhesive layer, 4 ... Laminated board, 5 ... Surface layer circuit, 6 ... Through hole, 7 ... Photosensitive insulator, 8 ... Photovia (via hole), 9 ... No. 1 wiring layer, 10 ... 2nd wiring layer, 11 ... Baking mask (negative mask), 12 ... Land, 13 ... Electroless copper plating, 15 ... Groove, 16 ... Insulating layer, 16a ... Photosensitive solder resist.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Terutake Kato 216 No. 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Information & Communication Division (72) Naoki Nishimura 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd., Information & Communication Division (72) Inventor Yuko Iwamoto, 216 Totsuka-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Hitachi, Ltd., Information & Communication Division

Claims (11)

[Claims] 1. By alternately stacking a plurality of wiring layers and insulating layers, at least a first wiring layer is formed on an insulating base material.
A multilayer wiring circuit board having a laminated body structure in which a second wiring layer is laminated on the first wiring layer via an interlayer insulating layer, the through hole penetrating each layer in the laminated body, (1) an interlayer insulating layer having a flat surface provided on one wiring layer; and a second plated plate so that the surface forms the same flat surface as the surface of the interlayer insulating layer in the groove provided in the interlayer insulating layer. A multilayer wiring circuit board comprising: a wiring layer; and a via hole having no land portion connecting one end of the second wiring layer to the first wiring layer. 2. The multilayer printed circuit board according to claim 1, wherein the thickness of the wiring conductors forming the first and second wiring layers is smaller than the thickness of the interlayer insulating layer. 3. A double-sided copper-clad insulating substrate in which the insulating substrate and a wiring substrate having a first wiring layer formed on the surface thereof are laminated with copper foil on both sides of an insulating substrate obtained by impregnating glass fiber with an epoxy resin. The multilayer printed circuit board according to claim 1, which is formed of a wiring board having a wiring pattern formed thereon. 4. The multilayer printed circuit board according to claim 1, wherein the insulating layer is composed of a photosensitive solder resist. 5. The multilayer printed circuit board according to claim 1, wherein the second wiring layer and the via hole having no land are formed of a copper plating layer. 6. A step of preparing a substrate having a conductor layer formed on at least one surface of an insulating base material, forming a through hole in the substrate, and a step of forming a circuit pattern to be a first wiring layer on the conductor layer. A step of forming an interlayer insulating layer having a thickness thicker than that of the circuit pattern on the substrate including the circuit pattern, a groove pattern corresponding to the first wiring layer in the interlayer insulating layer, and penetrating the interlayer insulating layer. And forming a recess consisting of a via hole whose bottom is the first wiring layer, and removing the insulating layer adhering to the through hole to expose the conductor layer; and the entire surface of the substrate including the inside of the through hole and the inside of the recess. A step of applying a catalyst layer on the substrate, a step of polishing the surface of the substrate to remove the catalyst layer on the surface of the substrate excluding the inside of the through hole and the recess, and the second step in the through hole and the recess by electroless plating. Method for manufacturing a multilayer printed circuit board comprising a step of forming a conductive layer serving as a line layer. 7. A step of repeating a step to a step a plurality of times to form a multi-layer and, as a final step, after the step, the through hole and the other area other than the connection terminal to be an external terminal are covered with a solder resist. The method for manufacturing a multilayer printed circuit board according to claim 6, further comprising: 8. When the groove pattern is filled with a plating layer in the plating step of the step, the thickness of the plating layer is set to a thickness corresponding to the depth of the groove, and the surface is made flush with the surface of the interlayer insulating layer. 8. The method for manufacturing a multilayer printed circuit board according to claim 6, which is a step of forming a flat surface having no steps. 9. The multilayer printed circuit board according to claim 6, further comprising a step of forming the first wiring layer with a copper foil pattern and the second wiring layer with electroless plating. Production method. 10. In the through hole, a recess is formed in the interlayer insulating layer in the step, the groove pattern corresponding to the first wiring layer, and a via hole penetrating the interlayer insulating layer and having the first wiring layer as a bottom. 7. The method for manufacturing a multilayer printed circuit board according to claim 6, wherein the step of removing the insulating layer attached to and exposing the conductor layer is constituted by a pattern forming step of focusing and irradiating a laser beam. 11. A step as a final step after the step,
In the step of covering the through hole and the other area on the surface of the substrate other than the connection terminal which becomes the external terminal with the solder resist, the solder resist is composed of a photosensitive solder resist, and the resist film is exposed and developed through a predetermined mask. The method for manufacturing a multilayer printed circuit board according to claim 7, which is a step of forming a pattern by photolithography.