JPH01282892A - Manufacture of multilayer printed wiring board - Google Patents
Manufacture of multilayer printed wiring boardInfo
- Publication number
- JPH01282892A JPH01282892A JP63113198A JP11319888A JPH01282892A JP H01282892 A JPH01282892 A JP H01282892A JP 63113198 A JP63113198 A JP 63113198A JP 11319888 A JP11319888 A JP 11319888A JP H01282892 A JPH01282892 A JP H01282892A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- printed wiring
- multilayer printed
- resist
- resin layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000011347 resin Substances 0.000 claims abstract description 19
- 229920005989 resin Polymers 0.000 claims abstract description 19
- 239000000853 adhesive Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 13
- 230000001070 adhesive effect Effects 0.000 claims description 5
- 238000003754 machining Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract description 9
- 238000007747 plating Methods 0.000 abstract description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052802 copper Inorganic materials 0.000 abstract description 4
- 239000010949 copper Substances 0.000 abstract description 4
- 238000005553 drilling Methods 0.000 abstract description 4
- 238000007639 printing Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000004080 punching Methods 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 230000000149 penetrating effect Effects 0.000 abstract 4
- 238000010030 laminating Methods 0.000 abstract 2
- 238000003475 lamination Methods 0.000 description 7
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- 238000000465 moulding Methods 0.000 description 6
- 238000003825 pressing Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- KTRGHLZBDIJZLQ-UHFFFAOYSA-N elatine Natural products CCN1CC2(CCC(OC)C34C2C(OC)C5(OCOC56CC(OC)C7CC3(O)C6C7OC)C14)OC(=O)c8ccccc8N9C(=O)CC(C)C9=O KTRGHLZBDIJZLQ-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- BGTFCAQCKWKTRL-YDEUACAXSA-N chembl1095986 Chemical compound C1[C@@H](N)[C@@H](O)[C@H](C)O[C@H]1O[C@@H]([C@H]1C(N[C@H](C2=CC(O)=CC(O[C@@H]3[C@H]([C@@H](O)[C@H](O)[C@@H](CO)O3)O)=C2C=2C(O)=CC=C(C=2)[C@@H](NC(=O)[C@@H]2NC(=O)[C@@H]3C=4C=C(C(=C(O)C=4)C)OC=4C(O)=CC=C(C=4)[C@@H](N)C(=O)N[C@@H](C(=O)N3)[C@H](O)C=3C=CC(O4)=CC=3)C(=O)N1)C(O)=O)=O)C(C=C1)=CC=C1OC1=C(O[C@@H]3[C@H]([C@H](O)[C@@H](O)[C@H](CO[C@@H]5[C@H]([C@@H](O)[C@H](O)[C@@H](C)O5)O)O3)O[C@@H]3[C@H]([C@@H](O)[C@H](O)[C@@H](CO)O3)O[C@@H]3[C@H]([C@H](O)[C@@H](CO)O3)O)C4=CC2=C1 BGTFCAQCKWKTRL-YDEUACAXSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- KOWWOODYPWDWOJ-LVBPXUMQSA-N elatine Chemical compound C([C@]12CN(C3[C@@]45OCO[C@]44[C@H]6[C@@H](OC)[C@@H]([C@H](C4)OC)C[C@H]6[C@@]3([C@@H]1[C@@H]5OC)[C@@H](OC)CC2)CC)OC(=O)C1=CC=CC=C1N1C(=O)CC(C)C1=O KOWWOODYPWDWOJ-LVBPXUMQSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多層印刷配線板の製造方法に関し、特に開口部
を有する多層印刷配線板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a multilayer printed wiring board, and particularly to a method for manufacturing a multilayer printed wiring board having openings.
近年、半導体チップと称される電子部品は、その集積度
を高め、それにつれＩ１０端子数も増大してきており、
それを実装する印刷配線板も多層化、高密度化が要求さ
れている。特に半導体チ。In recent years, the degree of integration of electronic components called semiconductor chips has increased, and the number of I10 terminals has also increased accordingly.
The printed wiring boards on which they are mounted are also required to have multiple layers and higher density. Especially semiconductor chips.
ブを直接実装する多層印刷配線板においては、端子数の
増大に対応するため、階段状に形成した絶縁基板上にボ
ンディング用パッドを設けた構造がとられている。この
ような多層印刷配線板としては、例えば特開昭６２−１
５６８４７号公報に示された「多層配線板及びその製造
方法」（■）や特開昭６１−７５５９６号公報の「スル
ーホール多層回路基板とその製造方法」（■）がある。In multilayer printed wiring boards on which bonding pads are directly mounted, in order to cope with an increase in the number of terminals, a structure is adopted in which bonding pads are provided on an insulating substrate formed in a stepped shape. As such a multilayer printed wiring board, for example, Japanese Patent Application Laid-Open No. 62-1
There are "Multilayer wiring board and method for manufacturing the same" (■) shown in Japanese Patent Publication No. 56847 and "Through-hole multilayer circuit board and method for manufacturing the same" (■) in Japanese Patent Application Laid-Open No. 61-75596.
以下にこれらの多層印刷配線板の製造方法を図２及び図
３を参照して説明する。第２図は（Ｄの製造方法を説明
するための断面図である。まず、第２図（ａ）の如く銅
張積層板１に座ぐり加工を施して凹部１０を形成し、プ
リプレグ２ａ、２ｂ及び印刷配線板５ａ、５ｂに各々貫
通孔３を形成する。ここで貫通孔３は上方に位置するに
従い順次大きくなるようにする。次いで第２図（ｂ）の
如くプリプレグ２ａ、２ｂ及び印刷配線板５ａ、５ｂを
位置合わせして重ね、その上に銅張積層板１を凹部１０
を下に向けて重ねた後、積層成型を行なって多層印刷配
線板６とする。その後、穴明け、パネルメッキ、最外層
の回路形成を行なう。次いで第２図（ｃ）の如く多層印
刷配線板６に座ぐり加工を施して開口部８を形成して、
開口部を有する多層印刷配線板を得る。A method of manufacturing these multilayer printed wiring boards will be described below with reference to FIGS. 2 and 3. FIG. 2 is a sectional view for explaining the manufacturing method of (D). First, as shown in FIG. 2b and the printed wiring boards 5a, 5b.The through holes 3 are made to become larger sequentially as they are located upward.Then, as shown in FIG. 2(b), the prepregs 2a, 2b and the printing The wiring boards 5a and 5b are aligned and overlapped, and the copper clad laminate 1 is placed on top of the wiring boards 5a and 5b in the recess 10.
After stacking them facing downward, they are laminated and molded to form a multilayer printed wiring board 6. After that, hole drilling, panel plating, and circuit formation on the outermost layer are performed. Next, as shown in FIG. 2(c), the multilayer printed wiring board 6 is counterbored to form an opening 8.
A multilayer printed wiring board having openings is obtained.
第３図は（Ｕ）の製造方法を説明するための断面図であ
る。まず第３図（ａ）の如く、銅張積層板に感光性樹脂
によりメツキレジストを形成し金属レジスト１２（例え
ば半田、ニッケル、金）のメツキを行なった後、メツキ
レジストを剥離し、エツチングを行なって回路形成し印
刷配線板１１とする。次にプリプレグ２及び、前記印刷
配線板１１の内１枚に貫通孔３を形成する。次いで第２
図（ｂ）の如く上記の印刷配線板１１及びプリプレグ２
を位置合わせして重ね、積層成型を行なって、多層印刷
配線板６とする。次いで第３図（ｃ）の如く多層印刷配
線板６に穴明け、パネルメッキを施して、スルーホール
１３を形成する。次いで第３図（ｄ）の如く感光性樹脂
によりエツチングレジストを形成した後エツチングして
、開口部を有する多層印刷配線板を得る。FIG. 3 is a sectional view for explaining the manufacturing method of (U). First, as shown in FIG. 3(a), a plating resist is formed on a copper-clad laminate using a photosensitive resin, and a metal resist 12 (for example, solder, nickel, gold) is plated. After that, the plating resist is peeled off and etching is performed. Then, a circuit is formed and a printed wiring board 11 is obtained. Next, a through hole 3 is formed in the prepreg 2 and one of the printed wiring boards 11. Then the second
As shown in Figure (b), the above printed wiring board 11 and prepreg 2
are aligned and stacked, and laminated and molded to form a multilayer printed wiring board 6. Next, as shown in FIG. 3(c), holes are made in the multilayer printed wiring board 6 and panel plating is applied to form through holes 13. Next, as shown in FIG. 3(d), an etching resist is formed from a photosensitive resin and etched to obtain a multilayer printed wiring board having openings.
上述した従来の多層印刷配線板の製造方法は以下のよう
な欠点を有する。The conventional multilayer printed wiring board manufacturing method described above has the following drawbacks.
即ち（１）の製造方法においては積層成型時に、開口部
へプリプレグが流れ込んでしまうため、薄いプリプレグ
やプリプレグのフローが小さいノーフローのプリプレグ
を用いる必要がある。しかし前記のごときプリプレグを
用いて積層成型すると、印刷配線板の内層回路の近傍に
積層ボイドと呼ばれる気泡が発生する。この積層ボイド
は内層回路間の絶縁不良、層間剥離等の原因となる。そ
のため積層成型前に印刷配線板の表面にあらかじめ樹脂
をスクリーン印刷等の手法により塗布して、内層回路間
の間隙を埋める工夫がなされているが、多くの製造工数
、材料費を必要とするため、安価な多層印刷配線板の製
造はできない。上記の問題点は（Ｉ［）の製造方法にお
いても同様である。That is, in the manufacturing method (1), since the prepreg flows into the opening during lamination molding, it is necessary to use a thin prepreg or a no-flow prepreg with a small flow of prepreg. However, when the above-mentioned prepreg is used for lamination molding, air bubbles called lamination voids are generated near the inner layer circuit of the printed wiring board. This laminated void causes poor insulation between inner layer circuits, delamination, etc. For this reason, attempts have been made to fill in the gaps between the inner layer circuits by applying resin to the surface of the printed wiring board using a method such as screen printing before lamination molding, but this requires a large amount of manufacturing man-hours and material costs. , it is not possible to manufacture inexpensive multilayer printed wiring boards. The above problems also apply to the method for producing (I[).
上述した従来の開口部を有する多層印刷配線板に対して
、本発明は内層用印刷配線板上に樹脂層を形成する事に
より、積層成型時にプリプレグの開口部への流れ込みを
防止する事ができ、回路間隙への充填性が良好なプリプ
レグを使用できるため積層ボイドの発生を防止できる。In contrast to the above-mentioned conventional multilayer printed wiring board having openings, the present invention can prevent prepreg from flowing into the openings during lamination molding by forming a resin layer on the inner layer printed wiring board. Since it is possible to use prepreg that has good filling properties into circuit gaps, it is possible to prevent stacking voids from occurring.
又、この樹脂層の厚みにより、座ぐり加工機械の深さ方
向の許容範囲を拡大する事ができるので、開口部底面の
回路を損傷する事が無いという相違点を有する。Furthermore, the thickness of this resin layer allows the permissible range in the depth direction of the counterboring machine to be expanded, so there is a difference in that the circuit at the bottom of the opening will not be damaged.
本発明の目的は、かかる従来欠点を除去した多層印刷配
線板の製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a multilayer printed wiring board that eliminates such conventional drawbacks.
本発明によれば接着剤シートに機械加工を行なって所定
の形状の貫通孔を形成する工程と、内層用印刷配線板の
表面に前記貫通孔より一定寸法小さな形状に樹脂層を形
成する工程と、前記貫通孔と樹脂層の位置を合わせて、
前記接着剤シートと印刷配線板を重ね、加熱加圧する事
により成形し多層印刷配線板とする工程と、前記多層印
刷配線板を前記樹脂層の深さまで座ぐり加工を行なって
前記樹脂層を露出させる工程と、前記樹脂層を除去して
開口部を形成する工程とを含むことを特徴とする多層印
刷配線板の製造方法が得られる。According to the present invention, there are a step of machining an adhesive sheet to form a through hole of a predetermined shape, and a step of forming a resin layer in a shape smaller by a certain size than the through hole on the surface of the inner layer printed wiring board. , aligning the through hole and the resin layer,
A step of stacking the adhesive sheet and the printed wiring board and heating and pressurizing them to form a multilayer printed wiring board, and counterboring the multilayer printed wiring board to the depth of the resin layer to expose the resin layer. There is obtained a method for manufacturing a multilayer printed wiring board, which comprises the steps of: removing the resin layer to form an opening.
〔実施例１〕
以下に本発明の実施例を第１図（ａ）〜（ｄ）を参照し
て説明する。[Example 1] An example of the present invention will be described below with reference to FIGS. 1(a) to (d).
まず、第１図（ａ）の如くプリプレグ２に打ち抜き、あ
るいはルータ−加工等の手段によって、所定の形状の貫
通孔３を形成する。又、片面に回路を形成した印刷配線
板５の表面にエツチングレジスト４を、例えばデュポン
、［リストン４１２０Ｊドライフイルムを用い、フォト
印刷法で形成する。First, as shown in FIG. 1(a), a through hole 3 having a predetermined shape is formed in the prepreg 2 by punching or router processing. Further, an etching resist 4 is formed on the surface of the printed wiring board 5 on which a circuit is formed on one side by a photoprinting method using, for example, DuPont's [Riston 4120J dry film].
この時エツチングレジスト４の形状は貫通孔３より０．
１〜０．５ ｍｍ小さくする。次いで第１図（ｂ）の如
く貫通孔３とエツチングレジスト４の位置を合わせてプ
リプレグ２と印刷配線板５及びそれらの上に銅張積層板
１を重ね、所定のプレス条件に基いて積層成型を行なっ
て接着し、多層印刷配線板６とする。次いで第１図（ｃ
）の如く多層印刷配線板６に穴明け、パネルメッキ、回
路形成を施して最外層に回路を形成した後、エツチング
レジスト４の厚みのほぼ半分の深さまで座ぐり加工を行
ない、エツチングレジスト４を露出させる。次いで第１
図（ｄ）の如く、座ぐり加工部７の底面に残ったエツチ
ングレジスト４を５０℃の３ｗｔ％水酸化ナトリウムを
２〜４分間スプレーして剥離除去し、内層回路９を露出
させて、所望の開口部を有する多層印刷配線板を得た。At this time, the shape of the etching resist 4 is 0.0 mm from the through hole 3.
Reduce the size by 1 to 0.5 mm. Next, as shown in FIG. 1(b), the positions of the through holes 3 and the etching resist 4 are aligned, and the prepreg 2, the printed wiring board 5, and the copper clad laminate 1 are stacked on top of them, and lamination molding is performed under predetermined pressing conditions. The multilayer printed wiring board 6 is obtained by bonding. Next, Figure 1 (c
) After drilling holes in the multilayer printed wiring board 6, panel plating, and forming a circuit to form a circuit on the outermost layer, a counterbore process is performed to a depth of approximately half the thickness of the etching resist 4. expose. Then the first
As shown in Figure (d), the etching resist 4 remaining on the bottom surface of the counterbore 7 is peeled off by spraying 3 wt% sodium hydroxide at 50°C for 2 to 4 minutes to expose the inner layer circuit 9 and remove it as desired. A multilayer printed wiring board was obtained having openings of .
〔実施例２〕
以下に本発明の第２の実施例を第４図（ａ）〜（ｄ）を
参照して説明する。[Embodiment 2] A second embodiment of the present invention will be described below with reference to FIGS. 4(a) to 4(d).
まず第４図（ａ）の如くプリプレグ２ａ及びプリプレグ
２ｂに打ち抜き、あるいはルータ−加工等の手段によっ
て貫通孔３ａ、３ｂを形成する。又片面に回路を形成し
た印刷配線板５ａ、５ｂの表面にエラチンブレジス）４
ａ、４ｂを例えばデュポン、［リストン４１２０Ｊ
ドライフィルムを用い、フォト印刷法で形成する。この
時エラチンブレジスｈ４ａ、４ｂの形状は貫通孔３ａ、
３ｂ、ｉりそれぞれ０．１ ｍｍ〜０．５ ｍｍ小さく
する。次いで第４図（ｂ）の如く貫通孔３ａ、３ｂとエ
ラチンブレジス）４ａ、４ｂの位置をそれぞれ合わせて
重ねさらにそれらの上に片面銅張積層板１を重ね、所定
のプレス条件に基いて積層成型を行なって接着し、多層
印刷配線板６とする。次いで第４図（ｅ）の如く多層印
刷配線板６に穴明け、パネルメッキ、回路形成を旅して
最外層に回路を形成した後、エラチンブレジス）４ａの
厚みのほぼ半分の深さまで座ぐり加工を行い、さらにエ
ラチンブレジス）４ｂの厚みのほぼ半分の深さまで同様
に座ぐり加工を行なって、エラチンブレジス）４ａ及び
エラチンブレジス）４ｂを露出させる。次いで第４図（
ｄ）の如く座ぐり加工部７の底面に残ったエラチンブレ
ジス） ４ ａ、４ ｂを５０℃の３ｗｔ％水酸化ナト
リウムを３〜５分間スプレーして剥離除去し、多段の開
口部を有する多層印刷配線板を得た。First, as shown in FIG. 4(a), through holes 3a and 3b are formed in the prepregs 2a and 2b by punching, router machining, or the like. In addition, an eratin brace is formed on the surface of the printed wiring boards 5a and 5b which have a circuit formed on one side) 4
a, 4b, for example, DuPont, [Liston 4120J
It is formed using a photo printing method using dry film. At this time, the shape of the eratin braces h4a, 4b is the through hole 3a,
3b and i are each made smaller by 0.1 mm to 0.5 mm. Next, as shown in FIG. 4(b), the positions of the through holes 3a, 3b and the elatine braces 4a, 4b are aligned and stacked, and then the single-sided copper clad laminate 1 is stacked on top of them, and lamination molding is performed based on predetermined pressing conditions. The multilayer printed wiring board 6 is obtained by bonding. Next, as shown in FIG. 4(e), after drilling holes in the multilayer printed wiring board 6, performing panel plating, and forming a circuit to form a circuit on the outermost layer, a counterbore is formed to a depth of approximately half the thickness of the elatine board 4a. Then, counterboring is performed in the same manner to a depth of approximately half the thickness of the eratine breath 4b to expose the eratine breath 4a and the eratine breath 4b. Next, Figure 4 (
As shown in d), the elatin braces 4a and 4b remaining on the bottom surface of the counterbore processing section 7 were peeled off and removed by spraying 3 wt% sodium hydroxide at 50°C for 3 to 5 minutes, resulting in multilayer printing with multi-stage openings. I got a wiring board.
以上説明したように本発明によれば次の効果がある。 As explained above, the present invention has the following effects.
（１）プリプレグレジンのプレス工程時の流れ出しによ
り、開口部ヘレジンが流入する事を完全に防止でき、高
い歩留で多層印刷配線板が製造できる。(1) It is possible to completely prevent the resin from flowing into the openings due to the prepreg resin flowing out during the pressing process, and it is possible to manufacture multilayer printed wiring boards with a high yield.
（２）通常の多層印刷配線板と同様の材料を使用できる
ので、安価な多層印刷配線板の製造が可能である。(2) Since the same materials as ordinary multilayer printed wiring boards can be used, inexpensive multilayer printed wiring boards can be manufactured.
第１図は本発明の開口部を有する多層印刷配線板の製造
方法を説明するための断面図、第２図及び第３図は従来
の多層印刷配線板の製造方法を説明するための断面図、
第４図は本発明の第２の実施例を説明するための断面図
である。
１・・・・・・銅張積層板、２．２ａ、２ｂ・・・・・
・プリプレグ、３ 、３ ａ 、３ｂ−貫通孔、４．４
ａ 、 ４ ｂ ・旧・・エツチングレジスト、５．
５ａ、５ｂ・・・・・・印刷配線板、６・・・・・・多
層印刷配線板、７・・・・・・座ぐり加工部、８・・・
・・・開口部、９・・・・・・内層回路、１０・・・・
・・凹部、１１・・・・・・印刷配線板、１２・・・・
・・金属レジスト、１３・・・・・・スルーホーノペ
１４・・・・・・銅箔。
代理人 弁理士 内 原 音
第１図
第２図
第３図
第４図FIG. 1 is a cross-sectional view for explaining the method for manufacturing a multilayer printed wiring board having openings according to the present invention, and FIGS. 2 and 3 are cross-sectional views for explaining the conventional method for manufacturing a multilayer printed wiring board. ,
FIG. 4 is a sectional view for explaining a second embodiment of the present invention. 1... Copper-clad laminate, 2.2a, 2b...
・Prepreg, 3, 3a, 3b-through hole, 4.4
a, 4 b - Old... etching resist, 5.
5a, 5b...Printed wiring board, 6...Multilayer printed wiring board, 7...Spot facing part, 8...
...Opening, 9...Inner layer circuit, 10...
・・Recessed portion, 11 ・・Printed wiring board, 12 ・・・
・・Metal resist, 13・・・Through-honope
14...Copper foil. Agent Patent Attorney Oto Uchihara Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
する事により、製造する多層印刷配線板において、前記
接着剤シートに機械加工を行なって所定の形状の貫通孔
を形成する工程と、内層用印刷配線板の表面に前記貫通
孔より一定寸法小さな形状に樹脂層を形成する工程と、
前記貫通孔と樹脂層の位置を合せて前記接着剤シートと
印刷配線板を重ね加熱加圧する事により成形し多層印刷
配線板とする工程と、前記多層印刷配線板を前記樹脂層
の深さまで座ぐり加工を行なって樹脂層を露出させる工
程と、前記樹脂層を除去して開口部を形成する工程とを
含むことを特徴とする多層印刷配線板の製造方法。In a multilayer printed wiring board manufactured by stacking an adhesive sheet between a plurality of printed wiring boards and applying heat and pressure, a step of machining the adhesive sheet to form a through hole of a predetermined shape, forming a resin layer on the surface of the printed wiring board in a shape that is a certain size smaller than the through hole;
A step of forming a multilayer printed wiring board by aligning the through holes and the resin layer and stacking the adhesive sheet and the printed wiring board under heat and pressure, and seating the multilayer printed wiring board to the depth of the resin layer. A method for manufacturing a multilayer printed wiring board, comprising the steps of: exposing a resin layer by boring; and forming an opening by removing the resin layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63113198A JPH0719970B2 (en) | 1988-05-09 | 1988-05-09 | Method for manufacturing multilayer printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63113198A JPH0719970B2 (en) | 1988-05-09 | 1988-05-09 | Method for manufacturing multilayer printed wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01282892A true JPH01282892A (en) | 1989-11-14 |
| JPH0719970B2 JPH0719970B2 (en) | 1995-03-06 |
Family
ID=14606039
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63113198A Expired - Fee Related JPH0719970B2 (en) | 1988-05-09 | 1988-05-09 | Method for manufacturing multilayer printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0719970B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03280495A (en) * | 1990-03-28 | 1991-12-11 | Taiyo Yuden Co Ltd | Electronic component mounting structure and method of packaging |
| JP2007221110A (en) * | 2006-02-16 | 2007-08-30 | Samsung Electro-Mechanics Co Ltd | Method for manufacturing substrate in which cavity is formed |
| JP2008112996A (en) * | 2006-10-27 | 2008-05-15 | Samsung Electro-Mechanics Co Ltd | Method of manufacturing printed-circuit substrate |
| JP2011243751A (en) * | 2010-05-18 | 2011-12-01 | Unimicron Technology Corp | Circuit substrate and manufacturing method thereof |
| CN102487578A (en) * | 2010-12-03 | 2012-06-06 | 欣兴电子股份有限公司 | Circuit board and manufacturing method thereof |
| JP2012529770A (en) * | 2009-06-24 | 2012-11-22 | インテル・コーポレーション | Multi-chip package and method for providing multi-chip package die-to-die interconnects |
| JP2019087722A (en) * | 2017-11-09 | 2019-06-06 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Printed circuit board and method of manufacturing the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SG146460A1 (en) | 2007-03-12 | 2008-10-30 | Micron Technology Inc | Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components |
-
1988
- 1988-05-09 JP JP63113198A patent/JPH0719970B2/en not_active Expired - Fee Related
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03280495A (en) * | 1990-03-28 | 1991-12-11 | Taiyo Yuden Co Ltd | Electronic component mounting structure and method of packaging |
| JP2007221110A (en) * | 2006-02-16 | 2007-08-30 | Samsung Electro-Mechanics Co Ltd | Method for manufacturing substrate in which cavity is formed |
| JP2008112996A (en) * | 2006-10-27 | 2008-05-15 | Samsung Electro-Mechanics Co Ltd | Method of manufacturing printed-circuit substrate |
| US11824008B2 (en) | 2009-06-24 | 2023-11-21 | Intel Corporation | Multi-chip package and method of providing die-to-die interconnects in same |
| US12113026B2 (en) | 2009-06-24 | 2024-10-08 | Intel Corporation | Multi-chip package and method of providing die-to-die interconnects in same |
| JP2012529770A (en) * | 2009-06-24 | 2012-11-22 | インテル・コーポレーション | Multi-chip package and method for providing multi-chip package die-to-die interconnects |
| US11876053B2 (en) | 2009-06-24 | 2024-01-16 | Intel Corporation | Multi-chip package and method of providing die-to-die interconnects in same |
| US10510669B2 (en) | 2009-06-24 | 2019-12-17 | Intel Corporation | Multi-chip package and method of providing die-to-die interconnects in same |
| US10763216B2 (en) | 2009-06-24 | 2020-09-01 | Intel Corporation | Multi-chip package and method of providing die-to-die interconnects in same |
| US10923429B2 (en) | 2009-06-24 | 2021-02-16 | Intel Corporation | Multi-chip package and method of providing die-to-die interconnects in same |
| JP2011243751A (en) * | 2010-05-18 | 2011-12-01 | Unimicron Technology Corp | Circuit substrate and manufacturing method thereof |
| CN102487578A (en) * | 2010-12-03 | 2012-06-06 | 欣兴电子股份有限公司 | Circuit board and manufacturing method thereof |
| JP2019087722A (en) * | 2017-11-09 | 2019-06-06 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Printed circuit board and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0719970B2 (en) | 1995-03-06 |
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