JPH08305599A - Test basis data generating device - Google Patents

Abstract

PURPOSE: To easily generate test data on the basis of real data by sending/ receiving data between a data processing unit and a target device and storing sequentially test basis data to a memory depending on a bus cycle pulse. CONSTITUTION: Plural timing counter circuits 61 are respectively provided to each signal line on a data transfer bus 11 and count a timing clock and generating data at a leading and trailing timing of each signal as a count. The count is returned to a head address of a memory 8a and a count from an address generation circuit 7 is returned to a memory 8b and they are stored in the memories 8a, 8b alternately as synthesized test basis data. Then, data are sent/ received between a data processing unit of a host computer 20 and a target device 12 and the basis data are stored sequentially in the memories 8a, 8b depending on a bus cycle pulse. Thus, timing data can be easily generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test basic data generating device, and more particularly to a test for generating test data of a card such as a PC card or an interface board such as a PCI bus interface board to which a LAN, HDD or the like is connected. In the data generator, it is easy to generate test data based on the actual data when the card or interface board and the host computer are operating, and the amount of data can be reduced, and the test waveform on the tester side can be reduced. The present invention relates to a test basic data generating device that is easy to generate.

[0002]

2. Description of the Related Art A card such as a PC card or a LAN,
A target device to be tested, such as a PCI bus interface board, to which a device such as an HDD is connected, is connected to a host computer or the like by a connector, and data is exchanged with the target device, for example, in bit parallel according to a bus cycle. I do. Each bit signal transmitted at this time includes a data signal, an address signal, a control signal, and the like. Depending on the number of signals transmitted / received in parallel at one time, the number of pins in a PC card is about 68, but that of a memory card, PCI bus, VEM bus, etc. is usually about 32. Some card buses have 16 signal lines. Incidentally, the actual number of pins of the connector is the above-mentioned number of pins plus a larger number of pins.

The test data for such a card, substrate, etc. may be manually created or may be simulated by a host computer to give predetermined input / output data to create test data. Normal,
The circuits mounted on cards, boards, etc. are ROM, R
Memory such as AM and ASIC, gate array, MPU, M
Although there is a controller such as a CU or the like, in the creation of test data by simulation, simulation of each single circuit is performed, these are combined and the entire simulation is performed to create test data.

[0004]

Target devices such as a card to be tested, an interface board, or an interface board to which the device is connected are various types of target devices.
The function has been expanded so that it can be used over the difference of S, and a controller such as a gate array, MPU, MCU, etc., and a memory are provided inside thereof. Therefore, they go beyond a simple information storage device and internally perform a wide variety of data processing comparable to a terminal device. However, the actual operation of the application program on the side of the data processing device to which the target device is attached is unpredictable. Moreover, the test target is the response signal of the target device itself. For this reason, it is not possible to perform a sufficient test with the test data that transmits or receives the test signal based on the response signal.

Test data created by a simulation circuit model for a target device such as a card, an interface board or an interface board to which the device is connected is mainly intended to confirm the basic operation of design specifications. Therefore, it is difficult to create test data corresponding to the operation of the actual application program on the data processing device side on which the card, the board, etc. are mounted. Even if the test data is created in response to the operation of a certain application program by a certain simulation circuit model, it is only a fixed form,
With respect to the test data of a wide variety of application programs, the actual data cannot be reproduced, so that it is the current situation that a highly accurate test cannot be performed. Therefore, there is a part of this type of test data that must be manually created. Also a card,
The circuit mounted on the target device such as the board may include the operation of a logic circuit or controller that cannot be simulated. In such a case, this kind of circuit should be the test target. Since the test data is inevitably manual.

On the other hand, in this kind of test data, the timing relationship between the rise and fall of the address signal and the data signal and the rise and fall of the control signal is an important factor, and the setting of the timing condition is necessary for generating the test waveform. I can't miss it. Conventionally, as an example of this timing data, as shown in FIG.
Each change point (T) from the start to the end of the transfer in (b))
The timings of R ₁ , TR ₂ , TR ₃ , ... Are counted based on the previous change point of the timing clock (see FIG. 9A), and the data corresponding to the counted value (FIG. 9C) is counted. (See) is generated. In such a case, the number of bits corresponding to the distance (period) of the maximum change point, 16 bits in the figure, is required as one data up to the next change point. When performing tests in response to many operating conditions, such timing data leads to an increase in the amount of test data, and until the test program that generates test waveforms is generated by the tester according to various test data. The amount of work tends to increase. An object of the present invention is to solve the above-mentioned problems of the conventional technology, and it is easy to generate test data based on actual data exchanged between the target device and the host computer, Another object of the present invention is to provide a test basic data generating device that can reduce the amount of timing data and can easily generate a test waveform on the tester side.

[0007]

The features of the test data generating apparatus of the present invention for achieving such an object are that it is connected to a data transfer bus between a target device and a data processing device, and Sample clock generation circuit that receives a bus cycle pulse that indicates the reference period of the data transfer and that generates a timing clock of a higher frequency in synchronization with this, and the rise of the signal on the data transfer bus with the bus cycle pulse as the reference. And a first counter that counts a timing clock up to either one of its rising edge and its falling edge, and a timing from one of the rising edge and its falling edge of the signal on the data transfer bus to the other edge of its falling edge and its rising edge. A second counter for counting clocks and a first counter
And a data generating circuit for synthesizing the value of the second counter into one data value and generating it as test basic data, and a memory for storing the test basic data, and between the data processing device and the target device. Data is transferred and the test basic data is sequentially stored in the memory according to the bus cycle pulse. Note that among the collected test data, the response data from the target device such as the card or the interface board becomes the expected value data for the target device in the test data.

[0008]

As described above, the actual transmission / reception data between the target device and the host computer is collected as the test basic data, and the data to be collected includes, for example, the timing relationship between the address signal or the data signal and the control signal. The rising or falling timing is counted based on the bus cycle signal, and the next falling or rising timing is counted based on this rising or falling timing. Can be treated as within the bus cycle period. Therefore, the timing data value can be reduced, and moreover, since the count values are combined to generate the timing data for each cycle, the timing data amount of the test data can be reduced. As a result, basic test data as actual data can be easily collected in a memory with a smaller amount of information for many operating states. If the basic data includes directional data, the transmission data from the data processing device side is output based on this and the actual data, and the received data from the target device side such as the card or interface board is set as the expected value. By doing so, the test data for the target device can be easily generated.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a test basic data generating device of the present invention, FIG. 2 is an explanatory diagram of directionality flag data in the test basic data generating device, and FIG.
5 is an explanatory diagram of cycle flag data in the test basic data generating device, FIG. 4 is a block diagram of a timing counter circuit in the test basic data generating device, FIG.
Is an explanatory diagram of timing data generation of a test data generation circuit, FIG. 6 is an explanatory diagram of a generation method in the case of generating test data from the test basic data, and FIG.
Flow chart of test data generation process and FIG.
Is 4 in 1 bus cycle in the test data generation circuit.
6 is a block diagram of a timing counter circuit that generates edge timing data. FIG. In FIG. 1, the test basic data generation device 10 is connected to a host computer 20 and a connector 11 a that receives a target device 12 to be tested, such as a card such as a PC card, a LAN, a PCI bus interface board to which an HDD is connected. The external storage device 13 is equipped with a memory card, FDD, or the like.

Here, the connector 11a and the connector 11b
For example, in the case of a PC card, 68 pins of 70 pins are internally connected to each other, and a transmission / reception signal is transmitted from each connector to the connector 1 from the connector 11a.
It is connected via the bus 11 so as to pass through to 1b. Therefore, the transmission signal from the host computer 20 is sent to the corresponding pin of the target device 12 corresponding to each pin, and the response signal (return signal) from the target device 12 is sent to the corresponding pin of the host computer 20 corresponding to each pin. To be done. For other cards or buses, the number of pins of the connector 11a and the connector 11b is usually 32 + 2 = 34, but the description thereof is omitted.

The directional flag generating circuit 1 connected to the bus 11 includes a card enable (CE), an output enable (OE), a write enable (WE), and an I / O read among the control signal lines of the bus 11. (IOR), I
Receives output from each signal line of / O write (IOW).
Further, the cycle flag generation circuit 2 receives a wait signal and a timing clock TCLK among the control signals of the bus 11 via the AND gate 2a. The timing clock TCLK (see FIG. 5A) is used in the timing clock generation circuit 3e.
4 clock CLK and system clock S on bus 11
It is generated as a signal synchronized with CLK (see FIG. 5 (b)) or the cycle pulse CYC on the bus 11 (see FIG. 5 (c)). Here, 16 pulses of TCLK are generated in one bus cycle (see FIG. 5 (a)). Here, the control signal is a control signal in the case of being connected to a PC card, and in a memory card, a PCI bus, a VEM bus, or the like, the control signal is a control signal indicating the direction of read or write.
OCHCK, IOCHRDY, IOW, IOR, WRI
Various control signals such as TE, IACK, IACKIN, and IACKOUT are used. However, in the following, the control signal of the PC card will be described as an example in which the control signal is close to the signal on the bus of the microprocessor.

In addition to the directional flag generating circuit 1 and the cycle flag generating circuit 2, the test basic data generating device 10 includes a start condition detecting circuit 3, a power supply voltage detecting circuit 4, an end detecting circuit 5, and a test data generating circuit 6. , An address generation circuit 7, memories 8a and 8b, and a controller 9. The controller 9 internally has a memory card interface or an FDD interface, and alternately transfers the data stored in the memories 8a and 8b to the external storage device 13 and sequentially stores the data. When the stop detection signal is received from the decoder 3c of the start condition detection circuit 3 which will be described later, the data generation operation is stopped and a specific stop code is sent to the memories 8a and 8b that store the test basic data. Then, when the detection signal from the decoder 3c is stopped, the operation is restarted.

The directional flag generation circuit 1 includes four NANDs 1a, 1b, 1c, which receive respective control signals as shown in the figure.
1d and two NANDs 1a and 1b respectively
Two NOR1s that receive the respective outputs of 1c and 1d
e, 1f, and each of the two NORs 1e, 1f has an F level in accordance with the received control signal.
A 2-bit directional flag bit signal of 0 and F1 is generated. This flag bit signal is generated according to the input / output logical relationship shown in FIG. As a result, as shown in FIG. 2 (b), when the host computer 20 is a read (READ) for receiving data from the target device 12, the flag bits F0 and F1 become "10", and the host computer 20 becomes the target device 12. At the time of writing (WRITE) for transmitting data, the flag bits F0 and F1 are "
01 ". Also, the flag bits F0 and F1 are" 1 ".
When it is 1 ”or“ 00 ”, it is indefinite (DONT
CARE) and impossible (UNKOWN).

The cycle flag generating circuit 2 is composed of 16 pulse counters 2b, 128 pulse counters (not shown) and two stages of flip-flops 2c, and receives the control signal, the WAIT signal and the timing pulse TCLK.
In response to this, a cycle flag bit signal for reading or writing 2-bit data of F2 and F3 is generated. This flag bit signal has the relationship shown in FIG.
That is, when the wait (WAIT) signal is "H", the counter 2b counts the timing clock TCLK, the count value is "1", and the output is "1".
At this time, "10" is set in the two flip-flops 2c, the flag bits F2 and F3 are output as "10", and the cycle starts. Then, the counter 2b counts the pulse of the timing clock TCLK. When the count value of the counter 2b becomes "16", "01" is set in the two flip-flops 2c, and the flag bits F2 and F3 are "01".
Is output and the data transfer cycle is stopped, the counter 2b is reset (cleared) according to the output, and returns to the initial value "0". As a result, the next timing clock TCLK is received and the next cycle starts (see FIG. 3 (b)). The counter 2b is reset by the rise of the cycle pulse CP sent from the cycle flag generation circuit 2 to the timing data generation circuit 6 (fifth period).
(See FIG. (D)). The cycle pulse CP is a pulse of one bus cycle (bus cycle pulse CYC) indicating a reference period of data transfer on the bus.
Is a signal corresponding to.

The cycle flag generation circuit 2 generates this as a cycle pulse CP either directly or in synchronization with the timing clock TCLK. The cycle pulse CP generates a timing clock TCLK every 16 pulses, or a bus cycle pulse or a system clock SCLK (see FIG. 5) transmitted onto the bus 11 as shown by a wiring line 2d shown by a dotted line in FIG. (See (b)). For example, when one bus cycle is formed by four system clocks on the bus, the cycle pulse CP may be generated in synchronization with the timing clock TCLK every time four system clocks are counted. Alternatively, the bus cycle pulse CYC may be directly generated as the cycle pulse CP.

By the way, the wait signal is "
Since the AND gate 2a is closed during L ", the timing clock TCLK is not input to the cycle flag generation circuit 2. Therefore, the counter 2b does not count. Also, the wait (WAIT) signal is" H ".
Timing clock TCL when falling from "L" to "L"
K input stops. At this time, flip-flop 2
"11" is set in c, the counter 2b is reset, and the cycle ends (see FIG. 3 (b)). further,
WAIT for a certain period, for example, 8 bus cycles or more
When neither the signal nor the timing pulse TCLK changes, the output from the 128 pulse counter is sent to the flip-flop 2c, and the flag bits F2 and F3 are "11".
Generate the signal. The two-stage flip-flop 2c
Is reset at the rising edge of the cycle pulse CP, and when the value of the counter 2b is other than the above,
Assuming that the data has been reset and the data has been transferred, the flag bits F2 and F3 are sent to the test data generating circuit 6 respectively. As a result, FIG.
As shown in FIG. 6B, each flag bit is sent to the test data generating circuit 6 in response to the data transfer. Regarding the data transmission timing and the reset timing of each flag, after the flag data is established by inserting a delay circuit or the like and the flags F0 to F3 are set in the flag register 60 on the test data generation circuit 6 side, Adjust the timing so that it is reset at the timing.

The start condition detection circuit 3 is composed of a D flip-flop 3a and a 3-input NAND gate 3b, and the power supply voltage detection circuit 4 supplies a power-on detection signal PWO.
When N is input to the NAND gate 3b and becomes "H", the gate is opened as a signal that the power of the card is turned on. One of the other inputs of the 3-input NAND gate 3b is the Q output of the flip-flop 3a, and the other one receives the output of the decoder 3c via the inverter 3d. So these other inputs are usually H
It is at the IGH level (hereinafter "H"). The output of the NAND gate 3b is normally "H",
It becomes significant at "L". The flip-flop 3a is the bus 1
"REG" to select the space of the attribute on 1
Gate of the gate 3
Send output to b. As a result, the NAND gate 3b generates the output signal GTON, which is input to the timing clock generation circuit 3e and the test data generation circuit 6. As a result, it becomes possible to collect data corresponding to the "REG" signal. The application program installed in the host computer 20 starts operating in response to the fall of the signal "REG".

The decoder 3c of the start condition detecting circuit 3 has an F
It is composed of a gate array such as PLA (Field Programmable Logic Array) and is connected to the data line and the interrupt signal line on the bus 11. Then, when special code data is placed on the data line or when a predetermined interrupt signal is generated, it is decoded to generate the output of "H", and the NAND gate 3b is closed. Then, the output signal GTON is stopped and the decode signal is sent to the controller 9. Further, by this, the test data generating operation and the recording operation are temporarily stopped. Further, when a specific code or interrupt for releasing the stop condition is released, the decode output is set to "L" and GTON is lowered to start the test basic data generating operation. The timing clock generation circuit 3e sends a timing clock TCLK synchronized with the cycle pulse CYC on the bus 11 to the test data generation circuit 6 or the like in response to the output signal GTON of the NAND gate 3b.

The power supply voltage detection circuit 4 includes a comparator (C
OM), which receives an input signal from a line connected to the pin of the operating power supply signal Vcc on the bus 11 and compares it with a predetermined reference voltage VREF to detect a power ON signal PWON.
Occurs. This detection signal is sent to the start condition detection circuit 3, the end detection circuit 5, and the test data generation circuit 6.
The end detection circuit 5 is composed of a NAND circuit and has a bus 1
Upon receiving the reset signal of 1 and the detection signal PWON, the end signal CEND is sent to the test data generation circuit 6 according to these AND conditions. The test data generation circuit 6 is
It receives 68-bit data from the bus 11 and generates 9-bit data for each bit as timing data (described later) for a maximum of 68 × 9 = 6 in total.
The 12-bit data and the preceding 4-bit flag data F0 to F3 are added to the 4-bit data to generate a total of 616-bit data corresponding to each bus cycle, and the address generation circuit 7 generates the bit data. The data is output to the memory selected from the memories 8a and 8b in accordance with the indicated address.

The data generation of the test data generation circuit 6 is performed by receiving the timing clock TCLK from the timing clock generation circuit 3e and the enable signal of the AND signal of the inversion signal of the output signal GTON and the inversion signal of the detection signals PWON and CEND. As a result, the gate circuit 6c is generated and the operation is started. And the entered 7
The flag data F0 to F3 of the 2-bit signal is received by the flag register 60 and stored therein.
The signals on the bus 11 are respectively received by 68 timing counter circuits 61, 61, ... Which are arranged in parallel in bit parallel. The output of each timing counter circuit 61 is serially transferred to and set in the 612-bit buffer memory 62, and subsequently, the value of the flag register 60 is serially transferred and set in the buffer memory 62.

Therefore, each unit of 9 bits of the 612 bits of the buffer memory 62 corresponds to the timing data of the signal from each line of 68 bits from the bus 11, and 616 bits from the 613th bit of the buffer memory 62. Each digit up to the digit corresponds to each flag bit corresponding to one bus cycle. The flag bits F2 and F3 stored at the rising edge of the cycle pulse CP are stored.
Is usually a signal of "10" or "11". The 616 bit output of the buffer memory 62 is 32
Cycle pulse C in memories 8a and 8b in bit parallel
According to the timing of P, it is transmitted at the timing of the clock twice the timing clock TCLK.

Now, the timing counter circuits 61 and 6
1, ... Are provided corresponding to the respective signal lines on the bus 11, and by counting the timing clock TCLK, data of the rising and falling timings of each signal are generated as count values. The operation and the internal circuit will be described with reference to FIG. FIG. 4 is a block diagram showing the relationship between the timing counter circuit 61 and the buffer memory 62 that receive a certain signal on the bus 11. The timing counter circuit 61 includes a first edge detection circuit 63 that detects the edge of the first transition point of rising or falling and a second edge detection circuit 63 that detects the edge of the next transition point.
The edge detection circuit 64, the flip-prop 65 of the D-latch, which is set to "1" when it is "H" at the first timing of the input waveform, the timing clock TCL from the generation of the cycle pulse CP to the first edge.
A 4-bit first edge counter 66 that counts the number of K as a timing value, a second edge counter 67 that counts the number of the timing clock TCLK from the first edge detection to the second edge as a timing value, and a 9-bit shift register 68 and a delay circuit 69.

Here, the output value of the flip prop 65 is the MSB (most significant bit), and the first edge counter 6
The output value of 6 is assigned to the lower digit 4 bits, the output value of the second edge counter 67 is assigned to the upper 4 bits, and a total of 9 bits of data are assigned to the shift register 68 corresponding to the digit positions. The falling edge of the 16th pulse of the timing clock TCLK is set in parallel to the digit (see FIG. 5 (f)). Then, the shift register 68 of each timing counter circuit 61 causes the cycle pulse PC
After receiving this data, this data is serially stored in the buffer memory 6
2 is transferred to. The timing data thus transferred is stored in the memory 8 at the timing of the next cycle pulse PC.
a or transferred to the memory 8b and stored.

The first edge detection circuit 63, the second edge detection circuit 64, the flip prop 65, the first edge counter 66, and the second edge counter 67 delay the cycle pulse PC shown in FIG. It is received via and is reset a little later than the rising timing. First edge detection circuit 63 and second edge detection circuit 64
Respectively receive the signal of the predetermined wiring line of the bus 11 at the terminal 70 and detect the change point thereof. The first edge detection circuit 63 is activated when the power is turned on, but the second edge detection circuit 64 and the second edge counter 67 have the first edge detection circuit 63.
It is enabled by the detection signal DA of the edge detection circuit 63, receives the reset signal from the delay circuit 69, and then stops its operation. Therefore, these circuits start the detection operation from the time when this detection signal is generated, and operate until just before receiving the reset signal.

Detection signal DA of the first edge detection circuit 63
Is a first edge counter 66 and a second edge detection circuit 64.
And sent to the second edge counter 67. The first edge counter 66 receives the timing clock TCLK, counts it, stops counting when it receives the detection signal DA of the first edge detection circuit 63, and sends the count value to the shift register 68. At this time, the second edge detection circuit 64 and the second edge counter 67 are operated by the detection signal DA, and the second edge counter 6
7 starts counting the timing clock TCLK, stops the count by the detection signal DA from the second edge detection circuit 64, and sends the count value to the shift register 68.

The flip-flop 65 latches the signal on the bus at the falling timing of the cycle pulse PC, which is a timing slightly after the reset. As a result, the signal on the bus 11 is "H" at the start of the bus cycle.
"1" is set to this and "L"
Is set to "0". Therefore, based on this value, it can be determined whether the signal has risen or has fallen at the time of detecting the first edge. Similarly, it can be determined whether the signal rises or falls at the next second edge detection time point DB. The output of the flip prop 65, the output of the second edge counter 67, and the output of the first edge counter 66 are the cycle pulse P, respectively.
It is set in the shift register 68 at the rising timing of C and transferred to the buffer memory 62. Finally, the data of the flag register 60 is also sent to the shift register 68 of the timing count circuit 61 of the last wiring line and transferred to the buffer memory 62. as a result,
For the waveform of FIG. 5 (e), timing data as shown in FIG. 5 (g) is obtained.

The address generation circuit 7 is provided with a program counter 7a therein, receives the timing clock TCLK from the timing clock generation circuit 3e and the cycle pulse CP from the cycle flag generation circuit 2, and is a clock at a speed double that of the timing clock TCLK. First, a selection signal for the memory 8a and a write control signal CNT are generated in synchronism with, and the program counter 7a is incremented according to the cycle pulse CP to increase the address AD of the memory 8a.
D is generated to access the memory 8a. When data is written up to the final address of this memory 8a,
Selection signal for selecting memory 8b and write control signal CNT
Is generated and the value of the program counter is returned to the head address of the memory 8b. Then, in the same manner as described above, the data is written up to the final address of the memory 8b, the selection signal for selecting the memory 8a and the write control signal CNT are generated again, and the value of the program counter is returned to the head address of the memory 8a. In this way, the memories 8a, 8 are alternately
The synthesized test basic data of 72 bits is stored in b.

The data thus stored is stored in the memory 8a by the controller 9 which receives the PWON signal, the selection signal and the write control signal CNT from the power supply voltage detection circuit 4.
Data is read from the memory side not written in 8b, and the data is sequentially transferred to and stored in the external storage device 13. The test basic data collected as described above is read under the control of the controller 9 by mounting the external storage device 13 on the host computer 20 or the like and reading the data, or by turning on a predetermined switch. Through the bus 11, the data read from the external storage device 13 is sent to the data processing device such as the host computer 20 to which it is attached.

As shown in FIG. 6, the test basic data in 616-bit units stored in the external storage device 13 in correspondence with the bus cycle is composed of 612-bit timing data and 4-bit flag data. The flag bits F2 and F3 recorded at this time are usually "10",
Alternatively, the signal is "11". Data processing device or host computer 2 that has received this test basic data
As shown in FIG. 7, 0 is "01" when the flag data F0 and F1 are discriminated in the write state as shown in FIG. 7, and at this time, control for driving the driver transmitted as test data in step 101 is performed. Generate data. Then, in step 102, the flag bits F2 and F3 are discriminated, and when the flag bits are "10", write control data is generated in step 103, and this is arranged in the test program as test data. Then, of the 616 bits, 612-bit data is divided into 9-bit units, output data having a waveform that rises or falls at each timing is generated as test data, and this is arranged at a predetermined position of the test program. Then, the process returns to step 100 and the above steps are repeated.

On the other hand, if the NO condition is reached in step 102, the process proceeds to step 104, and in this step 104 it is judged whether the flag bits F2 and F3 are "11" by referring to the next 616-bit basic data. If the condition is NO, the process proceeds to step 111. Where YE
When the condition is S, the process returns to step 100 and the above steps are repeated. As a result, flag data F0, F1
Is "01" and flag bits F2 and F3 are "10" and "1".
When it is "1", test data is generated according to the data of 612 bits out of the 616 bits and is arranged in the test program. This is set to flag bits F2 and F3.
Is not "11", or flag bits F0 and F1 are "
Continue until it is not 01 ". And then step 100.
When the flag bits F0 and F1 are "10" in the judgment of
It becomes the next processing.

That is, in step 100, the next test basic data is referred to, and the flag data F0 and F1 are discriminated. When this is the read state, it is "10". At this time, the read control signal is sent in step 106. Generate test data to generate and use as test program data. Then, in step 107, the data that enters the waiting state for the transfer data from the target device 12 is next arranged as test data. Next, in step 108, the flag bits F2 and F3 are discriminated, and when this is "10", in step 109 the 612 bits of the 616 bits of the test basic data are divided into 9-bit units, and at each timing. Output data having a rising or falling waveform is generated as expected value data and placed at a predetermined position in the test program. And
Return to step 100 and repeat the above steps.

On the other hand, if the NO condition is reached in step 108, the process proceeds to step 110, and in step 104, it is determined whether the flag bits F2 and F3 are "11" by referring to the next 616-bit basic data. If the condition is NO, the process proceeds to step 111. Where YE
When the condition is S, the process returns to step 100 and the above steps are repeated. As a result, flag data F0, F1
Is "10" and flag bits F2 and F3 are "10" and "1".
When it is "1", test data is generated according to the data of 612 bits out of the 616 bits and is arranged in the test program. This is set to flag bits F2 and F3.
Is not "11", or flag bits F0 and F1 are "
Continue until it is not 10 ". Of course, step 10
When the flag bits F0 and F1 are "01" in the determination of 0, the processes in steps 101 to 104 are performed.

In step 110, F2 and F3 are "1".
If YES in the determination of "1", control data that compares the transfer data with the transfer data and stores the result in a predetermined storage location is also arranged if necessary. Is generated or other processing is performed.
Process to generate test data individually or perform other process. As other processing, if necessary, the processing returns to step 100 again to continue the processing.

In this way, test data is generated from actual data. In principle, the above processing is automatically converted by a program, but it may be generated manually. Therefore, a test device is provided in place of the external storage device 13, the generated test data is stored in an external storage device such as an FD storage device provided in the test device, and the test device is used to store the target device 12 or the host computer 20. You can connect them to do these tests. In the above case, the target device 1
In No. 2, the programs installed in it have been checked as correct programs. It has also been checked that there is no error in the operation of each circuit of the target device 12. The target device 12 as described above may be inspected in the same direction as the conventional one. You may use what tested each circuit individually. Further, each circuit may be tested by simulation. By using such a correct target device, test data can be easily generated in a form close to actual data.
Based on the correct target device tested in this way, it is possible to easily generate more accurate test data, which is more realistic than the conventional simulation, for each application program.

FIG. 8 shows a concrete example of the timing counter circuit 61a for detecting four edges. The timing counter circuit 61a is a timing counter circuit 61a.
In addition to the above circuit, a third edge detection circuit 63a that detects the edge of the third rising or falling transition point and a fourth edge detection circuit 64a that detects the edge of the fourth transition point, Corresponding to these edge detection circuits, a third edge counter 66a and a fourth edge counter 67
a and are provided. The third edge detection circuit 63a and the third edge counter 66a include a second edge detection circuit 64.
The third edge counter 66a starts counting the timing clock TCLK, stops the counting in response to the detection signal of the third edge detecting circuit 63a, and shifts the count value to the shift register 68.
Send to a.

The fourth edge detection circuit 64a and the fourth edge counter 67a are enabled by the detection signal of the third edge detection circuit 63a, and the fourth edge counter 67a is activated.
Starts counting the timing clock TCLK, stops the counting in response to the detection signal of the fourth edge detection circuit 64a, and sends the count value to the shift register 68a. Further, it receives the cycle pulse PC via the delay circuit 69 and is reset a little later than the rising timing thereof, and thereafter stops its operation. The shift register 68a is a 17-bit register, receives the output of the flip-prop 65 at its MSB, and the value of the third edge counter 66a is at the 9th to 12th bits, and at the 13th to 16th bits. The value of the fourth edge counter 67a is set in parallel.

The relationship between the controller 9, the decoder 3c of the start condition detection circuit 3, and the test basic data will be described. For example, an interrupt signal is sent from the target device 12 to the host computer 20 on the bus 11. When this occurs, the decoder 3c detects this and stops the generation of the timing clock TCLK, and the controller 9 receives this detection signal to stop the operation of the test data generation circuit 9 and transfers the stop code to the memory 8a or 8b. And remember. When an interrupt acceptance signal is output from the host computer 20 to the target device 12, the decoder 3c detects this and stops the decoding signal to cause the controller 9 to restart the operation, generate the timing clock TCLK, and restart the operation. Start collecting data for. Such temporary suspension and resumption of data is also performed when a code is generated on the bus 11 such that the data is not transferred for a while. As a result, test data can be generated only in an effective bus cycle, and the amount of collected test data can be reduced. It should be noted that the stop code is converted into specific test data such as a wait loop when this occurs when the test data is generated.

As described above, in the embodiment, as the timing data, 9-bit data is used to indicate whether the first signal is the rising state or the falling state, but this is the same as the timing of the first edge. As data of 8-bit state change at the timing of the second edge only,
It may be possible to judge whether the first edge is rising or falling from the flow of data by program processing or the like.
Therefore, it is not necessary to add 1 bit to 8 bits to make 9 bits. In the embodiment, the target device may be loaded with an application program in addition to the basic program for testing. However, the present invention may be a target device in which a basic operation program or the like is simply installed, as long as the condition that the target device operates is sufficient. Of course, an application program may be installed in this.

The number of bits transferred by the target device is determined according to the system, and is not limited to 68-bit data. Therefore, the number of bits of the test basic data is not limited to 616 bits.
In particular, with a bus having 32 wiring lines, it is possible to generate test data with a smaller number of bits. Then, the flag generated by the directional flag or cycle flag generation circuit is
Although bits are allocated, more flags may be allocated as spares. In particular, when the number of transfer bits is small, the number of bits assigned to this can be increased. The generation circuit of the directional flag and the cycle flag can be composed of various logic circuits.

The direction flags of the embodiment are card enable (CE), output enable (OE),
Write enable (WE), I / O read (IOR),
It is generated by receiving the output from each signal line of I / O write (IOW). In memory cards, PCI buses, VEM buses, etc., this is IOCHCK, which is a control signal indicating the direction of read or write. IOCHRDY, IOW, I
OR, WRITE, IACK, IACKIN, IACK
It is generated according to various control signals such as OUT.

[0041]

According to the present invention, the actual transmission / reception data between the target device and the host computer is collected as the test basic data, and the data to be collected is, for example, the timing of the address signal or the data signal and the control signal. The rise or fall timing is counted based on the signal of each bus cycle including the relationship, and the next fall or rise timing is counted based on this rise or fall timing. The value of the count value of can be treated as within the bus cycle period.
Therefore, the timing data value can be reduced, and moreover, since the count values are combined to generate the timing data for each cycle, the timing data amount of the test data can be reduced. As a result, basic test data as actual data can be easily collected in a memory with a smaller amount of information for many operating states.

[Brief description of drawings]

FIG. 1 is a block diagram of a test basic data generating device of the present invention.

FIG. 2 is an explanatory diagram of directionality flag data in the test basic data generating device, and FIG. 2 (a) is an explanatory diagram showing a relationship between an input signal and an output signal thereof.
(b) It is explanatory drawing of the function of the flag bit.

FIG. 3 is an explanatory diagram of cycle flag data in the test basic data generation device, (a) is
It is explanatory drawing of the function of the flag bit, and (b) is explanatory drawing of the relationship with the data transfer.

FIG. 4 is a block diagram of a timing counter circuit in the test basic data generation device.

FIG. 5 is an explanatory diagram of timing data generation of a test data generation circuit.

FIG. 6 is an explanatory diagram of a generation method when generating test data from test basic data.

FIG. 7 is a flowchart of a test data generation process.

FIG. 8 is a block diagram of a timing counter circuit that generates timing data of four edges in one bus cycle in the test data generation circuit.

FIG. 9 is an explanatory diagram of timing data generation of a conventional test basic data generation device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Directional flag generation circuit, 2 ... Cycle flag generation circuit, 3 ... Start condition detection circuit, 4 ... Power supply voltage detection circuit, 5
... End detection circuit, 6 ... Test data generation circuit, 7 ... Address generation circuit, 8a, 8b ... Memory, 9 ... Controller, 10 ... Test basic data generation device, 11a, 11b
... Connector, 12 ... Target device, 13 ... External storage device, 20 ... Host computer, 61 ... Timing counter circuit, 62 ... Buffer memory, 63 ... First edge detection circuit, 64 ... Second edge detection circuit, 65 ... Flip prop , 66 ... First edge counter, 67 ... Second edge counter, 68 ... Shift register, 69 ... Delay circuit.

Claims (3)

[Claims] 1. A data transfer bus between a target device and a data processing device, which receives a bus cycle pulse indicating a reference period of data transfer on the data transfer bus and synchronizes with the bus cycle pulse to transmit a higher frequency signal. A sample clock generating circuit for generating a timing clock; a first counter for counting the timing clock up to either one of the rising edge and the falling edge of the signal on the data transfer bus with the bus cycle pulse as a reference; A second counter that counts the timing clock from one of the rising edge and the falling edge of the signal on the data transfer bus to the other of the falling edge and the other edge of the rising edge; and a first counter and a second counter. Generate values as test basic data by combining values into one data value A data generating circuit and a memory that stores the test basic data are provided, and data is transferred between the data processing device and the target device, and the test basic data is sequentially stored in the memory according to the bus cycle pulse. Test basic data generator. 2. A data transfer bus is further connected,
The target device includes a directional signal generation circuit that generates a signal indicating a transfer direction of the data or data indicating a transfer direction in accordance with a signal corresponding to control data among the data transfer signals on the bus. , A card or an interface board, wherein the data generating circuit uses the output data of the directional signal generating circuit as the test basic data in addition to the test basic data. apparatus. 3. A data transfer bus is further connected,
2. The test basic data generating apparatus according to claim 1, wherein the valid bus cycle is detected according to a signal corresponding to a data transfer signal on the bus, and the data generating circuit is operated only during the valid bus cycle.