KR0146519B1 - Interrupt bus data pattern extracting apparatus of computer system - Google Patents

Abstract

The present invention relates to an interrupt bus data pattern extraction apparatus for a computer, comprising: a data register for storing a desired data pattern; A data pattern identity determination unit; A trace memory unit for latching and storing data of a system bus; A trace memory address generation section for providing the trace memory section with an address where the latched data is stored; A match address storage unit for storing a corresponding address generated in the trace memory address generator; And a data trace unit for tracing data of the corresponding address stored in the trace memory unit.

The present invention provides a function to find the data pattern of the interrupt bus, so that the interrupt bus signals can be interpreted more accurately, which can be very useful for the user to analyze and debug the system in the development and maintenance of the computer system. have.

Description

Interrupt Bus Data Pattern Extractor for Computer System

1 is an overall configuration diagram of a general bus-based multiprocessor computer system

2 is a block diagram showing the main block of the bus analyzer

3 is a block diagram of a block for interrupt bus analysis.

4 is a detailed configuration diagram of a function control module which is an essential part of the present invention.

Figure 5 shows the ICC Bus Short Message Format.

6 is a state machine of the data pattern identity determination unit.

The present invention relates to a system bus analyzer of a computer system, and more particularly, to an interrupt bus pattern finder having a function of finding an interrupt bus data pattern of a system bus.

The system bus analyzer stores the state of a series of bus signals on a bus during certain bus cycles when the computer system is operating a bus, such as reading and writing data over the system bus, and then displaying them as needed to show the operation of the system. Allows you to analyze This can be very useful to developers or maintainers when developing systems or maintaining them. It's like extending the functionality of the Logic Analyzer. Especially in large medium and larger systems, the system bus often uses a system-specific bus. In this case, a bus analyzer is created and used by system developers. Because the logic analyzer is not only expensive equipment, it is difficult to observe all signal lines on the bus at the same time due to the limited number of channels, and it is inconvenient to install and move. Therefore, by making and using a dedicated bus analyzer board that can be mounted on the bus like other boards to analyze the bus condition, it is easy to install and move, and it is easy to check and check all signal lines defined on the system bus. In addition, the cost is very low compared to general logic analyzer.

Although the system bus analyzer used in the main computer III for the administrative computer network has a data transfer bus (DTB) pattern search function, the interrupt bus data pattern search function is not implemented. The problem caused by the lack of the above functions is that it is difficult to analyze the interrupt bus protocol because it is difficult to find the desired data pattern. Second, it is difficult to predict the system performance. Third, it is difficult to cope with system errors. Difficulty can be mentioned.

Therefore, the data pattern search apparatus on an interrupt bus according to the present invention provides a function of finding a data pattern of a desired interrupt bus, and provides the user with more accurate control and interpretation of interrupt bus signals. To help you analyze and debug your system.

SUMMARY OF THE INVENTION The present invention has been made to overcome the above-mentioned problems and achieve the above object, and the data bus pattern extraction apparatus of the interrupt bus of the computer system bus according to the present invention stores a specific data pattern to extract specific interrupt bus data. A data register; A data pattern identity determination unit that determines the identity of the specific data of the data register and the interrupt bus data latched in synchronization with a bus clock; A trace memory unit for latching and sequentially storing data on an interrupt bus in synchronization with a system bus clock until the data pattern identity determination unit determines that data is the same; A trace memory address generation unit for providing the trace memory unit with an address where the latched data of the interrupt bus is stored until the data pattern identity determination unit determines that the data is the same;

A match address storage unit for storing a corresponding address generated in the trace memory address generation unit when it is determined that the data is identical by the data pattern identity determination unit; And a data trace unit which reads an address stored in the match address storage unit and traces data of a corresponding address stored in the trace memory unit.

And in the data bus pattern extracting device of the interrupt bus of the computer system bus, the data pattern identity determining section sets the steps of the bus cycles constituting the interrupt bus transfer protocol as states, and whether each step of the bus cycle satisfies the bus protocol. The state to be transitioned is determined, and is characterized in that it consists of a state machine which determines the identity by comparing with the data pattern recorded in the data register in the state of indicating the interrupt vector transfer cycle.

In the data bus pattern extraction apparatus of an interrupt bus of a computer system bus, the data register further includes a mask register for masking bits of each bit constituting a data pattern to be extracted bit by bit. do.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, the overall configuration of a medium computer system to which the present invention is applied is the same as that of FIG. 1 and includes a processor board 12, a memory 13, an input / output processor board 14, and a bus state analyzer board on the backplane bus 11. 15) can be mounted. The system uses a bus-based backplane system bus in which the boards that make up the system are plugged into slots in the backplane to perform their own functions. At this time, the bus analyzer board to which the present invention is applied is inserted into a slot of the backplane to analyze the interrupt bus signal among the system bus signals on the backplane.

2 is a block diagram illustrating the overall configuration of the bus analyzer. Reference numeral 21 denotes a terminal, 22 a central processing unit (CPU), 23 a memory controller, 24 a trace memory, 25 a bus interface, and 26 a system bus. The operation of FIG. 2 is briefly described as follows. When the user inputs a command to start the trace of the system bus 26 data through the terminal 21, the central processing unit 22 interprets the input command and transmits it to the memory unit 23. The memory controller 23 opens the path buffer of the bus interface 25 according to the trace start command of the central processing unit 22 so that the data of the system bus 26 can reach the trace memory 24. The memory controller 22 sends address information and a recording signal to the trace memory 24 so that the data of the system bus 26 are sequentially written to the trace memory 24. If a trigger occurs in the middle of the trace, the memory controller 23 stops the generation of the write signal to the trace memory unit 24 and closes the path buffer of the bus interface 25. The central processing unit 22 displays data stored in the trace memory 24 on the terminal according to the user's request, and the user analyzes the state of the system bus 26 through the terminal.

FIG. 3 shows the configuration of blocks of an apparatus for analyzing an interrupt bus including the present invention among the bus analyzers. Reference numeral 300 denotes a data trace unit, 310 denotes a function control module, 320 denotes a trace memory unit, 330 denotes a TPG (Timming Pulse Generator) module, and 340 denotes a bus interface module. The data trace unit 300 reads an address in which the interrupt data pattern to be extracted is stored and traces data of the corresponding address stored in the trace memory unit 320, and the trace memory unit 320 matches a match signal. It stores the data on the latched interrupt bus at every interrupt bus clock until is enabled. The TPG module 330 receives the system bus clock from the system bus and generates timing pulses based on the system bus clock to provide the function control module 310 and the bus interface module 340. In addition, the bus interface module 340 converts a BTL signal of a system bus into a TTL signal.

Meanwhile, the detailed configuration of the function control module 310 of FIG. 3, which is a main part of the present invention, is the same as that of FIG. 4 and its function is as follows. Reference numeral 400 is an interrupt vector match (IV_MAT) module, 410 is a trace memory address generator, and 420 is a match address storage unit.

The IV_MAT (400) module has an internal register that can read and write the interrupt vector value to be searched by the CPU, and compares the interrupt vector value coming through the interrupt bus of the system bus with the value of the recorded internal register. By sending the match signal to the trace memory address generation unit 410, the bus cycle having the interrupt vector value to be searched can be found.

The trace memory address generation unit 410 generates and provides address and time information in the trace memory, and receives a match signal from the IV_MAT 400 module to be matched to the match address storage unit 420. The address at the time and the Cntl signal are sent so that the address in the trace memory in which the interrupt vector value to be searched is stored is stored in the match address storage unit 420.

The match address storage unit 420 receives an address and a Cntl signal when a match is received from the trace memory address generation unit 410 module, stores it in an internal register, and stores the stored address when the processor needs it. Give it. Then, the processor reads the register value and finds the address of the trace memory in the trace memory where the interrupt vector to be found is displayed on the monitor.

Meanwhile, the IV_MAT module 400, which is a core part of the present invention, will be described in more detail. The IV_MAT module 400 includes a mask register 440 and a data register 430, and includes a data identity determining unit 450 including a state machine operated in synchronization with an interrupt bus clock ICLK. In the state machine of the data identity determining unit 450, the signal coming from the system bus is compared with the values of the two registers to generate a Match signal.

The mask register 440 is composed of 8 bits. The mask register 440 functions to mask a data pattern value to be searched among the interrupt bus signals in bit units. When the mask register 440 is '1', the mask register 440 is masked. The data register 430 stores an interrupt vector value to be searched and consists of 8 bits. The address is VMask [7..0]: 0x80008 and VData [7..0]: 0x8000C. These registers are selected by the data being written by the processor and the 'VMrSel' and 'VDrSel' signals enabled by the address decoder. The contents of these registers become the actual value of the data pattern to be searched for in the interrupt signal, and are compared with data coming on the bus every clock.

The state machine of the data identity determination unit 450 monitors the data flow state on the interrupt bus and analyzes the bus protocol of the interrupt bus. The protocol of the interrupt bus can be divided into two parts, one for interrupt bus arbitration and the other for data transfer, that is, interrupt vector transmission. In the case of the vector transfer cycle during the protocol of the interrupt bus, the value of the data register is compared with the vector value currently being transmitted on the bus, and if it is the same, a match signal is sent to the trace memory address generator 410 to indicate that a trigger has occurred. The synchronous clock is set to the interrupt clock (ICLK) and operates even if the ICLK is variable.

The system used in one embodiment of the present invention uses a US Intel product (Model: Intel 82489DX) as the interrupt bus interface controller device. The Intel 82489DX interrupt controller device uses an Interrupt Control Communication Bus (ICC) bus. The ICC bus is a 5-wire synchronous bus connected to the 82489DX, of which 4-wire is used for data transfer and arbitration, and the other is used as a clock. There are two types of message formats used on the ICC bus, a short message format and a long message format, which are intended to be applied to the short message format. The short message format has a transmission length of 21 cycles and the sequence according to the transmission protocol for each cycle is shown in FIG. The first four cycles are arbitration cycles for the use of the ICC bus, the fifth cycle represents the mode of use mode, the sixth cycle represents the control bits, the seventh to eighth cycles are vector transfer cycles, and the 9-16th cycle is The 17th is a checksum, the 18th is a post amble, the 19th is reception, and the 20-21 is an IDLE status.

On the other hand, in the interrupt bus protocol based on the short message format, the state constituting the state machine for finding the desired interrupt vector value is composed of 13 states, as shown in FIG. Each state is described as follows.

-IDLE status: Search for post amble cycle in ICC bus message format (ICCB [3..0] == HF)

-ACCP Status: Check the Accept cycle of the ICC bus message format. (ICCB [3..0] == H8)

-IDLE1 status: Check if IDLE1 cycle is in ICC bus message format. (ICCB [3..0] == H0)

-IDLE2 status: Check if IDLE2 cycle is in ICC bus message format. (ICCB [3..0] == H0)

-ARB1 status: Checks the first arbitration cycle of the ICC bus message format. The ICCB [3..0] value must not be zero.

-ARB2 status: A status that identifies the second arbitration cycle of the ICC bus message format. The ICCB [3..0] value must not be zero.

-ARB3 status: The third arbitration cycle of the ICC bus message format is acknowledged. The ICCB [3..0] value must not be zero.

ARB4 state: The fourth arbitration cycle of the ICC bus message format is acknowledged. The ICCB [3..0] value must not be zero.

-DM status: Nothing is done, but it must go through this status in order to match the protocol and then move on to the next cycle.

-CNTL state: Nothing is done, but it must go through this state in order to match the protocol and then move on to the next cycle.

-VEC1 state: Compared with the data coming from the ICC bus and the contents of the internal register VDr [7..4], if it is OK, the internal signal m11 is driven high and then transitions to the VEC2 state. But if it is not OK, it will transition to IDLE state.

-VEC2 state: Compared with the data coming from the ICC bus and the contents of the internal register VDr [3..0], if it is OK, the internal signal m10 is driven high and then transitions to the VEC2 state. But if it is not OK, it will transition to IDLE state.

-Finish state: In this state, internal signals are initialized and then transferred to IDLE state.

The operation of the state machine will be described based on the state of the state machine described above. First, the state machine polls while waiting for the post amble cycle of ICC bus message format in IDLE state, and then transitions to ACCP state when the hexadecimal value F (HF) enters the ICCB [3..0] bus. The ACCP state checks the accept cycle and goes to the IDLE1 state when H8 enters the ICCB [3..0] bus, otherwise goes to the previous state IDLE state. If ICCB [] == H0 in IDLE1 state, it goes to IDLE2 state. If ICCB [] == H0 in IDLE2 state, it goes to ARB1 state. If ICCB [] == H0 in IDLE1 and IDLE2 state, go back to IDLE state. The ARB1 state, meanwhile, indicates that the interrupt bus has initiated an arbitration cycle, so the ICCB [] value must not be H0 and then transition to ARB2. ARB2, ARB3, and ARB4 operate similarly to the ARB1 state, and transition to the DM state if the transition condition is met. In DM state, it unconditionally transitions to CNTL state and then to VEC1 state. In the VEC1 state, when the contents are the same (OK) in comparison with the data coming from the ICC bus and the contents of the internal register VDr [7..4], the internal signal m11 signal goes high and then transitions to the VEC2 state. If the contents are not the same (Not OK), the state goes back to the IDLE state. In the VEC2 state, compare the data coming into the ICC bus and the contents of the internal register VDr [3..0], and if it is OK, set the m10 signal high and send the match signal to the match address storage unit 420 in the IV-MAT module. The trace memory addresses at the end and finish are stored in the Tr / Fr registers. Looking at the m11 signal in VEC2 state and transitioning to the FINISH state, the process of finding the desired interrupt vector value is over. In the FINISH state, internally used signals are initialized and then go back to the IDLE state to start searching for another interrupt vector value.

As described above, the apparatus for finding an interrupt bus pattern of a computer system according to the present invention provides a function for finding a data pattern of a desired interrupt bus, and provides the user with more accurate control and interpretation of interrupt bus signals. It helps the user to analyze and debug the system. This provides a useful tool in the development and maintenance of medium computers.

Claims (3)

An apparatus for extracting a data pattern of an interrupt bus of a computer system bus, comprising: a data register (400) for storing a data pattern of interrupt bus data; A data pattern identity determination unit 450 which determines the identity of the data pattern stored in the data register and the interrupt bus data latched in synchronization with a bus clock; A trace memory unit 320 for latching and sequentially storing data on an interrupt bus in synchronization with a system bus clock until the data pattern identity determination unit determines that data is the same; A trace memory address generation unit (410) which provides the trace memory unit with an address where the latched data of the interrupt bus is stored until the data pattern identity determination unit determines that the data is the same; A match address storage unit (420) for storing a corresponding address generated in the trace memory address generation unit when the data pattern identity determination unit determines that data is identical; And a data trace unit 300 which reads an address stored in the match address storage unit and traces data of a corresponding address stored in the trace memory unit. Data pattern extraction device. The state of claim 1, wherein the data pattern identity determination unit 450 sets the stage of the bus cycle constituting the interrupt bus transfer protocol to state, and states that each stage of the bus cycle satisfies the bus protocol. Is determined, and the state of the interrupt bus on the computer system bus is characterized in that the state of the step of indicating the interrupt vector transfer cycle is determined by comparing with the data pattern recorded in the data register. Data pattern extraction device. The computer system bus of claim 1, wherein the data register 430 further includes a mask register 440 for masking bits of each bit constituting a data pattern to be extracted. Data bus pattern extraction device on interrupt bus.