JPH08137720A - Test base data generation device and test data generation method - Google Patents

Abstract

PURPOSE: To generate test data of high reliability even if a simulation circuit model is not formed by permitting a data processor to operate a PC card, transferring data between them and storing test base data in memories. CONSTITUTION: Directional signal generation circuits 1 and 2 are connected to a data transfer bus 11 between the PC card 12 and the data processor 20. A signal showing the transfer direction of data or data showing the transfer direction are generated in accordance with control data among data transfer signals on the bus. A data generation circuit 6 receives the outputs of the directional signal generation circuits 1 and 2 and the data transfer signal and emits data obtained by adding directional data to transfer data from the signals or the signal and data as test base data. At that time, the data processor 20 operates the PC card 12, data is transferred between them and test base data are stored in memories 8a and 8b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test basic data generating device and a test data generating method.
The present invention relates to a test data generating apparatus for generating test data of a PC card, which is easy to generate test data based on actual data when the PC card is operating.

[0002]

2. Description of the Related Art A PC card is connected to a host computer or the like by a connector and, for example, 20 MH.
Data is exchanged in 68 bits in parallel with z. One bit is assigned to each bit signal transmitted at this time in 10 cycles (10 vectors), each bit is modulated by the modulation circuit on the transmission side, and each bit is demodulated by the demodulation circuit on the reception side. PC cards have 68-pin terminals (actually, two more pins are provided.) Among them, IC memory cards and I / O cards are address pins, data pins,
Allocation positions of control pins and the like are almost the same, but some control pins have different contents. However, "RE that selects the attribute space that indicates the attribute of each card"
The control signal pin for G "is assigned to the same pin.

The test data for such a PC card may be manually created or may be created by simulating an internal circuit by a host computer and giving predetermined input / output data. Usually a PC
Circuits mounted on the card include memories such as ROM and RAM and controllers such as ASIC, gate array, MPU, MCU, etc. However, in creating test data by simulation, simulation of each single circuit is performed. Are synthesized and the entire simulation is performed to create test data.

[0004]

Due to the miniaturization of controllers such as gate arrays, MPUs, MCUs, etc., and improvement in memory capacity, PC cards have a wide variety of types that go beyond mere information storage devices and are comparable to terminal devices. Since various data processing can be internally performed, the actual operation of the application program on the data processing device side in which the PC card is mounted cannot be predicted. Moreover, the test target is
This includes a transmission / reception circuit, a modulation circuit, and a demodulation circuit built in the PC card, and the response signal itself and the like are also the test object. For this reason, it is not possible to perform a sufficient test with the test data that is transmitted or received based on the response signal from the PC card.

The test data created by the simulation circuit model for such a PC card is mainly for confirming the basic operation of the design specifications, and the actual application on the side of the data processing device in which the PC card is mounted. It is difficult to create test data corresponding to the operation of the program. Even if test data is created according to the operation of an application program by a certain simulation circuit model, it is only a fixed form, and the actual data cannot be reproduced for the test data of various application programs. However, the current situation is that accurate tests cannot be performed. And, in this kind of test data, there remains a part where the test data must be manually created.
In addition, the circuit mounted on the PC card may include an operation of a logic circuit or controller that cannot be simulated. In such a case, this type of circuit is a test target. The test data is inevitably manual.

The test data must be manually created by a person referring to the circuit diagram and considering a combination of the test data so as to meet a predetermined file format, which requires a lot of work time. Moreover, it is difficult to create special test data or test data that needs to be exchanged with the PC card for a long time in the actual work, and some of them are excluded. In such a case, the accuracy of the test data actually used falls. Moreover, in the case where the test is manually performed, an error often occurs in the created test data, and the check is difficult. In the case of completely manual operation, it is difficult to create test data based on the operation unique to each mounted circuit, so normally test data is created based on the overall operation. . As a result, the accuracy of the created test data is not sufficient for each circuit. An object of the present invention is to solve such a problem of the conventional technique, and to generate test basic data which can efficiently generate highly reliable test data without forming a simulation circuit model. An object is to provide an apparatus and a method of generating test data.

[0007]

The features of the test data generating apparatus of the present invention for achieving such an object are as follows.
A signal indicating a data transfer direction or data indicating a transfer direction is connected to a data transfer bus between the C card and the data processing device, and a data transfer direction signal or a data transfer direction signal is transmitted in accordance with a signal corresponding to control data among data transfer signals on the bus. Generates a directional signal generation circuit, receives the output of this directional signal generation circuit and a data transfer signal, and generates these signals or data obtained by adding the directional data to the transfer data from these signals and data as test basic data. And a memory for storing the test basic data, and the data processing device operates the PC card to transfer data between them to store the test basic data in the memory.

Further, in the test data generating method of the present invention, in the above configuration, the data processing device operates the PC card to transfer data between them to store the data in the memory, The data sent to the PC card is used as the send data in the test data, and the response data from the PC card is used as the expected value data in the test data by referring to the directional data from the data of 1.

[0009]

As described above, in order to use the data actually exchanged with the PC card as the basic data for the test, the actual PC
When the card is operated, a predetermined application program is activated to operate the data processing device, transmission / reception is performed with the data processing device, directional data indicating the transfer direction of the data is generated from this data, and this data is generated. Provide a device to synthesize with real data. As a result, various transmission data regarding the operation of the application and response data thereto can be collected together with the direction data by simply activating the PC card. Therefore, it is possible to easily collect the basic test data as actual data in the memory without simulating the built-in circuit of the PC card.
Since this basic data includes the directional data, the transmission data on the data processing device side is output by this and the actual data, and the test data is easily generated by using the received data from the PC card side as the expected value. You can do it.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a test basic data generating device of the present invention, FIG. 2 is an explanatory diagram of directionality flag data in the test basic data generating device, and FIG.
FIG. 4 is an explanatory diagram of the cycle flag data in the test basic data generating device, FIG. 4 is an explanatory diagram of a generating method when generating test data from the test basic data, and FIG. 5 is a flowchart of the test data generating process. . In FIG. 1, a test basic data generation device 1
Reference numeral 0 has a connector 11a for receiving the PC card 12, and a connector 11b connected to the host computer 20, and a memory card or FDD is mounted as the external storage device 13. Here, the connector 11a and the connector 11b are internally connected with 68 pins out of 70 pins respectively corresponding to each other, and are connected via the bus 11 so that a transmission / reception signal is passed through from the connector 11a to the connector 11b. Has been done. Therefore, the transmission signal from the host computer 20 is sent to the corresponding pin of the PC card 12 corresponding to each pin,
A response signal (return signal) from the card 12 is sent to the corresponding pin of the host computer 20 for each pin.

The directional flag generating circuit 1 connected to the bus 11 includes a card enable (CE), an output enable (OE), a write enable (WE), and an I / O read among the control signal lines of the bus 11. (IOR), I
Receives output from each signal line of / O write (IOW).
Further, the cycle flag generation circuit 2 receives a wait signal of the control signal of the bus 11 and the system clock CLK via the AND gate 2a. The system clock CLK is supplied to the bus 1 by the clock generation circuit 14.
The data signal on 1 is detected under the OR condition and generated as a signal synchronized with this.

The test basic data generator 10 includes a start condition detection circuit 3, a power supply voltage detection circuit 4, an end detection circuit 5, and a vector data generation circuit 6 in addition to the directional flag generation circuit 1 and the cycle flag generation circuit 2. , An address generation circuit 7, memories 8a and 8b, and a controller 9. The controller 9 has a memory card interface or an FDD interface inside, and alternately transfers the data stored in the memories 8a and 8b to the external storage device 13 and sequentially stores the data. The directional flag generation circuit 1 includes four NANDs 1a, 1b, 1c and 1d for receiving respective control signals and two NORs 1e for receiving respective outputs of two NANDs 1a, 1b and NANDs 1c, 1d. , 1f, and generates 2-bit directional flag bit signals F0 and F1 to the two NORs 1e and 1f in accordance with the received control signal. This flag bit signal is generated according to the input / output logical relationship shown in FIG. As a result, as shown in FIG. 2B, when the host computer 20 is a read (READ) for receiving data from the PC card 12, the flag bits F0 and F1 are "1".
0 ", and the host computer 20 sets the PC card 12
In the case of a write (WRITE) for sending data to, the flag bits F0 and F1 become "01". Further, when the flag bits F0 and F1 are "11" and "00", respectively, they are indefinite (DONT CARE) and disabled (UNKOW).
N).

The cycle flag generating circuit 2 is also composed of 10 pulse counters 2b, 80 pulse counters (not shown) and two stages of flip-flops 2c, and outputs the received control signal, WAIT signal and synchronization signal SYN. According to F2
, F3 generate a cycle flag bit signal when reading or writing 2-bit data. This flag bit signal has the relationship shown in FIG. That is, when the wait (WAIT) signal is "H", the counter 2b counts the synchronous clock SYN, and when the count value is "1" and its output is "1", the two flip-flops 2c receive "10". "" Is set and the flag bits F2 and F3 are output as "10" to start the cycle. Further, the counter 2b counts the pulse of the synchronous clock SYN. The output of the counter 2b is "1"
When it becomes "0", the two flip-flops 2c receive "0".
1 "is set and rag bits F2 and F3 are set from these.
Is output as "01" and the data transfer cycle is stopped, the counter 2b is reset (cleared) in response to the output and returns to the initial value. As a result, the next cycle starts after receiving the next synchronous clock SYN. At the same time, a unit pulse PU indicating a data unit in which 1-bit data is transferred is generated with 10 pulses as one unit, and the unit pulse PU is sent to the vector data generation circuit 6. Since the AND gate 2a is closed while the wait (WAIT) signal is "L", the synchronous clock SYN is not input to the cycle flag generation circuit 2, so the counter 2b does not count. In addition, the weight (WAI
When the T) signal falls from "H" to "L", the input of the synchronous clock SYN is stopped. At this time, "11" is set in the flip-flop 2c, the counter 2b is reset, and the cycle ends. Furthermore, for a certain period,
For example, when the WAIT signal and the synchronizing signal SYN do not change for 80 cycles or more, the output from the 80 pulse counter is sent to the flip-flop 2c and the flag bits F2 and F3 generate the signal "11". In addition, 2
Since the flip-flops 2c of the stages are reset at the rising edge of the unit pulse PU, at other times, it is assumed that the data is being transferred, and the flag bits F2 and F3 generate the vector data signals of "00", respectively. It is sent to the circuit 6. As a result, as shown in FIG. 3B, each flag bit is sent to the vector data generation circuit 6 in response to the data transfer.

The start condition detection circuit 3 comprises a D flip-flop 3a and a 2-input AND gate 3b, and the power supply voltage detection circuit 4 supplies a power-on detection signal PWO.
When N is input to the AND gate 3b and becomes "H", the gate is opened as a signal that the power of the card is turned on. The flip-flop 3a receives a "REG" signal that selects the attribute space on the bus 11, latches the falling edge of the signal, and sends the output to the gate 3b. As a result, the AND gate 3b outputs the output signal G
TON is generated, and this is input to the synchronous clock generation circuit 3c and the vector data generation circuit 6. As a result, "RE
Data can be sampled in response to the G "signal. The application program installed in the host computer 20 starts operating in response to the fall of the" REG "signal. Is
Upon receiving the system clock CLK, the synchronous clock SYN is sent to the vector data generation circuit 6 and the like in response to the output signal GTON of the AND gate 3b.

The power supply voltage detection circuit 4 includes a comparator (C
OM), which receives an input signal from a line connected to the pin of the operating power supply signal Vcc on the bus 11 and compares it with a predetermined reference voltage VREF to detect the power ON signal PWON.
Occurs. This detection signal is sent to the start condition detection circuit 3, the end detection circuit 5, and the vector data generation circuit 6.
The end detection circuit 5 is composed of a NAND circuit and includes a bus 11
In response to the AND signal and the previous detection signal PWON, the end signal CEND is sent to the vector data generation circuit 6 under these AND conditions. The vector data generation circuit 6 receives 68-bit data from the bus 11 and outputs the preceding 4-bit flag data F0 to F3 from the 69th bit to the 72nd bit.
In addition to the bit-th bit, a total of 72-bit bit data is generated and output to the selected memory of the memories 8a and 8b according to the address indicated by the address generation circuit 7.

The generation of data by the vector data generating circuit 6 is performed by the synchronous clock generating circuit 3c from the synchronous clock SYN.
Receiving output signal GTON and detection signals PWON and CEN
The gate circuit 6c generates a signal which is an AND condition with the inverted signal of D as an enable signal to start the operation. The 72-bit counters 6a, 6a, ..., Which are arranged in parallel, receive the input 72-bit signals in bit parallel. The output of the counter 6a is set in bit parallel to each digit position of the 72-digit register 6b. Each digit from 1 digit to 68 digits of this register 6b corresponds to data from each line of 68 bits from the bus 11,
Each digit from the 69th digit to the 72nd digit of the register 6b corresponds to the flag bit of the 69th bit to the 72nd bit. The output of each digit of the register 6b is sent to the memories 8a and 8b in bit parallel according to the timing of the unit pulse PU. When each 7-bit counter is triggered by the synchronous clock SYN and receives a signal of 7 bits or more for each input signal, it outputs 1-bit data to the corresponding digit position of the register 6b, and the cycle flag It is reset according to the unit pulse PU from the generation circuit 2. Thus, when a signal of 7 bits or more arrives, 1-bit data is detected, and even if there is a loss of up to 3 bits, 1-bit detection is performed and the bit is saved.

The address generation circuit 7 is internally provided with a program counter 7a, and the synchronous clock generation circuit 3 is provided.
c to synchronous clock SYN and cycle flag generation circuit 2
In response to the unit pulse PU from the memory 8a, the selection signal of the memory 8a and the write control signal CNT are first generated in synchronization with the synchronization clock SYN, and the program counter 7a is incremented according to the unit pulse PU to increase the address ADD To access the memory 8a. When data is written up to the final address of the memory 8a, a selection signal for selecting the memory 8b and a write control signal C
Generate NT and store the value of the program counter in the memory 8b.
Return to the start address of. Then, in the same manner as described above, data is written up to the final address of the memory 8b, and again,
Selection signal for selecting the memory 8a and write control signal CNT
Is generated and the value of the program counter is returned to the start address of the memory 8a. In this way, the memory 8 is alternately
72-bit combined test basic data is stored in a and 8b.

The data thus stored is stored in the memory 8a by the controller 9 which receives the PWON signal, the selection signal and the write control signal CNT from the power supply voltage detection circuit 4.
Data is read from the memory side not written in 8b, and the data is sequentially transferred to and stored in the external storage device 13. The test basic data collected as described above is read under the control of the controller 9 by mounting the external storage device 13 on the host computer 20 or the like and reading the data, or by turning on a predetermined switch. Through the bus 11, the data read from the external storage device 13 is sent to the data processing device such as the host computer 20 to which it is attached.

As shown in FIG. 4, the 72-bit test basic data stored in the external storage device 13 consists of 68-bit actual data and 4-bit flag data. The data processing device or the host computer 20 receiving this test basic data, as shown in FIG.
At 0, the flag data F0 and F1 are discriminated. When the flag data is in the write state, the flag data is "01". At this time, in step 101, control data for driving the driver to be transmitted as test data is generated. And then step 1
In 02, the flag bits F2 and F3 are discriminated.
If it is 01 ", write control data is generated in step 103, and this is arranged in the test program as test data.

In step 104, the flag data of the next 72-bit basic data is referred to and its flag bit F2,
Whether F3 is "01" or not is determined, and if the condition is NO, in step 105 68 bits of the 72 bits are placed as output data in the test program. Then, the process returns to step 104. As a result, the flag data F0 and F1 are "01" and the flag bits F2 and F3 are
When is "00", test data of 68-bit data is subsequently arranged as output data. This is continued until the flag bits F2 and F3 become "10". If it is determined in step 104 whether F2 and F3 are "10", Y
When the ES condition is satisfied, the process returns to step 100. Further, the flag bits F2 and F3 are set to "1" in the judgment of step 102.
When it is 0 ", the process returns to step 100. Step 10
When 0 and the NO condition other than the above occur at step 102, the process proceeds to step 112.

In step 100, the next test basic data is referred to, and the flag data F0 and F1 are discriminated. When the flag data is in the read state, the flag data is "10". At this time, the read control signal is sent in step 106. Generate test data to generate and use as test program data. Then, in step 107, the data to be put in the waiting state for the received data from the PC card 12 is arranged next as test data. Next, in step 108, the flag bit F
2, F3 is discriminated, and when it is "01", in step 109, 68 bits of the next test basic data is used as expected value data and further compared with the received data from the PC card, and the result is stored in a predetermined storage position. Control data to be added and arranged as test data, and in step 110, it is determined whether or not the flag bits F2 and F3 are "11" by referring to the flag data of the next 72-bit basic data. Sometimes, in step 111, a data bit as an expected value out of the 72 bits, for example, do
The 16-bit basic data of .about.d15 is used as expected value data and further compared with the received data from the PC card, and the control data for storing the result in a predetermined storage position is similarly used as the test data. Then, the process returns to step 110.

As a result, the flag data F0 and F1 are "0".
1 "and flag bits F2 and F3 are" 00 ",
Then, similarly to the above, test data of 16-bit data is arranged as expected value data, and control data for comparing the received data with the received data and storing the result in a predetermined storage position is arranged. This is continued until the flag bits F2 and F3 become "10". F2 and F3 in step 110 are "0"
If YES in the determination as to whether or not the result is 1 ”, control is performed in step 113 in which test data of 16-bit data is arranged as expected value data, and the result is stored in a predetermined storage position in comparison with the received data. Data is placed.
Then, the process returns to step 100. Step 10
Even if the flag bits F2 and F3 are "10" in the judgment of 8, the process returns to step 100. If a NO condition other than the above occurs in step 108, the process proceeds to step 112. In step 100, the flag data F0 and F1 are discriminated. If the flag data F0 and F1 are not "01" or "10", in step 112 the test data is individually generated or other processing is performed.

In this way, test data is generated from actual data. In principle, the above processing is automatically converted by a program, but it may be generated manually. In the above case, the PC card 12 has already been checked as a correct program such as the program installed therein. It has also been checked that there is no error in the operation of each circuit of the PC card 12. Such a PC card 12 may be inspected in the same direction as the conventional one. You may use what tested each circuit individually. Further, each circuit may be tested by simulation. By using such a correct PC card, test data can be easily generated in a form close to actual data. Based on the correct PC card tested in this way, it is possible to easily generate more accurate test data for each application program, which is more accurate than the conventional simulation.

As described above, in the embodiment, the PC card may be loaded with an application program in addition to the basic program for testing. But,
The present invention may be a PC card in which a basic operation program or the like is simply installed, as long as the condition that the PC card operates is sufficient. Of course, an application program may be installed in this. Also,
The number of bits transferred by the PC card is determined according to the system and is not limited to 68-bit data.
Therefore, the number of bits of the test basic data is not limited to 72 bits. Although 4 bits are assigned to the flags generated by the directional flag and cycle flag generation circuits, more flags may be assigned as spares. In particular, when the number of transfer bits is small, the number of bits assigned to this can be increased. Further, the generation circuit of the directional flag and the cycle flag can be configured by various logic circuits, and 10 bits of 10 cycles can be directly transmitted to the vector data generation circuit without being transmitted to the vector data generation circuit.
1-bit flag data may be generated for each cycle and sent to the vector data generating circuit.

[0025]

According to the present invention, in order to use the data actually exchanged with the PC card as the basic data for the test, the PC card is actually operated and a predetermined application program is started to process the data. Since a device is provided that operates the device, transmits / receives data to / from the device, generates directional data indicating the transfer direction of the data from the data, and synthesizes the directional data with the actual data. By simply starting up, various transmission data regarding the operation of the application and response data thereto can be collected together with the directional data. As a result, the test basic data collected in the memory is referred to as the directional data, and the data sent from the data processing device to the PC card is the test data, and the response data from the PC card is the expected data. By using the actual transmission / reception data by using the value data, more reliable test data can be efficiently created. Therefore, it is not necessary to form a simulation circuit model.

[Brief description of drawings]

FIG. 1 is a block diagram of a test basic data generating device of the present invention.

FIG. 2 is an explanatory diagram of directionality flag data in the test basic data generating device, and FIG. 2 (a) is an explanatory diagram showing a relationship between an input signal and an output signal thereof.
(b) It is explanatory drawing of the function of the flag bit.

FIG. 3 is an explanatory diagram of cycle flag data in the test basic data generation device, (a) is
It is explanatory drawing of the function of the flag bit, and (b) is explanatory drawing of the relationship with the data transfer.

FIG. 4 is an explanatory diagram of a generation method when generating test data from the test basic data.

FIG. 5 is a flowchart of the test data generation process.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Directional flag generation circuit, 2 ... Cycle flag generation circuit, 3 ... Start condition detection circuit, 4 ... Power supply voltage detection circuit, 5
... End detection circuit, 6 ... Vector data generation circuit, 7 ... Address generation circuit, 8a, 8b ... Memory, 9 ... Controller, 10 ... Test basic data generation device, 11a, 11b
... connector, 12 ... PC card, 13 ... external storage device,
20 ... Host computer.

Claims (3)

[Claims] 1. A signal which is connected to a data transfer bus between a PC card and a data processing device, and which indicates a transfer direction of the data according to a signal corresponding to control data among data transfer signals on the bus. Alternatively, a directional signal generating circuit that generates data indicating a transfer direction, and an output of the directional signal generating circuit and the data transfer signal are added, and the directional data is added to the transfer data from these signals or these signals and data. A data generating circuit for generating the test basic data as the test basic data and a memory for storing the test basic data, and the data processing device operates the PC card to transfer data between them. A test basic data generator for storing test basic data. 2. A signal for starting and ending an operation cycle for write data or read data for the PC card or a start and end for an operation cycle for write data or read data for the PC card in accordance with a signal corresponding to control data among data transfer signals on the bus. Start cycle to generate data about
An end signal generation circuit is provided, and the data generation circuit receives the output of the directional signal generation circuit, the output of the cycle start / end signal generation circuit, and the data transfer signal, and transfers these signals or these signals and data. 2. The test basic data generating device according to claim 1, wherein the test basic data generating device generates data obtained by adding direction data and data indicating the start or end of a write or read operation cycle to the data as the test basic data. 3. A signal which is connected to a data transfer bus between a PC card and a data processing device and which indicates a transfer direction of the data according to a signal corresponding to control data among data transfer signals on the bus. Alternatively, a directional signal generating circuit that generates data indicating a transfer direction, and an output of the directional signal generating circuit and the data transfer signal are added, and the directional data is added to the transfer data from these signals or these signals and data. A data generating circuit for generating the test basic data as the test basic data and a memory for storing the test basic data, and the data processing device operates the PC card to transfer data between them. The test basic data is stored, and the data processing device refers to the directional data of the test basic data in the memory to output the P Sending data to the card and transmitted data in the test data, the method for generating test data for generating test data to the expected value data in the test data response data from the PC card to the data processing device.