JPH08160452A - Active matrix substrate - Google Patents

Abstract

PURPOSE: To provide an active matrix substrate having a high opening rate without increasing the occupying area of additive capacitor electrode parts by making it possible to prevent interlayer shorting in these additive capacitor electrode parts. CONSTITUTION: This active matrix substrate 10 is formed by wiring scanning lines 12 and signal lines 13 on an insulatable substrate 11 and forming picture element electrodes 14 in regions enclosed by the scanning lines 12 and the signal lines 13. TFTs 15 electrically connected to the respective scanning lines 12, signal lines 13 and picture element electrodes 14 are formed. The scanning lines 12 adjacent to the scanning lines 12 connected to the TFTs 15 for driving the picture elements are superposed on the picture element electrodes 14 and the additive capacitor electrode parts 26 are formed in the superposed parts. Anodically oxidized films, gate insulating films and protective films are laminated on the edge parts of the scanning lines 12. The gate insulating films are removed by patterning and the anodically oxidized films and protective films are laminated in the parts exclusive of the edge parts.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix substrate, and more particularly to an active matrix substrate used for an active matrix driving type display device or the like.

[0002]

2. Description of the Related Art An additional capacitance is provided in order to prevent the potential of the pixel electrode from fluctuating and to obtain an active matrix substrate of excellent display quality. This causes the decrease in the non-defective rate. In order to prevent this interlayer short circuit, it has been conventionally proposed to employ a structure in which the insulating layers in the additional capacitance electrode portion are multilayered. For example, a gate insulating film is formed after forming an oxide film by anodic oxidation on the scanning line and the additional capacitance line forming the additional capacitance electrode portion, thereby forming a two-layer structure.

As a known document describing a conventional active matrix substrate, for example, JP-A-4-265 is known.
There is a 945 publication. In this publication, two layers of insulating films are formed between the picture element electrode forming the additional capacitance and the additional capacitance electrode portion so that a short circuit is unlikely to occur. That is, a structure has been proposed in which the additional capacitance electrode portion is formed with the gate insulating film and the protective film sandwiched therebetween.

4 to 6 are configuration diagrams of a conventional active matrix substrate, FIG. 4 is a plan view of a main portion of a display portion, and FIG.
6 is a sectional view taken along the line CC 'in FIG. 4, and FIG. 6 is a sectional view taken along the line DD' in FIG. In the figure, 40 is an active matrix substrate, 41 is an insulating substrate, 42 is a scanning line, 43 is a signal line, 44 is a pixel electrode, and 45 is a TFT (Thin Film).
Transistor), 46 is a gate electrode, 47 is a cathode oxide film, 48 is a gate insulating film, 49 is a semiconductor layer, 50 is an etching stopper, 51 is a contact layer, 52 is a lease electrode, 53 is a drain electrode, and 54 is a contact. A hole, 55 is a protective film, and 56 is an additional capacitance electrode portion.

In the active matrix substrate 40,
Scanning lines 42 and signal lines 43 are arranged as electrode lines on the insulating substrate 41 made of a glass plate.
A pixel electrode 44 is formed in a region surrounded by the signal line 43. A TFT 45 as a switching element for driving each picture element electrode 44 is formed by being electrically connected to each of the scanning line 42, the signal line 43 and the picture element electrode 44.

The TFT 45 has a gate electrode 46 branched from the scanning line 42.
6. An anodic oxide film 47 is formed on the scanning line 42. Further, the gate insulating film 48 is formed so as to cover the entire surface of the substrate.
Is formed, and a semiconductor layer 49 serving as a channel portion of the TFT 45 is formed on the gate insulating film 48 so as to face the gate electrode 46. An etching stopper 50 is formed on the semiconductor layer 49, and a contact layer 51 that is electrically separated is formed on the etching stopper 50. A source electrode 52 branched from the signal line 43 toward the pixel electrode 44 and a drain electrode 53 branched from the pixel electrode 44 toward the source electrode 52 are provided on the contact layer 51. .

Further, a contact hole 54 is provided on the drain electrode 53 and a protective film 55 is formed. Further, a pixel electrode 44 made of an indium oxide-based material is formed on the protective film 55. The additional capacitance electrode portion 56 connected to the pixel electrode 44 is superimposed on the scanning line 42 to form an additional capacitance. In addition, as shown in FIG. 6, the gate insulating film 48 and the protective film 55 are laminated so that the number of laminated insulating films of the additional capacitance electrode portion 56 is uniform.

[0008]

As described above, in the conventional active matrix substrate, it is possible to prevent the occurrence of interlayer short circuit by forming the additional capacitance electrode portion with the insulating film having a multi-layer structure. Since the film thickness of the additional capacitance electrode portion increases, the capacitance per unit area decreases. Therefore, it is necessary to increase the area of the additional capacitance electrode portion in order to obtain a desired capacitance, which causes a reduction in the aperture ratio.

The present invention has been made in view of the above circumstances, and makes it possible to prevent an interlayer short circuit in the additional capacitance electrode portion, and further, without increasing the occupied area of the additional capacitance electrode portion, It is an object to provide an active matrix substrate having a high aperture ratio.

[0010]

According to the present invention, in order to solve the above-mentioned problems, (1) scanning lines or scanning lines and additional capacitance lines and signal lines are formed in a lattice pattern on an insulating substrate,
At each intersection of each line, through a thin film transistor whose switching is controlled by a signal of the scanning line,
In the active matrix substrate, in which each pixel electrode is connected to the signal line, and an additional capacitance electrode portion is formed with a plurality of insulating layers sandwiched between a part of the scanning line or the additional capacitance line, the additional capacitance electrode The number of laminated insulating layers forming the part is partially different, and (2) the pixel electrode is electrically connected to the drain electrode through a contact hole of a protective film on the thin film transistor, and With a structure in which an additional capacitance electrode portion connected to the pixel electrode is formed,
The gate insulating film and the protective film have a laminated structure in a part of the additional capacitance electrode part, and the part other than the laminated structure is composed of either the gate insulating film or the protective film. It is characterized by.

[0011]

[Action]

(1) Action corresponding to claim 1: Interlayer short circuit in the additional capacitance electrode portion is caused by cracks, pinholes, etc. due to poor coverage of the insulating film at the edges of the scanning lines and the additional capacitance wiring forming the additional capacitance electrode portion. There is a high probability that the defect is caused by. Therefore, in order to reduce the occurrence of interlayer short-circuit defects in the additional capacitance electrode part, the number of laminated insulating films may be increased only in the part where the defect occurrence rate is considered to be high, and in other parts, the insulating film may be formed. No need to increase.

(2) Action corresponding to claim 2: The number of laminated insulating films is increased only at the edge portions of the scanning lines and the additional capacitance wiring forming the additional capacitance, and insulation is performed except at the edge portions of the additional capacitance electrode portion. The number of laminated layers is reduced by one or more.
As a result, since the additional capacitance per unit area can be increased, the occupied area for obtaining the required additional capacitance can be reduced and a high aperture ratio can be obtained.

[0013]

Embodiments will be described below with reference to the drawings. 1 to 3 are configuration diagrams for explaining an embodiment of an active matrix substrate according to the present invention. FIG. 1 is a plan view of a main part of a display portion, and FIG. 2 is a sectional view taken along line AA 'in FIG. 3 and 4 are cross-sectional views taken along the line BB 'in FIG.
In the figure, 10 is an active matrix substrate, 11 is an insulating substrate, 12 is a scanning line, 13 is a signal line, 14 is a pixel electrode,
Reference numeral 15 is a TFT (Thin Film Transistor), 16 is a gate electrode, 17 is a cathode oxide film, 18
Is a gate insulating film, 19 is a semiconductor layer, 20 is an etching stopper, 21 is a contact layer, 22 is a source electrode, 2
3 is a drain electrode, 24 is a contact hole, 25 is a protective film, and 26 is an additional capacitance electrode portion.

This active matrix substrate 10 is provided on an insulating substrate 11 made of a glass plate or the like, a scanning line 12 as a first electrode wiring and a signal line 1 as a second electrode wiring.
3 is wired, and a pixel electrode 14 is formed in a region surrounded by the scanning line 12 and the signal line 13. Then, the TFT 1 is electrically connected to each of the scanning line 12, the signal line 13 and the pixel electrode 14 to serve as a switching element.
5 is formed.

The TFT 15 has a gate electrode 16 branched from the scanning line 12. An anodic oxide film 17 is formed on the gate electrode 16, and a gate insulating film 18 is formed so as to cover the entire surface of the substrate. A semiconductor layer 19 serving as a channel portion is formed on the gate insulating film 18 so as to face the gate electrode 16. In this embodiment,
It was formed using amorphous silicon. Further, an etching stopper 20 is formed on the semiconductor layer 19,
A contact layer 21 that is electrically isolated is formed on the etching stopper 20. The contact layer 2
A source electrode 22 that is branched from the signal line 13 toward the pixel electrode 14 and a drain electrode 23 that is branched from the pixel electrode 14 toward the source electrode 22 are provided on each of 1. . A protective film 25 is formed on the drain electrode 23.
However, the contact hole 24 is formed in the drain electrode 23. Further, the indium oxide based pixel electrode 14 is connected to the drain electrode 23 via the contact hole 24 on the protective film 25.

The pixel electrode 14 has a TFT for driving the pixel.
Scan line 12 adjacent to scan line 12 connected to 15
Are overlapped with each other, and the additional capacitance electrode portion 26 is formed in the overlapped portion. At the edge of the scanning line 12, the anodic oxide film 1
7, the gate insulating film 18 and the protective film 25 are laminated. The gate insulating film 18 is removed by patterning except the edge portion, and the anodic oxide film 17 and the protective film 25 are laminated.

Next, the manufacturing process of the active matrix substrate will be described with reference to FIGS. First, 30 tantalum is sputtered on the glass substrate 11.
Laminate to a thickness of 0 nm. The stack is patterned by photolithography to form scan lines 12. At this time, the gate electrode 16 is simultaneously formed. Next, the scanning line 12 and the gate electrode 16 are oxidized by an anodic oxidation method to form an anodic oxide film 17 with a thickness of 300 nm.

Subsequently, plasma CVD (Chemical Vapor)
Deposition: chemical vapor deposition method is used to form a gate insulating film 18 made of silicon nitride to a thickness of 300 nm in the semiconductor layer 1
As No. 9, amorphous silicon is laminated to a thickness of 30 nm, and silicon nitride is laminated to a thickness of 200 nm. Then, the upper layer of silicon nitride is patterned by photolithography to form the etching stopper 20.
Then, by plasma CVD, n + with phosphorus added
An amorphous silicon layer is laminated with a thickness of 50 nm.
Then, the contact layer 21 is formed by photolithography.
And the semiconductor layer 19 is patterned at the same time.

Next, as shown in FIG. 3, the gate insulating film 18 is patterned and removed except the edge portion on the scanning line 12. After that, Mo is used as a signal wiring material.
The metal films are laminated by a sputtering method and patterned by photolithography to form the signal line 13, the source electrode 22 and the drain electrode 23. next,
A silicon nitride film having a thickness of 300 nm is stacked on the protective film 25 by a plasma CVD method. Then, the contact hole 24 and the patterning are removed by photolithography.

Next, a transparent conductive film containing indium oxide as the pixel electrode 14 as a main component is formed by sputtering.
The active matrix substrate 10 is completed by stacking to a thickness of 0 nm and forming the pixel electrodes 14 and the additional capacitance electrode portions 26 by photolithography. Further, an alignment film (not shown) is formed on the active matrix substrate 10, and the alignment film is rubbed. Then, it is bonded to a substrate (not shown) provided with a counter electrode, and a liquid crystal (not shown) is injected between both substrates to obtain a liquid crystal panel. As described above, the active matrix substrate of the present invention can achieve the above object by making the insulating layers forming the additional capacitance multi-layered and further reducing the number of laminated insulating films in a part thereof.

[0021]

As is apparent from the above description, the present invention has the following effects. (1) Effect corresponding to claim 1: The number of laminated insulating films in the additional capacitance electrode portion is changed in any portion, and the insulating films are laminated only in a portion having a high occurrence rate of interlayer short-circuit defects. It is possible to prevent defects due to interlayer short circuits. (2) Effect corresponding to claim 2: The number of laminated insulating films is increased only in the edge portions of the scanning lines and the additional capacitance wiring forming the additional capacitance, and the insulating layers are laminated except in the edge portions of the additional capacitance electrode portion. Since the number of layers is further reduced or reduced, the additional capacitance of the insulating film does not decrease and it is not necessary to increase the area of the additional capacitance electrode portion. Therefore, the active matrix substrate of the present invention improves the aperture ratio of the liquid crystal panel. Let
A liquid crystal display device with low power consumption can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram for explaining an embodiment of an active matrix substrate according to the present invention.

FIG. 2 is a sectional view taken along the line AA ′ in FIG.

FIG. 3 is a sectional view taken along line BB ′ in FIG.

FIG. 4 is a main part plan view showing a display unit of a conventional active matrix substrate.

5 is a sectional view taken along line CC ′ in FIG.

6 is a cross-sectional view taken along the line DD ′ in FIG.

[Explanation of symbols]

10 ... Active matrix substrate, 11 ... Insulating substrate,
12 ... Scan line, 13 ... Signal line, 14 ... Picture element electrode, 15 ...
TFT (Thin Film Transistor), 16 ... Gate electrode, 17 ... Cathode oxide film, 18 ... Gate insulating film, 19 ... Semiconductor layer, 20 ... Etching stopper, 21 ... Contact layer, 22 ... Source electrode, 23 ...
Drain electrode, 24 ... Contact hole, 25 ... Protective film, 26 ... Additional capacitance electrode section.

Claims (2)

[Claims] 1. A thin film transistor in which scanning lines or scanning lines and additional capacitance lines and signal lines are formed in a grid pattern on an insulating substrate, and switching is controlled by signals of the scanning lines at respective intersections of the respective lines. In the active matrix substrate, each pixel electrode is connected to the signal line via, and an additional capacitance electrode portion is formed with a plurality of insulating layers sandwiched between a part of the scanning line or the additional capacitance line, An active matrix substrate, wherein the number of laminated insulating layers forming the additional capacitance electrode portion is partially different. 2. A structure in which the pixel electrode is electrically connected to a drain electrode through a contact hole of a protective film on the thin film transistor, and an additional capacitance electrode portion connected to the pixel electrode is formed. The gate insulating film and the protective film have a laminated structure in a part of the additional capacitance electrode part, and the part other than the laminated structure is composed of either the gate insulating film or the protective film. The active matrix substrate according to claim 1, wherein: