JPH07325314A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To prevent the reduction of resistance between a source and a drain due to the remaining etching of an a-Si along the level difference of a gate insulating film by an auxiliary capacitance electrode and to prevent the reduction of a voltage holding rate of a pixel capacitance and the short circuit between the source and the drain, as to an active matrix type liquid crystal display device using a TFT. CONSTITUTION:The device has such a structure that the auxiliary capacitance electrode 11S projects out of a display electrode 16 on the same plane. Thus, even in the case an a-Si13T due to defective etching remains in an area defined by the L-shaped level difference of the gate insulating film generated along the edge between the auxiliary capacitance electrode 11S and an auxiliary capacitance line 11SL, the a-Si13T does not reach the display electrode 16, and it is insulated from a drain line 17DL. Thus, the reduction of the resistance between the source and the drain is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device having an improved yield.

[0002]

2. Description of the Related Art Liquid crystal display devices have advantages such as small size, thin shape, and low power consumption, and are being put to practical use in fields such as OA equipment and AV equipment. In particular, the active matrix type using a thin film transistor (hereinafter abbreviated as TFT) as a switching element can perform static driving with a duty ratio of 100% in a multiplexed manner in principle, and has a large screen and a high-definition moving image display. Is used for.

The active matrix type liquid crystal display device is
A substrate in which TFTs are connected to display electrodes arranged in a matrix (TFT substrate) and a substrate having a common electrode (counter substrate) are bonded together, and liquid crystal is sealed in a gap. The TFT is a switching element that selects a data signal input to the display electrode, and includes a gate electrode, a drain electrode, a source electrode, and a non-single-crystal semiconductor layer. Each electrode is connected to a gate line, a drain line and a display electrode, and the non-single crystal semiconductor layer is amorphous silicon (a-Si) or polysilicon (p-S).
i), which functions as a channel layer. The gate line group is line-sequentially scan-selected and all TFs on one scan line are selected.
When T is turned on, a data signal synchronized with this is input to each display electrode via each drain line. The voltage of the common electrode is set in synchronization with the scanning signal, the liquid crystal in the gap is driven by the voltage between the display electrodes facing each other, and the light transmittance is adjusted for each display pixel. The composite of the key display is visually recognized as a display image. Also, OFF
The driving state of the liquid crystal during the period is continued by the applied voltage of the pixel capacitance formed between both electrodes being held for one field period by the OFF resistance of the TFT, but by adding the auxiliary capacitance in parallel with this. The retention characteristics can be improved. The auxiliary capacitance also has a function of suppressing the shift of the source voltage due to the parasitic capacitance generated in the overlapping portion between the source and the gate, which is unavoidable due to the limitation of the manufacturing process. That is,
By increasing the capacitance value by the parallel combined capacitance with the pixel capacitance, the influence of the DC component of the parasitic capacitance is reduced.

FIG. 3 is a plan view of a conventional liquid crystal display device. Gate line (11GL) and drain line (17
DL) are arranged to intersect each other, and both lines (11G
A display electrode (16) is arranged in a region surrounded by L, 17DL). At the intersection of both lines (11GL, 17DL), the gate electrode (11G), the gate insulating film, aS
i (13), passivation (14) and source / drain electrodes (17S, 17D) are sequentially stacked to form a TFT
And the source electrode (17S) is the display electrode (16).
Connected to. Further, the auxiliary capacitance electrode (11S) is arranged in an insulating manner so as to overlap with the display electrode (16), and is connected to the adjacent pixel by the auxiliary capacitance line (11SL). Gate line (11GL) and drain line (17DL),
In addition, in order to improve the insulation property at the intersection of the auxiliary capacitance line (11SL) and the drain line (17DL), in addition to the gate insulating film, a-Si (13G, 13G) is formed.
S), N ⁺ type a-Si (15G, 15S) and passivation (14G, 14S).

FIG. 4 is a sectional view taken along line AA of FIG.
FIG. 5 is a cross-sectional view taken along the line CC of FIG. A gate line (11GL) and a gate electrode (11) are formed on the glass substrate (10) by, for example, Cr sputtering and photoetching.
G), the auxiliary capacitance electrode (11S) and the auxiliary capacitance line (1
1SL) is formed. Cover these all over,
SiN _x to be the gate insulating film (12), a-Si to be the channel layer of the TFT, and SiN _x to be the passivation of the TFT are continuously formed by CVD, and the upper SiN _x is photo-etched to the TFT portion. And patterned on the passivation (14, 14G, 14S) at the wiring intersection. Furthermore, a-Si (hereinafter referred to as N ⁺ a-Si) that is heavily doped with impurities such as phosphorus to obtain ohmic contact of the TFT is formed by CVD.
After the film formation, the N ⁺ a-Si and a-Si are formed in an island shape on the TFT portion and the wiring intersection by etching using the same mask as a-Si (13, 13G, 13S).
Layer and N ⁺ a-Si (15, 15G, 15S) layer. On the other hand, the display electrode (16) is formed by sputtering of ITO and photoetching, and is superimposed on the auxiliary capacitance electrode (11S) via the gate insulating film (12). In the uppermost layer, for example, 2 made of Al / Mo
The drain line (17DL), the drain electrode (17D), and the source electrode (17S) are formed by sputtering and photoetching the layer film. N ⁺ a-Si (1
5) is the source and drain electrodes (17S, 17S)
The source part and the drain part are separated by etching using D) as a mask.

[0006]

SUMMARY OF THE INVENTION a-Si (13,13
G, 13S) and N ⁺ a-Si (15, 15G, 15
Although the etching of S) is performed by a dry process, when etching residue occurs due to etching failure,
As shown in FIGS. 3 and 5, the a-Si (13T) is used as the auxiliary capacitance electrode (11S) and the auxiliary capacitance line (11SL).
-Shaped gate insulating film along the edges of the gate (12)
Is likely to remain in the area defined by the step. For this reason,
When the L-shaped step is in the region of the display electrode (16), the display electrode (16) and the drain line (17DL) are connected by the unetched a-Si (13T). The resistance value between the source and the drain is decreased together with the connection by the high resistance a-Si, and the retention characteristic of the voltage applied to the pixel capacitance is deteriorated, and further, the source and the drain are short-circuited.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to solve this problem. First, a plurality of gate lines and auxiliary capacitance electrodes arranged on a substrate are provided with one auxiliary capacitance electrode. Auxiliary capacitance line connected to each other in the direction,
An insulating film covering the gate line and the auxiliary capacitance electrode, a drain line arranged so as to intersect the gate line and the auxiliary capacitance line with the insulating film interposed therebetween, and the auxiliary capacitance with the insulating film interposed therebetween. In a liquid crystal display device having a display electrode partially overlapped with an electrode and a thin film transistor formed at an intersection of the gate line and the drain line, an edge of the auxiliary capacitance electrode is
It is a configuration having no corner portion in the overlapping region with the display electrode.

Secondly, in the first structure, the auxiliary capacitance electrode is formed so as to be two-dimensionally protruded from the display electrode in the connection portion with the auxiliary capacitance line.
Thirdly, in the first configuration, the display electrode is notched in a concave shape at a connection portion between the auxiliary capacitance electrode and the auxiliary capacitance line.

[0009]

According to the first structure, the step along the step of the insulating film raised by the auxiliary capacitance electrode in the region of the display electrode does not have a corner, and an etching residue of the semiconductor layer of the thin film transistor occurs in this region. It gets harder. The second
With this configuration, it is possible to make the corners along the step of the insulating film generated along the edges of the auxiliary capacitance electrode and the auxiliary capacitance line outside the region of the display electrode. As a result, even if an etching residue of the semiconductor layer occurs in the region defined by the corners of the wayside, this region does not reach the display electrode, so the display electrode is insulated from the drain line connected to the semiconductor layer. Be done.

According to the third structure, by making the intersection with the drain line an auxiliary capacitance line having a line width narrower than that of the auxiliary capacitance electrode, interlayer short circuit is reduced.

[0011]

EXAMPLES Next, examples of the present invention will be described with reference to FIGS. 1 is a plan view of the pixel portion, and FIG. 2 is a cross-sectional view taken along the line BB of FIG. As the cross-sectional view taken along the line AA in FIG. 1, the same FIG. 4 as the conventional example is used. The same reference numerals are used for the same reference numerals as in the conventional example.

A gate line (11GL) having a gate electrode (11G) portion and an auxiliary capacitance electrode (11S) connected to an adjacent pixel by an auxiliary capacitance line (11SL) are formed on the glass substrate (10). The gate insulating film (12) is formed on the entire surface of these layers. On the gate insulating film (12), the drain electrode (1
A drain line (17DL) having a 7D portion is arranged to intersect the gate line (12GL), and a display electrode (16) is arranged in a region surrounded by the gate line (11GL) and the drain line (17DL). ing. Also,
The corresponding gate insulating film (1 G on the gate electrode (11 G)
2) on top of a-Si (14), passivation (1
5), N ⁺ a-Si (16), and source and drain electrodes (17S, 17D) are laminated to form a TFT.
In addition, the drain line (17DL) and the gate line (1
1GL) and at the intersection of the drain line (17DL) and the auxiliary capacitance line (11SL), a-Si made of the same material as the TFT together with the gate insulating film (12).
(13G, 13S), passivation (14G, 14
S) and N ⁺ a-Si (15G, 15S) are interposed to enhance insulation.

Although the auxiliary capacitance electrode (11S) is arranged under the display electrode (16) with the gate insulating film (12) interposed therebetween, as shown in FIG.
1S) is a connection portion with the auxiliary capacitance line (11SL), and is formed so as to protrude from the display electrode (12).
Therefore, at the intersection of the auxiliary capacitance line (11SL) and the drain line (17DL), the a-Si (13T) due to the etching residue remains in the auxiliary capacitance line (11SL).
Even if it exists in the region defined by the step of the gate insulating film (12) formed in an L shape along the edge of the auxiliary capacitance electrode (11S), as shown in FIG. Since the step portion of the mold is outside the area of the display electrode (16), the a-Si
(13T) is not connected to the display electrode (16)
The insulation between the drains is maintained.

Such a liquid crystal display device is manufactured, for example, as follows. First, Cr or the like is laminated on a glass substrate (10) by sputtering, and by etching this, a gate electrode (11G), a gate line (11GL), an auxiliary capacitance electrode (11S) and an auxiliary capacitance line (11SL). Is formed. The gate insulating film (12) is formed by coating this and laminating SiN _x or the like on the entire surface by plasma CVD. Then, a-Si and SiN _x are continuously laminated by plasma CVD, and the uppermost S
iN _x is formed in an island shape at the TFT portion and the wiring intersection portion by etching, and the passivation (14, 14G.1) is performed.
4S). Then, N by plasma CVD
⁺ a-Si is laminated, and the N ⁺ a-Si and the previously laminated a-Si are formed in an island shape at the TFT portion and the wiring intersection portion by etching using the same mask to form a-Si.
(13,13G, 13S) and N ⁺ a-Si (15,1)
5G, 15S).

At this time, the patterning of N ⁺ a-Si and a-Si is performed by dry etching. As shown in FIG. 2, the auxiliary capacitance electrode (11S) under the gate insulating film (12) is formed. With respect to the step formed at the edge of the auxiliary capacitance line (11SL), etching residue is likely to occur in the lowered region. Therefore, a-Si (13S)
The thin film of a-Si (13T) integrated with the structure extends to the step portion.

Next, ITO is laminated by sputtering, and this is etched to display electrodes (1
6) is formed. In the present invention, as shown in FIG. 1, the display electrode (16) does not reach the L-shaped step formed by the edges of the auxiliary capacitance electrode (11S) and the auxiliary capacitance line (11SL). Thus, the pattern of the display electrode (16) is formed in a shape that avoids the L-shaped step portion. Thereby, as shown in FIG. 2, the display electrode (16) is a
-Drain line (17D) without connecting to Si (13T)
Insulation from L) is maintained.

In the uppermost layer, for example, a laminated film of Al / Mo is formed by sputtering and is etched to form a drain line (17DL), a drain electrode (17D) and a source electrode (17S). Finally, the source and drain electrodes (17S, 17D) are used as a mask to etch N ⁺ a-Si (15) to separate the source and drain portions.

Particularly in this embodiment, the auxiliary capacitance electrode (11
S) is not extended and protruded from the display electrode (16), but the display electrode (16) is formed in a recessed pattern in the overlapping portion with the auxiliary capacitance electrode (11S). The storage capacitor electrode (11S) is connected to the display electrode (1
6) It is protruding from. As a result, the auxiliary capacitance electrode (11S) is formed so as to extend so as not to come too close to the drain line (17DL), and an interlayer short circuit is prevented.

[0019]

As is clear from the above description, at the intersection of the edge of the display electrode and the edge of the auxiliary capacitance electrode, the display electrode is formed on the semiconductor layer along the step of the gate insulating film raised by the auxiliary capacitance electrode. The semiconductor layer prevents the display electrode and the drain line from being connected to each other by forming the pattern so as to avoid the region where the etching residue is likely to occur, and the insulation between the source and the drain is maintained. As a result, the retention characteristic of the pixel capacitance due to the reduction of the resistance between the source and the drain and the short circuit between the source and the drain are prevented, so that the display quality is improved and the yield is increased.

[Brief description of drawings]

FIG. 1 is a plan view of a pixel portion of a liquid crystal display device according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line BB of FIG.

FIG. 3 is a plan view of a pixel portion of a conventional liquid crystal display device.

4 is a cross-sectional view taken along the line AA of FIG. 1 or FIG.

5 is a cross-sectional view taken along the line CC of FIG.

[Explanation of symbols]

10 glass substrate 11G gate electrode 11GL gate line 11S auxiliary capacitance electrode 11SL auxiliary capacitance line 12 gate insulating film 13 a-Si 14 passivation 15 N ⁺ a-Si 16 display electrode 17DL drain line 17D drain electrode 17S source electrode

Claims (3)

[Claims] 1. A plurality of gate lines and auxiliary capacitance electrodes arranged on a substrate, an auxiliary capacitance line connecting the auxiliary capacitance electrodes to each other in one direction, and the gate line and the auxiliary capacitance line with an insulating film interposed therebetween. In a liquid crystal display device having a drain line arranged to intersect, a display electrode partially overlapped with the auxiliary capacitance electrode, and a thin film transistor formed at the intersection of the gate line and the drain line, The liquid crystal display device is characterized in that an edge of the auxiliary capacitance electrode does not have a corner in a region where the auxiliary capacitance electrode overlaps with the display electrode. 2. The liquid crystal display device according to claim 1, wherein the auxiliary capacitance electrode is formed so as to be two-dimensionally protruded from the display electrode at a connection portion with the auxiliary capacitance line. 3. The liquid crystal display device according to claim 1, wherein the display electrode is notched in a concave shape at a connection portion between the auxiliary capacitance electrode and the auxiliary capacitance line.