JPH0787537B2 - Video signal DC stabilization circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a video signal DC stabilizing circuit for stabilizing a DC level of a video signal to a constant value in a video signal transmission device such as a television signal. Is.

[Conventional technology]

An example of a conventional video signal DC stabilizing circuit is shown in FIG. 5 and explained. This circuit has the configuration shown in FIG. In addition, feedback control is performed to fix the DC signal at a constant DC level (hereinafter referred to as a clamp level) that the video signal should have.

That is, first, the video signal applied to the input terminal 101 is supplied to the reproduction circuit 102, is DC-stabilized, and then is output from the output terminal 103.
Each is supplied to the A / D conversion circuit 105.

Then, in this sync separation circuit 104, the horizontal sync signal is separated from the video signal, and based on this horizontal sync signal,
A repetitive pulse (hereinafter, referred to as H pulse) that is phase-synchronized with the horizontal synchronization signal and is generated at a time interval (hereinafter, referred to as H interval) of the horizontal synchronization signal frequency is generated, and the H pulse is supplied to the comparison circuit 106. It In the A / D conversion circuit 105, the video signal is converted into digital data of 9 bits by analog / digital conversion using the sampling clock input from the clock terminal 108, and the comparison circuit 10
Supplied to 6. In this comparison circuit 106, 9-bit digital data (data value is A) is fixed reference data (data value is B) corresponding to the clamp level.
Compared to. This comparison data is A> B, A = B, A <B 3
By the H pulse supplied from the sync separation circuit 104, one sample at a time corresponding to the horizontal sync signal of the video signal is repeatedly sampled at H intervals and immediately before each H pulse. The sample value is held and supplied to the control signal generation circuit 107.

Next, in the control signal generation circuit 107, the comparison circuit 1
A control signal is generated based on the comparison data supplied from 06.

Then, when the comparison data is A> B, the horizontal sync signal level is higher than the clamp level, so the horizontal sync signal level is lowered, and when A = B,
Since the horizontal synchronizing signal level is equal to the clamp level, the horizontal synchronizing signal level is held, and when A <B, the horizontal synchronizing signal level is lower than the clamp level, so the horizontal synchronizing signal level is raised. A quantity control signal is generated at every H interval and without change during the H interval and is supplied to the reproduction circuit 102 to perform DC stabilization of the video signal.

[Problems to be Solved by the Invention] In the above-described conventional video signal DC stabilizing circuit, when comparing the horizontal synchronizing signal level of the video signal and the clamp level, three-valued comparison data (A> B, A) is used. = B, A <B) only. Therefore, since only three types of control signals (decrease the level, maintain the level, and increase the level) corresponding to the respective comparison data can be set, there is a problem that the control accuracy is rough and the image There was a problem that the controllability was poor with respect to sudden changes in the DC level of the signal.

Further, of the above comparison data, since only one sample of data is used, if noise or the like is superimposed on the video signal, noise may be superimposed on the comparison data and the value of the comparison data may be erroneous. However, there was a problem that the control became unstable. In addition, since the sound-in-sync system video signal that superimposes audio data on the horizontal sync signal of the video signal is controlled based on the comparison data of the horizontal sync signal level and the clamp level, the horizontal sync signal level is However, the direct current stabilization control was impossible because of the instability.

[Means for solving problems]

The video signal DC stabilizing circuit according to the present invention shifts the DC level of the arbitrary signal portion of the video signal to the DC level that the arbitrary signal portion should have based on the control signal and holds this DC level to maintain the DC level of the video signal. , A sync separation circuit that separates the composite sync signal and the horizontal sync signal from the video signal from this playback circuit, and the sampling clock to convert the video signal from the playback circuit to digital signal data The A / D conversion circuit that does this and the first pulse width that determines the start time can be set arbitrarily so that the start time and duration of the control pulse for specifying the position of the arbitrary signal portion can be set arbitrarily. Timing pulse,
A second timing pulse, which starts from a time point determined by this pulse width and whose duration is determined and whose pulse width can be arbitrarily set, is generated from the composite synchronization signal and the horizontal synchronization signal, and the second timing pulse and the sampling clock A control pulse generation circuit that generates a control pulse having a predetermined number of sampling clocks in the pulse by logical product and reference data that is a digital value of the DC level that the arbitrary signal portion should have are subtracted from the signal data to obtain a comparison error. The comparison circuit to be obtained, the comparison error is sampled by using a predetermined number of sampling clocks in the control pulse, the average of the predetermined number of comparison errors obtained is calculated, and the average comparison error output from the integration circuit is calculated. And a D / A conversion circuit for converting into a control signal and outputting to a reproduction circuit.

[Action]

In the present invention, the average comparison error, which is the level difference between the DC level of the arbitrary signal portion of the video signal and the DC level of the arbitrary signal portion that the DC-stabilized video signal should have, is calculated, and the average thereof is calculated. Feedback control is performed using a control signal having a control amount according to the comparison error value.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a video signal DC stabilizing circuit according to the present invention.

In the figure, 1 is an input terminal to which a video signal 21 is applied, 2
Is a reproducing circuit for DC-stabilizing the video signal 21 from the input terminal 1, and 3 is an analog output terminal for obtaining the DC-stabilized video signal 22 from the reproducing circuit 2.

4 is a sync separation circuit for separating the composite sync signal 23 and the horizontal sync signal from the video signal 22 from the reproduction circuit 2;
Convert the video signal 22 from 9 to 9 bit signal data 25
A / D conversion circuit, 6 is a setting circuit, 7 is a comparison circuit for comparing the 9-bit reference data 26 from the setting circuit 6 with 9-bit signal data 25 from the A / D conversion circuit 5, and 8 is this The comparison error 27 obtained by the comparison circuit 7 and the control pulse train 29 from the control pulse generation circuit 9 are input, and the average comparison error
An integrating circuit for obtaining 28, 10 receives the average comparison error 28 from the integrating circuit 8 and supplies a control signal 30 to the reproducing circuit 2 A /
It is a D conversion circuit.

Reference numeral 11 denotes a clock input terminal, and the sampling pulse 31 from the clock input terminal 11 is configured to be supplied to the D / A conversion circuit 5 and the control pulse generation circuit 9. 12
Is a digital output terminal from which the 9-bit signal data 25 from the A / D conversion circuit 5 can be obtained.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to FIGS. 2, 3, and 4.

2 to 4 are time charts showing the operation of the control pulse generating circuit 9 of FIG. 1, (a) of FIG. 2 showing a video signal (near the horizontal synchronizing signal), and (b) of FIG. ) Is an H pulse, (c) is a first timing pulse, (d) is a second timing pulse, (e) is a sampling clock,
(F) shows the respective control clocks. Further, FIG. 3A shows a video signal,
(B) shows a composite synchronizing signal, (c) shows an H pulse, (d) shows a control clock train, and (e) shows a control pulse train. In addition, in FIG. 3, (a) shows a vertical synchronizing signal section. Further, FIG. 4A shows an H pulse, FIG. 4B shows a control pulse train, FIG. 4C shows a horizontal synchronizing signal, FIG. 4D shows an equalizing pulse, and FIG. These are shown respectively. In addition, in FIG. 4, (b) and (c) indicate sample sections, respectively.

First, the video signal 21 is input from the input terminal 1 and supplied to the reproducing circuit 2. Then, one of the video signals 22 whose direct current is stabilized in the reproduction circuit 2 is output to the analog output terminal 3, and the other is output to the sync separation circuit 4 and the A / D conversion circuit 5.
Is supplied to.

Next, in the sync separation circuit 4, the composite sync signal 23 (horizontal sync signal,
The vertical synchronizing signal and the equalizing pulse) are separated from the horizontal synchronizing signal, and the horizontal synchronizing signal is phase-synchronized with the horizontal synchronizing signal and at a time interval of the horizontal synchronizing signal frequency (hereinafter referred to as H interval). A repetitive pulse 24 (hereinafter referred to as an H pulse) is generated, and the composite sync signal 23 is generated.
The repetitive pulse (H pulse) 24 is supplied to the control pulse generating circuit 9.

On the other hand, sampling clock 31 from clock input terminal 11
Is supplied to the A / D conversion circuit 5, and the other is supplied to the control pulse generation circuit 9.

Then, in the A / D conversion circuit 5, the video signal 22 supplied from the reproduction circuit 2 is converted into 9-bit signal data 25 by analog / digital conversion using the sampling clock 31 input from the clock input terminal 11. Converted,
One is a digital output terminal 12 as a digital video signal.
And the other is supplied to the comparison circuit 7.

On the other hand, in the setting circuit 6, a constant DC level (hereinafter, referred to as a clamp level) that the DC-stabilized video signal should have, actually, a DC level of an arbitrary signal portion of the DC-stabilized video signal. Is set to an arbitrary value and supplied to the comparison circuit 7 as 9-bit reference data 26.

In the comparison circuit 7, the value of the reference data 26 supplied from the setting circuit 6 is subtracted from the value of the 9-bit signal data 25 supplied from the A / D conversion circuit 5 to obtain the signal data 25 and the reference data 26. Is supplied to the integrating circuit 8 as a comparison error 27.

Next, in the control pulse generation circuit 9, the composite sync signal 23 and the H pulse 24 supplied from the sync separation circuit 4,
Based on the sampling clock 31 supplied from the clock input terminal 11, as shown in FIG.
First timing pulse (FIG. 2 (c)) whose rising pulse width can be arbitrarily set in synchronization with the rising of the H pulse (FIG. 2 (b)) generated based on the horizontal sync signal separated from FIG. Is generated in synchronization with the falling edge of the first timing pulse, a second timing pulse (FIG. 2 (d)) whose pulse width can be arbitrarily set is generated, and the second timing pulse and the sampling clock ( Figure 2
(E)) A control clock train (Fig. 2)
(F)) is generated. Further, as shown in FIG. 3, the control clock based on the composite sync signal (FIG. 3 (b)) separated from the video signal (FIG. 3 (a)) and the H pulse (FIG. 3 (c)). A control pulse train (FIG. 3 (e)) 29 is generated by the logical product with the train (FIG. 3 (d)). Each pulse of the control pulse train 29 has a pulse starting point according to the pulse width of the first timing pulse shown in FIG. 2 (c), and a pulse width according to the pulse width of the second timing pulse shown in FIG. 2 (d). Can be set independently and arbitrarily.

Therefore, as shown in FIG. 2, as shown in FIG.
The pulse position is set in the back porch portion of (a)), and as shown in FIG. 3, the generation is prohibited within the vertical synchronizing signal period (a). Therefore, in the phase relationship shown in FIG. 4, it is possible to sample the signal portion of the video signal at the same level, and the pulse duration and sampling clock 31
It has a sample clock number based on and. And
The control pulse train 29 from the control pulse generating circuit 9 is supplied to the integrating circuit 8.

Next, in the integration circuit 8, the comparison error 27 supplied from the comparison circuit 7 is imaged by the control pulse train 29 supplied from the control pulse generation circuit 9 (the number of sample clocks in one pulse is a predetermined number N). N comparison errors corresponding to the back porch of the signal are sampled and summed,
N is calculated by multiplying the sum of N comparison errors by 1 / N.
The average comparison error 28 in which the individual comparison errors are averaged is calculated, and the above calculation is performed every time the control pulse is supplied,
Further, while the control pulse is supplied, the value is held and the average comparison error 28 is supplied to the D / A conversion circuit 10.

Next, in the D / A conversion circuit 10, the average comparison error 28 supplied from the integration circuit 8 is converted into an analog signal by digital / analog conversion, and the analog signal minimizes the average comparison error 28. That is, if the average comparison error 28 is a positive value, it means that the DC level of the video signal 22 is higher than the clamp level.
If the DC level of 22 decreases by an analog signal value corresponding to the average comparison error 28, and if the average comparison error 28 has a negative value, it indicates that the DC level of the video signal 22 is lower than the clamp level. Therefore, the DC level of the video signal 22 is converted into the control signal 30 so that the analog signal value corresponding to the average comparison error 28 rises, and is supplied to the reproducing circuit 2.

The above-described operation is performed in the vertical synchronization signal period (Fig. 3 (a)).
Except for the above), the DC level of the video signal 22 is stabilized at every H interval.

〔The invention's effect〕

As described above, according to the present invention, the average which is the level difference between the DC level of the arbitrary signal portion of the video signal and the DC level of the arbitrary signal portion which the DC-stabilized video signal should have. Since the comparison error is calculated and the feedback control is performed by using the control signal of the control amount according to the average comparison error value, the control accuracy and the control followability and responsiveness are the same as those of the conventional type. Improved compared to the circuit of
Since the control is performed by averaging a large number of comparison errors, the influence due to the superposition of noise and the like is reduced, and the stability of the control can be improved, so that the practical effect is extremely large.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a video signal DC stabilizing circuit according to the present invention, and FIGS. 2, 3 and 4 are time charts for explaining the operation of the control pulse generating circuit in FIG. FIG. 5 is a block diagram showing an example of a conventional video signal DC stabilizing circuit. 2 ... Reproduction circuit, 4 ... Sync separation circuit, 5 ... A / D conversion circuit, 6 ... Setting circuit, 7 ... Comparison circuit, 8 ... Integration circuit, 9 ... Control pulse generation circuit, 10 ... … D / A conversion circuit.

Claims (1)

[Claims] 1. A video signal direct current stabilization circuit for stabilizing a direct current level of a video signal to a constant value, which is used in a video signal transmission device such as a television signal, and an arbitrary signal of the video signal based on a control signal. A reproducing circuit for changing the direct current level of the portion to the direct current level that the arbitrary signal portion should have and stabilizing the direct current level of the video signal by holding this direct current level, and a composite synchronizing signal from the video signal from the reproducing circuit. And a sync separation circuit for separating the horizontal sync signal, an A / D conversion circuit for converting the video signal from the reproduction circuit into digital signal data by using a sampling clock, and a position for specifying the position of the arbitrary signal The first timing pulse whose pulse width that determines the start time can be set arbitrarily so that the start time and duration of the control pulse can be set arbitrarily. And a second timing pulse whose pulse width that determines the duration starts from a time point determined by this pulse width and which can be arbitrarily set, is generated from the composite synchronization signal and the horizontal synchronization signal. And a control clock generating circuit for generating the control pulse having a predetermined number of sampling clocks in the pulse by a logical product of the sampling clock, and the reference data which is a digital value of a direct current level that the arbitrary signal portion should have. A comparison circuit that subtracts from the data to obtain a comparison error, an integration circuit that samples the comparison error using a predetermined number of sampling clocks in the control pulse, and averages the obtained predetermined number of comparison errors, and an integration circuit A D / A conversion circuit for converting the average comparison error output from the circuit into a control signal and outputting the control signal to the reproduction circuit. Video signal DC stabilization circuit to symptoms.