JPH0141063B2 - - Google Patents

Description

[Detailed Description of the Invention] A TBC is used to remove jitter (time axis fluctuation) from a color video signal reproduced by a VTR, and this TBC is basically configured as shown in Fig. 1, for example. has been done.

That is, in FIG. 1, a color video signal Sc from a VTR is supplied to an A-D converter 3 through an input terminal 1 and an input processor 2 to be converted into a digital signal Sd, and this signal Sd is written into a memory 4. Then, the signal Sd is read from the memory 4, and this read signal
Sd is supplied to the DA converter 5 and converted into an analog color video signal Sc, and this signal Sc is taken out to the output terminal 7 through the processor 6.

Also, the signal Sc from the input processor 2 is supplied to the burst gate circuit 11 to generate a burst signal.
Sd is taken out, and this burst signal Sb is output to PLL1.
2, synchronized with signal Sb, and signal Sb
A pulse Pw having a frequency N times (N is an integer greater than or equal to 2, for example, N=4) is formed. The pulse Pw formed in this manner is a constant period pulse signal in which only the initial phase matches the burst signal Sb. That is, the pulse Pw has the same amount of jitter as the jitter of the color video signal Sc only at the time of phase synchronization with the burst signal Sb for each horizontal period.

This pulse Pw is supplied as a clock pulse to the AD converter 3 through the sequence controller 13, and is also supplied to the memory 4 as a clock pulse during writing.

As a result, the jittery color video signal Sc input from terminal 1 has only a specific point in one horizontal period converted into a digital signal Sd from A to D by the pulse Pw that follows the jitter in the color video signal Sc. It is converted and written to memory 4.

On the other hand, a vertical synchronizing pulse Pv, a horizontal synchronizing pulse Ph, and a stable frequency and phase, which serve as a reference, are connected to terminal 15.
A color subcarrier Ss is supplied, and the signal Ss is supplied to the signal forming circuit 14 to form a pulse Pr with a frequency N times that of the signal Ss.This pulse Pr is supplied to the memory 4 through the controller 13 as a clock pulse at the time of reading. At the same time, it is supplied to the D-A converter 5 as a clock pulse.

Therefore, the color video signal Sc subjected to time axis correction is outputted to the terminal 7.

The above is the basic configuration and operation of TBC.

By the way, the ability of TBC to remove jitter is determined by how accurately the color video signal Sc having jitter is sampled to follow the jitter. This means that the pulse Pw is the color video signal Sc
This means that it must have a jitter equal to the jitter of .

However, in the TBC described above, the jitter of the color video signal Sc at terminal 1, for example,
Even though the pulse Pw changes continuously as shown by the solid line in Figure A, since the pulse Pw is formed from the burst signal Sb obtained in a horizontal period, the frequency or phase of the pulse Pw is shown by the broken line in Figure 2A. As shown, it changes only in steps, and therefore, the difference between the jitter of the signal Sc (solid line) and the frequency or phase of the pulse Pw (broken line) remains as a speed error in the color video signal Sc at terminal 7. I end up.

Therefore, in reality, the error voltage Ee corresponding to the speed error is extracted from the PLL 12 as shown in FIG. 2B, and the forming circuit is
4, the pulse Pr is phase-modulated to produce a pulse Pr with a frequency or phase as shown by the broken line in FIG. 2C.
Therefore, the color video signal Sc at terminal 7
This ensures that almost no jitters remain.

The TBC configured in this manner is described in detail in, for example, Japanese Patent Laid-Open No. 148317/1983 filed by the applicant of the present application. In other words, the bulletin states:
As a method of compensating for speed errors, a method of performing linear approximation of the speed error component to compensate and a method of determining the rate of change of the speed error component and then performing curve approximation to compensate are disclosed.

According to this disclosure, since the change in one horizontal period of the difference between the curve shown by the solid line and the straight line shown by the broken line in FIG. 2A of this specification corresponds to the actual speed error fluctuation component, this speed error fluctuation Figure B shows a linear approximation of the components.
By phase-modulating the pulse Pr using an error voltage Ee as shown in FIG. 1 and reading the stored contents of the main memory device using the phase-modulated pulse Pr, almost all speed errors can be eliminated. Furthermore, by determining the speed error fluctuation component by curve approximation instead of linear approximation, it is possible to obtain an improved TBC that further reduces the approximation error.

In this way, in the TBC shown in FIG. 1 and the TBC shown in the above-mentioned publication, the readout clock is phase-modulated by a speed error fluctuation component approximated by a straight line or a curve, and this phase-modulated readout clock is The speed error is removed on the read side of the memory 4 by reading out the digitized video signal from the memory and resampling the read signal using a DA converter.

However, in the speed error compensation method using the technique described above, the speed error is removed from the video signal converted into analog by the D-A converter 5, but the digital signal Sd written in the memory 4 is Speed error not removed. Therefore, the digital video signal read out from the memory 4
If Sd is directly combined with other digital signals that do not include speed error components for screen composition, etc., problems such as color unevenness will occur.

Therefore, when digital synthesis processing is performed using a conventional TBC that compensates for the speed error described above on the read side of the memory, an A-D converter that re-converts the output signal of the D-A converter 5 The disadvantage was that the configuration became even more complex.

This invention attempts to solve these problems.

Therefore, in the present invention, the writing clock is phase-modulated by a speed error fluctuation component approximated by a straight line or a curve as described above, and the reproduced video signal is converted from A to D by this phase-modulated writing clock. By converting and writing to memory 4, the signal written to memory 4
Configure Sd so that it does not have a speed error component.
That is, while the conventional TBC described above compensates for speed errors on the read side of the memory, the present invention is characterized in that speed errors are compensated on the write side of the memory.

That is, for example, as shown in FIG.
12 is a phase comparison circuit 31, a zero-order hold circuit 32 that holds this comparison output, and a VCO 3 whose oscillation frequency is controlled by this hold output.
3 and a frequency dividing circuit 34 that divides the oscillation output of the VCO 33 into a frequency of 1/N, and a color video signal Sc from the input processor 2.
is supplied to the AD converter 3 through the delay circuit 21 for one horizontal period.

According to such a configuration, the phase detection circuit 31
The burst signal Sb extracted from the color video signal Sc by the burst gate circuit 11 and the frequency-divided signal obtained by dividing the output of the VCO 33 to a frequency of 1/N by the frequency dividing circuit 34 are divided into one horizontal line. Compare the phase for each period. The result of this comparison is output as a phase error voltage, and is output to the zero-order hold circuit 3.
2, and this hold output is
It is supplied to VCO33 and controls the oscillation frequency.
Through a series of operations in this loop, the oscillation output Pw of the VCO 33 is controlled to a frequency N times that of the burst signal Sb, and is supplied as a clock pulse to the A-D converter 3 and memory 4 through the sequence controller 13.

Therefore, in the PLL 112, the pulse Pw formed by the above series of operations is assumed to have jitter that is a linear approximation of the jitter of the color video signal Sc from the VTR in order to compensate for speed errors. . This will be explained with reference to FIGS. 2, 3, and 4.

That is, since the PLL 112 includes the VCO 33 whose oscillation frequency is controlled by the phase error voltage, it can be considered that the PLL 112 forms an integral loop. Then, this integration loop is connected to the phase comparator circuit 3.
Since the phase error voltage between the burst signal Sb and the frequency-divided signal is output every horizontal period from 1 to 1, it can be considered that sampling of one horizontal period is equivalently included. Therefore, when the circuit of FIG. 3 is Laplace-transformed and illustrated, it can be expressed as shown in FIG. 4. However, φ _i : Phase of input burst signal Sb φ _p : Phase of frequency-divided signal T: Sampling period (one horizontal period) K: Gain in the loop.

Then, in Fig. 4, when φ _p (s) is calculated, φ _p (s) = (φ _i (s) − φ _p (s))K(1−e ^−TS )
/S ² ...(1) When this is Z-transformed, φ _p (z)=KT/Z-1+KTφ _i (z) ...(2).

Here, if the gain in the loop is determined so that KT = 1, φ _p (z) = 1/Zφ _i (z) ...(3), and if this is inversely converted into a function of time t, φ _p (t)=φ _i (t-T)...(4). This equation (4) means the following.

In other words, if the gain in the loop is set so that KT=1, the phase φ _p of the output of the VCO 33 is
It is equal to the phase φ _i of the burst signal Sb before T period.
In other words, in this PLL 112, assuming that the phase comparison between the burst signal Sb and the frequency-divided signal is performed at the present time, the phase φ _p of the frequency-divided signal after the period T is larger than the current phase φ _p (φ _i -φ _p ), the oscillation frequency of the VCO 33 is controlled by the phase error voltage.

Here, if the period of the divided signal of the newly set oscillation frequency is t _p and the period of the divided signal of the oscillation frequency set one horizontal period ago is t _-1 , then the phase φ _p in period T is The change is that every time the divided signal of the newly set oscillation frequency passes one cycle, the phase φ _p accumulates the phase difference of the period (t _p - _{t -1} ), and the sum of this accumulation becomes the value in the period T. (φ _i −φ _p ). This state is shown in FIG. 2 by a dashed line.
The change in the phase φ _p represented by the dashed line is a linear approximation of the phase φ _i of the burst signal Sb, that is, the jitter of the color video signal Sc represented by the solid line, delayed by one horizontal period.

In this way, the output pulse Pw of VCO33
is assumed to have jitter equivalent to that of the color video signal Sc.

Note that the gain K in the loop is determined by the phase comparator circuit 3.
1 or the output of the hold circuit 32. Furthermore, in reality, the sampling period T fluctuates due to jitter, but this fluctuation can be ignored in detecting speed errors.

By the way, in the A-D converter 3, the pulse
If the jitter in Pw does not accurately correspond to the color video signal Sc, the jitter in the signal Sc cannot be canceled out. Therefore, the color video signal Sc output from the input processor 2 is delayed by one horizontal period by the delay circuit 21 and then supplied to the AD converter 3.

As a result of the above, the color video signal with jitter
Sc is now analog-to-digital converted by the pulse Pw, which has the same phase and the same amount of jitter, and is written into the memory 4. Therefore, the digital signal Sd read out from the memory 4 by the clock pulse Pr of a constant period synchronized with the reference signal has jitter removed and does not include speed errors.

The color video signal Sc supplied to the A-D converter 3 is delayed by one horizontal period by the delay circuit 21, so when the digital signal Sd is written into the memory 3, the written digital signal Sd is Jitters have been removed.

Here, since the 0-hold circuit is a circuit that simply holds the speed error signal, the output signal form of the 0-order hold circuit 32 has a stepped waveform as shown by the dotted line in FIG. 2A. Although,
By inputting this signal to the VCO 33, the signal is outputted from the VCO 33 in an integrated form. This is because the VCO 33 itself is an integral system.

Therefore, the pulse Pw, which is the output signal of the VCO 33, is the free oscillation signal of the VCO 33 as shown in Fig. 2B.
The pulse signal is phase-modulated by a linearly approximated velocity error signal as shown in FIG.

If a first-order hold circuit is used instead of this zero-order hold circuit, the signal controlling the VCO33 will be
Since the signal is as shown in FIG. B, the output signal Pw of the VCO 33 becomes a pulse that is phase-modulated by the speed error signal approximated by the above-mentioned curve in combination with the integral effect of the VCO 33.

Therefore, it is clear that in this case, it is only necessary to use a delay circuit for two horizontal periods instead of the delay circuit 21 for one horizontal period. Similarly, when it is necessary to approximate a higher-order curve, for example, to approximate an n-order curve (n is an integer), the hold circuit 32 may be an n-1-order hold circuit, and the delay circuit 21 may be an n-horizontal period delay circuit.

Therefore, even if processing is performed with other digital signals Sd of the same clock system that do not include jitter for screen composition or the like, color unevenness will not occur.

Furthermore, processing such as extracting and storing the error voltage Ee and phase modulation using the error voltage Ee,
Since no D converter is required, the circuit can be greatly simplified.

FIG. 5 shows an example in which the present invention is provided with a circuit for eliminating errors in the amount of delay of the delay circuit 21 or fluctuations in the amount of delay due to temperature characteristics. That is,
In this example, the delay circuit 21 is a variable delay circuit, and its delayed output is supplied to the burst gate circuit 41 to extract the burst signal Sb, and the burst signal Sb and the frequency-divided signal from the frequency divider circuit 34 are is supplied to the phase comparator circuit 42,
The comparison output is supplied to the delay circuit 21 as a control signal.

Therefore, the color video signal Sc supplied to the A-D converter 3 is
Since APC is applied, even if there is a fluctuation in one horizontal period due to changes in the frequency of the input signal Sc, the signal
The phase of Sc becomes constant.

By using a variable delay line as the delay circuit 21 in this manner, it is possible to eliminate variations in the amount of delay due to variations in the amount of delay of the delay line, and there is no possibility of hue shift occurring.

In addition, in the above description, the delay circuit 21 is, for example,
Can be configured with CCD.

[Brief explanation of drawings]

FIG. 1, FIG. 2, and FIG. 4 are diagrams for explaining the present invention, and FIG. 3 and FIG. 5 are system diagrams of an example of the present invention. 21 is a delay circuit, 12 is a PLL, and 32 is a zero-order hold circuit.

Claims (1)

[Scope of Claims] 1. A write clock is formed in accordance with the time axis fluctuation included in the input video signal, and the write clock converts the input video signal into a digital video signal, and converts the input video signal into a digital video signal. A digital video signal is sequentially written into a memory means, and the stored contents are sequentially read out from the memory means using a readout clock generated based on a reference signal to obtain an output video signal from which time axis fluctuations have been removed. The signal time axis correction device includes a speed error detection circuit that compares the phases of the color burst signal obtained from the input video signal and the write clock to detect a speed error of the write clock; a delay circuit for delaying the input video signal so that the input video signal corresponds to the speed error, and a time axis correction of the video signal, wherein the phase of the write clock is controlled according to the speed error. Device.