JPH03106279A - Time base corrector - Google Patents

Abstract

PURPOSE:To highly and accurately correct jitter by constituting a video signal so as to be written in a memory through a delay circuit and setting up the delay time of the delay circuit to the time combining a normal one-horizontal period and a response delay time. CONSTITUTION:The delay circuit 10 for delaying a video signal only by the time combining the normal one-horizontal period and the response delay time required at the time of forming a write clock from a jitter detecting signal is provided in the prestage of the memory 5. Namely, the delay time of the delay circuit 10 is set up to the time combining the normal one-horizontal period and the response delay time required for forming the write clock from the jitter detecting signal. When the video signal passing the delay circuit 10 is written in the memory by the write clock, the jitter of the video signal coincides with that of the write clock, so that the jitter correction can be highly accurately executed.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention is designed to prevent jitter (time base) in which a reproduced video signal fluctuates in the time axis direction due to uneven rotation of the video head, uneven running of the tape, expansion/contraction, etc. in a video table recorder. This paper relates to a digital timebase corrector that corrects errors (errors) using memory. (Prior Art) In a conventional digital time base corrector, a video signal is detected by a clock synchronized with a jifter detection signal such as a horizontal synchronization signal separated from a video signal (luminance signal or chroma signal) reproduced by a video tape recorder. is written into the memory and read from the memory using a clock with a stable period.

FIG. 4 shows one of the digital time base collectors described above, which targets a luminance signal as a video signal and uses a horizontal synchronization signal separated from the luminance signal as a jitter detection signal.

The synchronization separation circuit 1 separates the horizontal synchronization signal HD from the reproduced luminance signal Y, and the separated horizontal synchronization signal HD is converted into PLL (Phase LockedLo
op) is led to circuit 2 as a comparison signal. The PLL circuit 2 compares the phases of the internally generated reference signal and the comparison signal derived from the synchronization separation circuit 1, and outputs the jitter-containing clock WCK of the comparison signal (horizontal synchronization signal HD) to the write address counter. The address that is updated every time the write cross WCK is input is transferred from the write address counter 3 to the memory 5.
It is designed to output to .

The A/D converter 4 digitizes the reproduced luminance signal Y and outputs it as luminance data Dv. The memory 5 stores the luminance data DY from the A/D converter 4,
Each time the write clock WCK is input, data is written to the address specified by the write address counter 3. The oscillation circuit 7 driven by the crystal oscillator 6 uses a read clock R with an extremely stable frequency.
CK is output to the read address counter 8, and the read address counter 8 provides the memory 5 with an address that is updated every time the read clock RCK is input. The memory 5 is arranged so that the written luminance data Dv is read out from the address specified by the read address counter 8 every time the read clock RCK is input.

The D/A converter 9 converts the luminance data D read out from the memory 5 into an analog luminance signal Yl. This luminance signal Y. Since the frequency of the read clock RCK is extremely stable, the jitter is corrected and the signal has a substantially constant period in any horizontal period.

(Problem to be Solved by the Invention) As described above, in the digital time base collector, the luminance signal Y, which has an error in one horizontal period due to the jitter, is processed through the A/D converter 4. When writing to the memory 5, the writing is performed by tying a write clock WCK generated by the synchronization separation circuit 1 and the PLL circuit 2 and containing jitter equivalent to the luminance signal Y. However, if we look closely at the operation in the PLL circuit 2, the write cross signal WCK generated by comparing the reference signal and the comparison signal (horizontal synchronization signal HD) is actually one horizontal synchronization signal HD and one horizontal synchronization signal HD. It has a period corresponding to the time interval with the horizontal synchronization signal HD before the period. This point will be explained using FIG. 5.

Horizontal synchronization signal HD of the n-th line. The horizontal period of the luminance signal detected by the PLL circuit 2 due to the input of is equal to the time interval tn between the horizontal synchronizing signal HD-+ of the (n-1)th line and the horizontal synchronizing signal HD of the n-th line. -t, which corresponds to the luminance signal Y7- of the (n-1)th line.

The PLL circuit 2 receives the luminance signal Y. ．． The horizontal period in-1 of WCK. -, is output.

However, this write clock W C K n- + with period i, l-17m is the luminance signal Y1 of the n-th line.
This is used to control the writing of digitalized luminance data D. That is, the luminance data DYa of the n-th line is
Period t, l/ which is obtained by dividing its own horizontal period t7 by m
Instead of the clock WCK.m, the write clock WCK. −． Therefore, it is written into the memory 5.

Similarly, the luminance data D Yn- of the (n-1)th line
1 is the cycle Ly1-! corresponding to the luminance signal Y7-2 one horizontal period ago! /m writing Cl7k W C K ,l
- written to memory 5 by z, (n + 1
) line luminance data Dyg+1 is a write clock WCK. It is written by

In this way, the jitter, which is the time axis error included in the luminance signal for a certain period, and the jitter included in the write clock for writing this luminance signal into the memory 5 as luminance data match. It means that it is not.

Furthermore, since the PLL circuit 2 has a response delay, the mismatch between the jitter of the luminance signal and the jitter of the write clock becomes larger.

On the other hand, the period of the read clock RCK is obtained by dividing one normal horizontal period t0 of the luminance signal by m. Therefore,
Even if the luminance data read from the memory 5 at the k-th clock of the read clock RCK is the luminance data written to the memory 5 at the k-th write clock WCK in the (n-1)th line, , in the nth line, the luminance data is written in the (k+1)th clock, and in the (n+1)th line, it is the luminance data written in the (k-1)th clock. As a result, in the image in which the analog luminance signal Y1 outputted from the D/A converter 9 appears on the display screen, when focusing on, for example, the k-th dot in each horizontal line, the horizontal time There was a problem that jitter remained in the axial direction. In the above explanation, the luminance signal Y was taken as an example of the object to be written into the memory 5, but the same problem exists in the case of a chroma signal.

The present invention was devised to solve the above problems, and its purpose is to provide a time base collector that can perform jitter correction with high accuracy.

(Means for Solving the Problem) In order to solve the above problem, the time base collector of the present invention has a clock synchronized with a jitter detection signal such as a horizontal synchronization signal separated from a video signal (luminance signal or chroma signal). In the time base collector, which is designed to write a video signal to the memory and read it from the memory using a cross signal with a stable period, a regular horizontal period and a write cross signal are generated from the jitter detection signal at a stage before the memory. A configuration is adopted in which a delay circuit is provided that delays the response by a time that is the sum of the response delay time when the signal is generated.

(Function) By setting the delay time of the delay circuit to the sum of one regular horizontal period and the response delay time when generating a write clock from the jitter detection signal, the When a video signal is written into the memory using a write clock, the jitter of the video signal and the jitter of the write clock will be lost.

(Embodiment) FIG. 1 is a block diagram showing the electrical configuration of a time base collector according to an embodiment of the present invention.

In the same figure, l is a synchronous separation circuit, 2 is a PLL circuit, and 3 is a synchronous separation circuit.
is a write address counter, 4 is an A/D converter, 5 is a memory, 6 is a crystal oscillator, 7 is an oscillation circuit, 8 is a read address counter, and 9 is a D/A converter. Since it is the same as the conventional example, the same reference numerals are given here and the explanation will be omitted.

In this embodiment, in addition to the above structure, a delay circuit IO having a predetermined delay time T is provided before the A/D converter 4, and the luminance signal Y is delayed by the delay time T0. This signal is configured to be output to the A/D converter 4 as a signal Y'. The delay time TI, is a regular horizontal period t. and PLL circuit 2 generate horizontal synchronization signal HD
This time is set to the sum of the response delay time when controlling the write clock WCK. Next, the operation of the above-mentioned time base collector will be explained with reference to the time chart shown in FIG. The PLL circuit 2 receives the horizontal synchronizing signal HD, of the (n-1)th line one horizontal period before, by receiving the horizontal synchronizing signal HD, of the n-th line. −． and the nth line horizontal synchronization signal HD. The time interval Lm-1 between the luminance signal Yfi-1 of the (n-1)th line is detected as the horizontal period of the luminance signal Yfi-1 of the (n-1)th line, and after a certain response delay time, the luminance signal Y. -1 horizontal period tE1 divided into m (integer constant) write clock WCK.with period LR-17m. ．． Output. The first pulse of this write clock WCKn-1 is output ξ
The (n-1)th line horizontal synchronization signal HD. −、
This is the point in time when delay time T has elapsed since the time when was input.

On the other hand, the (n-1)th line luminance signal Yfi-. is delayed by delay time T0 by the delay circuit 10, and the luminance signal Y. ．． ' is input to the A/D converter 4. And digic from A/D converter 4? converted luminance data D
'/n-, is output to the memory 5, and the luminance signal Ya-
The data is written into the memory 5 using a write clock WCK,%-1 with a cycle t■,/m, which is obtained by dividing the horizontal period t,-1 of +' by m.

Similarly, the nth line luminance signal Y7 is delayed by the delay time TEl by the delay circuit 10, and the luminance signal Y7
' is input to the A/D converter 4. Then, the digitized luminance data Dy* is outputted from the A/D converter 4 to the memory 5, and is written into the memory 5 by the write clock WCKR with a period "n/m", which is obtained by dividing the horizontal period 1n of the luminance signal Y7' by m. .In addition, the (n+1)th line luminance signal Y■1 is also delayed by the delay circuit 10.
The signal is delayed by D and is input to the A/D converter 4 as a luminance signal Y7.1'. Then, the luminance data D is digitized from the A/D converter 4. is output to the memory 5, and the luminance signal Y. The horizontal period tR01 of 1' is divided into m, and the write clock WCK. has a period t@OH/m. −
is written to memory 5 by r. In this way, the delayed luminance signal Y' of any line has its own write clock WCK which equally divides one horizontal period into m.
As a result, the jitter included in the luminance signal Y and the jitter included in the write clock WCK match.

Therefore, the luminance data of each line is read out from the memory 5 by the readout clock RCK with a period t,/m, which is obtained by dividing one normal horizontal period t0 of the luminance signal by m, for example, the luminance data is read out at the kth hundredth clock of each readout clock RCK. The luminance data of any line is the luminance data DV.
Also, this is the luminance data written by the k-th clock of each write clock WCK. As a result, as shown in Figure 3, when focusing on, for example, the k-th dot of each horizontal line in the image appearing on the display screen, there is no shift in the horizontal time axis direction, and jitter correction is performed with high precision. It turns out. Note that the present invention is not limited to the above embodiments, and may be applied to chroma signals instead of luminance signals. Also, the writing of the luminance data DV to the memory 5 is performed with a predetermined delay time T.
The delay circuit 10 may be inserted between the A/D converter 4 and the memory 5 because the delay circuit 10 only needs to be delayed by D.

(Effects of the Invention) Since the time base collector of the present invention is configured to write the video signal into the memory through the delay circuit, the delay time of the delay circuit is determined by generating the write clock from one regular horizontal period and the jitter detection signal. By setting the time to include the response delay time at a certain time, the video signal that has passed through the delay circuit can be written by a crosshair that is synchronized with a jitter detection signal such as a horizontal synchronization signal separated from the video signal. Since the jitter of the video signal and the jitter of the writing crosslink match, the jitter can be corrected with high precision.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the electrical configuration of a time base collector according to an embodiment of the present invention, Fig. 2 is a time chart for explaining the operation of the embodiment, and Fig. 3 is a state of jitter correction. FIG. 4 is a block diagram showing the electrical configuration of a conventional digital time base collector, FIG. 5 is a time chart for explaining the operation of the conventional example, and FIG. FIG. 3 is a diagram of a display screen showing how jitter correction is performed in a conventional example. l...Synchronization separation circuit 2...PLL circuit 3...Write address counter 4...A/D converter 5...Memory 6...Crystal oscillator 7...Oscillation circuit 8...・Read address counter 9...D/A converter 10...Delay circuit Y...Luminance signal Y'...Delayed luminance signal H D...Horizontal synchronization signal WCK...Write cross clock RCK ...Read clock To...Delay time t. ．． ;-. i. J Figure 2 Figure 3

Claims (1)

[Claims] 1) A time base configured to write a video signal into a memory using a clock synchronized with a jitter detection signal such as a horizontal synchronization signal separated from the video signal, and read it from the memory using a clock with a stable period. In the collector, a delay circuit is provided at a stage before the memory, the delay circuit delaying by the sum of one regular horizontal period and a response delay time when generating a write clock from the jitter detection signal. timebase collector.