JP2573213B2 - Horizontal sync signal regeneration circuit - Google Patents

Description

The present invention relates to a horizontal synchronizing signal reproducing circuit for reproducing a horizontal synchronizing signal synchronized with a horizontal synchronizing signal separated from a video signal.

(Prior Art) In a video receiver, in order to receive a transmitted video signal and output it to a screen, a synchronization signal added to the transmitted video signal is exposed, and a phase locked loop is added to the synchronization signal. A circuit (hereinafter, PLL circuit) must be locked and a synchronization signal having a stable period must be reproduced.

Conventionally, a PLL circuit for reproducing a horizontal synchronizing signal uses a method called an area comparison type. Hereinafter, an outline of the above method will be described.

FIG. 6A shows a video signal of a television broadcast, and a slice signal is sliced at a dotted line level to obtain a synchronization signal shown in FIG. 6B. FIG. 6 (c) shows a horizontal synchronizing signal generated by the PLL circuit. The rising edge comes almost at the center of the portion ((α)) where the signal level in FIG. To stabilize the horizontal synchronizing signal. This is to make the area of the plus side and the minus side of the signal obtained by inverting the minus part of the signal of FIG. 6 (b) by the polarity of the signal of FIG. 6 (b), the area on the plus side and the minus side in FIG. 6 (d) change, and The horizontal synchronization signal is stabilized by moving the signal shown in FIG.

However, according to the above conventional method, when a video signal as shown in FIG. 7A is transmitted, the sliced signal has a waveform as shown in FIG. 7B. FIG. 7 (b)
When signals other than the synchronization signal are sliced as in
In order to make the areas on the plus side and the minus side equal as shown in FIG. 7 (b), the rising edge of the waveform in FIG. 7 (c) is synchronized with the synchronization signal section (β) shown in FIG. 7 (b). 7 (c), and the period of the signal shown in FIG. 7 (c) is not determined, and appears as jitter.

As described above, the area comparison type PLL synchronization circuit possibly includes the possibility of a period shift due to noise.

(Problems to be Solved by the Invention) In the PLL circuit for reproducing the horizontal synchronization signal of the area comparison type, the technical point is to separate the synchronization signal from the burst signal and the video signal. As shown in FIG. 7A, the slicing process was performed. However, according to this method, the periodicity of the synchronization signal is lost due to leakage of the burst signal or the video signal or noise, which causes jitter.

Accordingly, an object of the present invention is to provide a horizontal synchronizing signal reproducing circuit capable of stabilizing the period of a reproducing horizontal synchronizing signal by more completely separating a synchronizing signal from a burst signal and a video component. And

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, according to the present invention, an 8-bit digital signal represented by a 2's complement of the video signal of FIG. (Hereinafter, this type of digital signal is referred to as 2 '
The slice is performed by setting the dotted line level in FIG. In the sliced signal of FIG. 5 (b), the portion where the sign bit is set, that is,
The portion having a negative value is considered to be a synchronization signal, and the sign bit is as shown in FIG. 5 (c). Next, a mask signal for horizontal synchronization as shown in FIG. However, the mask signal shown in FIG. 5D is not operated until the synchronization signal is locked. Whether the synchronization signal is locked or not is determined by latching the sign bit shown in FIG. 5C at the rising edge of the area comparison horizontal synchronization signal shown in FIG. 5E, and setting the latched signal to "H". (High level), judge that it is locked,
When it is “L” (low level), it is determined that the lock is unlocked. After the lock is confirmed in this way, the mask signal shown in FIG. 5D is applied to the signal shown in FIG. 5A. Further, as shown in FIG. 5B, the slice level for extracting the synchronization signal is made closer to the pedestal level.

(Operation) The mask signal of the horizontal synchronization signal is generated as described above, and the PLL is generated.
According to the configuration in which the video signal is masked only when the circuit is locked, it is possible to extract only the synchronizing signal even when a signal containing noise as shown in FIG. 7A is transmitted. In addition, the depth of the synchronization signal can be completely reproduced.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. Hereinafter, the configuration and operation of the circuit shown in FIG. 1 will be described with reference to FIG.

In FIG. 1, an analog / digital conversion circuit (hereinafter, referred to as an A / D conversion circuit) 1 receives a video signal shown in FIG. 2 (a). Since the video signal converted to digital by the A / D conversion circuit 1 is 8-bit straight data, it is converted to 8-bit 2 'data (see FIG. 2 (b)) through the 2' operation circuit 2. This 2 'data is input to the data buffer circuit 3 with clear. The data output from the data buffer circuit 3 is controlled by a pulse supplied to a clear terminal. The output of the data buffer circuit 3 is one input of the adder circuit 6. The other input of the adder circuit 6 has a fixed value as shown in FIG. 2 (b) from which a synchronizing signal can be extracted without the 0 level being caught by the burst signal. The output of the adder circuit 6 is shown in FIG. The minus part of the output of the adder circuit 6 is the part of the synchronizing signal and the part where the video signal overflows. However, since the required signal is only the synchronizing signal,
The most significant bit (hereinafter referred to as MSB), which is the sign bit of the input and output of the adder circuit 6, is one bit at a time [FIG. 2 (b ').
And (c ') in FIG. 2 to the AND circuit 11, thereby generating a mask signal [refer to the mask signal (b'). Times. (C ') in FIG. 2] for extracting the synchronizing signal.

The AND circuits 12 to 19 generate a synchronizing signal from the output signal of the adder circuit 6 shown in FIG. 2C by using the mask signal [see the mask signal (b '). Times. (C') in FIG. The slice synchronization signal (sliced digital 8-bit synchronization signal) shown in FIG.
Are output to exclusive OR circuits 20 to 27. The output (sign bit of the video signal) of the AND circuit 12, which is the MSB of the slice synchronization signal, is “L” when the value of the slice synchronization signal is 0 level, because the slice synchronization signal is represented by two's complement. When the signal is at a negative level, the signal becomes "H", and the signal shown in FIG. The output of the AND circuit 12 [see FIG. 2 (d)] is output from the lock determination circuit 8, UP (up).
Edge one-shot pulse generation circuit 9, DOWN
The edge one-shot pulse generation circuit 10 is input to the edge one-shot pulse generation circuit 9, and the UP edge one-shot pulse generation circuit 9 and the DOWN edge one-shot pulse generation circuit 10 are controlled by the edge of the output pulse of the AND circuit 12,
The pulse shown in (f) is output, and an image mask signal (see FIG. 2 (g)) is created by the AND circuit 5.
The video mask signal shown in FIG. 2 (g) may be generated by using a counter circuit which starts counting by the output of the AND circuit 12 instead of the AND circuit 5 and the pulse generating circuits 9 and 10. .

On the other hand, the sliced digital 8-bit slice synchronization signal (see FIG. 2 slice synchronization signal) is supplied from AND circuits 12 to 19 to exclusive OR circuits (hereinafter referred to as EXOR circuits) 20 to 27. ing. The other inputs of the EXOR circuits 20 to 27 are the signals shown in FIG.
OR circuits 20 to 27, loop filter 28, horizontal synchronization generation circuit 29
Is a 50% duty horizontal synchronization signal reproduced by the area comparison PLL circuit composed of When the above-mentioned PLL circuit is in the locked state, the rising edge of the reproduced horizontal synchronizing signal shown in FIG. 2H corresponds to the portion where the synchronizing signal shown in FIG. In this case, the lock determination circuit 8 uses this principle to latch the signal shown in FIG. 2 (d) at the rising edge of the signal shown in FIG. 2 (h). Output is “H”
Is locked, and "L" is unlocked. When a video signal containing noise as shown in FIG. 3A is sent, the PLL circuit may be locked by the noise. In this case, the AND circuit shown in FIG. 3B is used. The rising edge of the output of the horizontal synchronization generation circuit 29 shown in FIG. 3 (c) does not come to the "H" portion of the 12 output, and the output of the lock determination circuit 8 becomes "L". As described above, the output of the lock determination circuit 8 becomes “H” only when the PLL circuit is locked to the transmitted horizontal synchronization signal.

The NAND circuit 4 receives the video mask signal shown in FIG. 2 (g) and the output of the lock determination circuit 8, and the output is input to the clear terminal of the data buffer circuit 3. In other words, the video mask signal output from the AND circuit 5 becomes effective when [see FIG. 2 (g)] is valid only when the horizontal synchronization signal is locked to the normal horizontal synchronization transmitted. . By controlling the mask signal using the lock signal in this manner, the synchronization signal is not masked by mistake, and only the video signal can be masked and set to the 0 level. FIG. 2 (i) shows the transmitted signal after masking.

The output of the lock determination circuit 8 is also input to the slice level setting circuit 7, which operates when the PLL circuit is locked, the video mask signal is activated, and as shown in FIG. This is for controlling the slice level to be close to the pedestal level so that the transmitted synchronization signal can be fully used because the signal is completely removed. When the output of the lock determination circuit 8 becomes "H", the slice level rises, and the transmitted synchronization signal is reproduced almost without being deleted as shown in FIG. 2 (j).

The reason why it is effective to reproduce a synchronizing signal in almost perfect form is that when a synchronizing signal is digitally formed, if the binarization is performed as shown in FIG. Synchronized signals reproduced by edge slopes or slice level fluctuations contain considerable errors. However, in order to reproduce analog area comparison type PLL circuits faithfully, errors are reduced by using digital 8 bits. Because you can.

As described above, in this embodiment, the lock determination circuit determines whether or not the phases of the separated horizontal synchronization signal from the AND circuits 12 to 19 and the reproduced horizontal synchronization signal from the horizontal synchronization generation circuit 29 match. 8 and if they match, the video mask signal from the AND circuit 5 is sent to the data buffer circuit 3
And the slice level in the adder circuit 6 is made closer to the pedestal level side.

Therefore, according to this embodiment, it is possible to prevent the leakage of the video component and the burst signal from the separated output of the horizontal synchronizing signal and the incorporation of noise, and to stabilize the cycle of the reproduced horizontal synchronizing signal.

Note that both the correction of the slice level at the time of locking and the masking of the video period are not always necessary at the same time, and it is possible to improve the synchronization performance with only one of them.

Although one embodiment of the present invention has been described above, the present invention is not limited to such an embodiment, and it goes without saying that various other modifications can be made.

[Effects of the Invention] As described above, according to the present invention, only the horizontal synchronization signal portion can be extracted from the transmitted video signal with the horizontal synchronization signal, so that almost perfect synchronization signals can be reproduced. As a result, it is possible to suppress the jitter of the synchronization signal as in the related art, and to improve the periodicity accuracy.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention,
2 to 4 are timing charts for explaining the operation, FIG. 5 is a timing chart for explaining the outline of the present invention, and FIGS. 6 and 7 show a conventional horizontal synchronizing signal reproducing circuit. 6 is a timing chart shown for explanation. 1 A / D conversion circuit, 2 2 'arithmetic circuit, 3 data buffer circuit, 4 NAND circuit, 5, 11 to 19 AND circuit, 6 adder circuit, 7 slice Level setting circuit, 8 Lock determination circuit, 9 UP edge one-shot pulse generation circuit, 10 DOWN edge one-shot pulse generation circuit, 20 to 27 EXOR circuit, 28 Loop filter, 29 Horizontal synchronization signal generation circuit.

Claims (2)

(57) [Claims] 1. A synchronization signal output means for comparing an input terminal to which a video signal having a video period and a synchronization period is input with a predetermined separation level, and outputting a synchronization signal according to the comparison result. And a PLL for generating a signal having a horizontal cycle synchronized with the synchronization signal
Synchronization signal means; phase difference detection means for detecting a phase difference between the synchronization signal and the output of the PLL synchronization signal means; and a mask for generating a mask signal for masking a video period of the video signal in accordance with the synchronization signal. And a signal generation unit. The synchronization signal output unit, when the phase difference detection unit detects that the phase is matched, a video signal in which the video period of the video signal is masked by the mask signal. A horizontal synchronizing signal reproducing circuit for outputting a synchronizing signal using the same. 2. An input terminal to which a video signal is input, a synchronization signal output means for comparing the video signal with a predetermined separation level, and outputting a synchronization signal in accordance with the comparison result; PLL that generates a signal with a fixed horizontal period
A synchronization signal unit; and a phase difference detection unit that detects a phase difference between the synchronization signal and the output of the PLL synchronization signal unit. The synchronization signal output unit is in phase with the phase difference detection unit. A horizontal synchronizing signal reproducing circuit, wherein when the detection is made, the separation level is made closer to a pedestal level of the video signal.