JPH0779168B2 - Constant voltage diode - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is used in the field of semiconductor devices.

The present invention relates to a constant voltage diode, and more particularly to a structure of a punch-through type low withstand voltage constant voltage diode having an N ⁺ PN ⁻ structure.

〔Overview〕

The present invention has a structure in which a P base layer and an N ^- collector layer of an N ⁺ PN ^- transistor are short-circuited, and a constant voltage diode using punch-through of the P base layer is formed on an outer peripheral portion of the P base layer. and P ⁺ impurity concentration and diffusion depth of guard ring layer so as to be larger than conventional, N having a sufficient diffusion depth in the outer peripheral portion of the N ⁺ emitter layer ⁺
By forming the guard ring layer, the surface breakdown of the diode is prevented and the characteristics are improved.

[Conventional technology]

Conventionally, a punch-through type constant voltage diode is formed by epitaxial growth on an N ⁺ semiconductor substrate 1 having an N type high impurity concentration (N ⁺ ) as shown in FIG.
N of ^- type low impurity concentration (N) ^- a collector layer 2, the P base layer 3 of P-type impurities in products concentration formed by ion implantation (P), is formed by ion implantation in the base layer 3
There is an N ⁺ emitter layer 5, and the P base layer 3 and the N ⁻ collector layer are short-circuited by a short-circuit electrode 8 on the surface. By using the V _EB breakdown voltage characteristic of the N ⁻ PN ⁺ transistor and setting the width of the P base layer 3 to about 1 μm, the depletion layer of the P base layer 3 becomes an N ⁻ collector when a low V _EB voltage is applied. Punch-through is performed on the layer 2 and the N ⁻ PN ⁺ transistor breaks down, and this breakdown characteristic is used for the Zener diode characteristic.

[Problems to be solved by the invention]

The conventional punch-through type constant voltage diode described above is
The impurity concentration of each layer is about 1 × 10 ¹⁶ cm ^-3 in the P base layer ³ ,
The N ⁺ emitter layer 5 has a breakdown voltage of about 1 × 10 ¹⁸ cm ⁻³ , and the N ⁻ collector layer 2 has a breakdown voltage of about (5 to 10) × 10 ¹⁴ cm ^−3.
V _z = 3-4V.

In this case, since the impurity concentration of the P base layer 3 is relatively low and channel leak is likely to occur on the silicon surface, the P ⁺ guard ring layer 4a of P type high impurity concentration (P ⁺ ) is formed on the outer periphery of the P base. However, the influence of channel leak is reduced. However, in this structure, a breakdown often occurs on the surface, so that the surface breakdown voltage V _s is generated as shown in FIG.
There was a drawback that a step breakdown waveform was seen and the characteristics deteriorated. This is due to contamination of the passivation film,
This occurs when the interface of the P base layer 3 becomes an accumulation state and becomes P ⁺ , this portion becomes an N ⁺ P ⁺ junction, and this portion breaks down.

It is an object of the present invention to provide a punch-through type constant voltage diode in which surface breakdown is prevented and characteristics are improved by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The present invention relates to an N ⁻ collector layer formed in a region on an N ⁺ silicon semiconductor substrate, a P base layer formed in the region of the N ⁻ collector layer, and a P base layer formed in the region of the P base layer. A punch-through type constant layer having an N ⁺ emitter layer, a short-circuit electrode connecting the N ⁻ collector layer and the P base layer, and a P ⁺ guard ring layer formed on the outer peripheral portion of the P base layer. In the voltage diode, the P ⁺ guard ring layer is
It is formed by being bonded to the outer peripheral portion of the N ⁺ emitter layer and has a surface concentration of impurities of 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁸ cm 3.
^-3, its has a diffusion depth is the P base layer 2 times or more the diffusion depth, the outer peripheral portion and the P ⁺ diffusion depth junction between the guard ring layer of the N ⁺ emitter layer is the N ⁺ It is characterized in that an N ⁺ guard ring layer having a diffusion depth of at least twice the emitter layer is formed.

[Action]

Since the diffusion depth of the N ⁺ guard ring layer formed on the outer peripheral portion of the N ⁺ emitter layer, that is, the outer peripheral portion of the emitter base junction is twice or more that of the N ⁺ layer, it is injected from the emitter to the base at the surface. Block the electrons that are generated.

Further, the surface concentration of impurities in the P ⁺ guard ring layer is approximately 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ , and the P base layer (1
X 10 ¹⁶ cm ^-3 ), and its diffusion depth is more than twice that of the P base layer, so that holes are prevented from leaking to the interface and the interface of the P base layer is accumulated. Never be. Furthermore, the V _EB breakdown voltage at the outer periphery is sufficiently higher than the punch through voltage.

Therefore, the surface breakdown due to the surface leakage can be prevented, and the V _EB breakdown voltage is always determined by the punch-through voltage of the N ⁺ PN ⁻ transistor, so that the break break characteristic can be improved.

Note that, as described above, the N ⁺ guard ring layer and the P ⁺ guard ring layer have a surface concentration of impurities and a diffusion depth of about N in order for the N ⁺ guard ring layer to have a sufficient guard effect. 1 × 10 ¹⁸ cm ^-3 (same as N ⁺ emitter layer)
^Therefore , the diffusion depth should be at least twice that of the N ⁺ emitter layer, approximately (1 × 10 ¹⁷ to 1 × 10 ¹⁸ ) cm ^-3 in the P ⁺ guard ring layer, and the diffusion depth should be at least twice that of the P base layer. Good.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic sectional view showing a first embodiment of the present invention, showing a vertical structure.

In the first embodiment, an N ^- collector layer 2, a P base layer 3 and an N ⁺ emitter layer 5, each of which is formed of an epitaxial layer sequentially stacked at a predetermined position on the N ⁺ semiconductor substrate 1, and an N ^- collector layer. 2 and the P base layer 3 for connecting the short-circuit electrode 8;
It is formed on the outer peripheral portion of the P base layer 3 and has a surface concentration of impurities of about (1 × 10 ¹⁷ to 1 × 10 ¹⁸ ) cm ⁻³ and a diffusion depth of P.
A P ⁺ guard ring layer 4 is more than twice the diffusion depth of the base layer 3, N ⁺ outer peripheral portion formed diffusion depth of the emitter layer 5 is at least twice the diffusion depth of the N ⁺ emitter layer 5 and N ⁺ guard ring layer 6 is, N ⁺ and an anode electrode 12 formed on the lower surface of the semiconductor substrate 1, and a cathode electrode 11 formed on the N ⁺ emitter layer 5.

In FIG. 1, 7 is the N ⁻ collector layer and the short-circuit electrode 8
N is an N ⁺ layer for connecting with, 9 is an oxide film, and 10 is a CVD oxide film.

The feature of the present invention is that the N ⁺ guard ring layer 6 is formed in FIG. 1 and the surface concentration of impurities in the P ⁺ guard ring layer 7 is set to (1
× 10 ¹⁷ to 1 × 10 ¹⁸ ) cm ⁻³ , and the diffusion depth thereof is twice or more that of the P base layer 3.

Next, the manufacturing method of the first embodiment will be described. First, a low concentration N ^- collector layer 2 is formed on an N ⁺ semiconductor (silicon) substrate 1.
Are formed by an epitaxial method. Next, by masking, the P ⁺ guard ring layer 4 is selectively formed on the N ⁻ collector layer 2 by boron diffusion.

Next, by ion implantation, the P base layer 3 is pre-diffused, and phosphorus is diffused after masking to selectively form the N ⁺ guard ring layer 6 and the N ⁺ layer 7 on the outer side thereof.

Further, masking is performed, the N ⁺ emitter layer 5 is selectively formed by the ion implantation method, and then the cathode electrode 11 and the anode electrode 12 are formed.

The surface concentration of the P ⁺ guard ring layer 4 is approximately (1 × 10 ¹⁷ to 1 × 10
¹⁸ ) cm ^-3 , surface concentration of N ⁺ guard ring layer 6 is about 1 × 10 ¹⁸
cm ^-3 , and the junction depth is about 4μ for the P ⁺ guard ring layer 4.
m, P base layer 3 is about 2 μm, N ⁺ guard ring layer 6 is about 2 μm, and N ⁺ emitter layer 5 is about 1 μm.

As a result of measuring the breakdown characteristics of the first embodiment, unlike the conventional example shown in FIG. 4, the surface breakdown voltage V _s was not observed, but the steep breakdown voltage V _z was observed.

FIG. 2 is a schematic sectional view showing a second embodiment of the present invention, showing a model structure.

The second embodiment is similar to the first embodiment described above except that the anode electrode 32 is formed on the surface of the substrate in the same manner as the cathode electrode 31, and the effects are also the same. Be effective.

In FIG. 2, 21 is an N ⁺ semiconductor substrate, 22 is an N ⁻ collector layer, 23 is a P base layer, 24 is a P ⁺ guard ring layer, and 25 is
N ⁺ emitter layer, 26 N ⁺ guard ring layer, 27 N ⁺ layer and
28 is a short circuit electrode.

〔The invention's effect〕

As described above, according to the present invention, since the high-concentration guard ring is formed on the surface of the P base layer, the influence of surface contamination or the like is small, and the V _EB breakdown voltage of the outer peripheral portion is the punch through voltage. because the more high enough, V _EB breakdown voltage,必Razz N ⁺ PN ^-
Determined by the punch through voltage of the transistor.

Therefore, there is an effect that good breakdown characteristics in which a two-stage breakdown waveform does not occur are not affected by the contamination of passivation and the like.

[Brief description of drawings]

FIG. 1 is a schematic sectional view showing a first embodiment of the present invention. FIG. 2 is a schematic sectional view showing a second embodiment of the present invention. FIG. 3 is a schematic sectional view showing a conventional example. Figure 4 shows the breakdown characteristics. 1, 21 …… N ⁺ semiconductor substrate, 2, 22 …… N ^- collector layer,
3, 23 ...... P base layer, 4, 4a, 24 ...... P ⁺ guard ring layer, 5, 25 …… N ⁺ emitter layer, 6, 26 …… N ⁺ guard ring layer, 7, 27 …… N ⁺ Layer, 8, 28 ... Short-circuit electrode, 9 ... Oxide film, 10 ... CVD oxide film, 11, 31 ... Cathode electrode, 1
2, 32 ... Anode electrode.

Claims (1)

[Claims] 1. An N ⁻ collector layer (2, 22) formed in a region on an N ⁺ silicon semiconductor substrate (1, 21) and a P base layer (2) formed in the region of this N ⁻ collector layer. 3, 23),
The N ⁺ emitter layer (5, 2) formed in this P base region
5), a short-through electrode (8, 28) connecting the N ^- collector layer and the P base layer, and a P ⁺ guard ring layer formed on the outer peripheral portion of the P base layer. In the constant voltage diode, the P ⁺ guard ring layer (4, 24) is formed by being joined to the outer peripheral portion of the N ⁺ emitter layer, and the surface concentration of the impurities is 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁸ cm ^-3 , the diffusion depth is more than twice the diffusion depth of the P base layer, and the diffusion depth at the junction between the outer peripheral portion of the N ⁺ emitter layer and the P ⁺ guard ring layer. Forming a N ⁺ guard ring layer (6, 26) having a diffusion depth of at least twice the N ⁺ emitter layer.