JPH0744228B2 - Static type semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static semiconductor memory device, and more specifically, each drain is connected to a load element and each gate is cross-connected to another drain. To improve a memory cell of a static semiconductor memory device in which data information is stored by a pair of MOS field effect transistors described above.

[Conventional technology]

As a static semiconductor memory device of this kind in a conventional example, here, a high resistance load type memory cell used in a so-called Static Random Access Memory (hereinafter, referred to as SRAM) is used. The connection state of each element is shown in FIG.

In the circuit configuration according to the conventional example of FIG.
2,33 and 34 are so-called M, as Q1, Q2, Q3 and Q4
OSFET (Metal Oxide Semiconductor Field Effect Tran
35 and 36 are high resistances shown as R1 and R2, which are the power supply potential (Vcc) 37, the ground potential (GND) 38,
Bit line (BL) 39, bit line (BL) 40 and word line (W
L) 43, respectively, as shown in the figure. In the figure, a is a wiring part made of a diffusion layer, and b is a wiring part made of polysilicon.

The MOSFETs (Q3, Q4) 33, 34 have their drains and gates cross-connected to each other to form a flip-flop circuit having two stable states, by which bit information (data) is transferred. Specifically, one of the memory cell nodes MC 41 is set to the “High” level potential and the other memory cell node MC 42 is set to the “Low” level potential, or the opposite state. To store 1-bit information.

The high resistances 35 and 36 connect the power supply potential (Vcc) 37 and the memory cell node MC 41 or MC 42.

Furthermore, the gates of the MOSFETs (Q1, Q2) 31, 32 are connected to the word line 43, and when the memory cell is selected, that is, when the word line 43 is at the "High" level, the memory cell node MC 41 and MC 42 serve to connect the bit lines 39 and 40 and are used for reading data from and writing data to the memory cells.

Next, FIG. 9 is a plan view of the high resistance load type SRAM memory cell, and FIG. 10 is the SR pattern shown in FIG.
Figure 3 shows a simplified plan pattern view of an AM memory cell.

In FIGS. 9 and 10, reference numeral 1 is an element isolation region, and an oxide film having a large film thickness is usually used for this isolation region.

In addition, 2a to 2c indicate the first polysilicon layer of the first layer, and of these, 2a is a word line, and each of the MOSFETs (Q1, Q2) 31 is a word line except the element isolation region 1. , 32
It also serves as the gate electrode of the
It serves as the gate electrode of T (Q4, Q3) 34, 33.

And, 4a to 4c indicate the second polysilicon layer of the second layer, among them, 4a is a wiring of the power supply potential (Vcc) 37, and 4b is used for a cross-coupled wiring in the memory cell. Through the first buried contact hole 3b
With the drain of MOSFET (Q4) 34 and the gate of MOSFET (Q3) 33
The source of the MOSFET (Q2) 32 is mutually connected, and 4c is the MOSFET (Q4) via the first buried contact hole 3c.
It connects the gate of 34 and the source of MOSFET (Q1) 31.

Further, 6 denotes a third polysilicon layer which is the third layer, and high resistances (R1, R2) 35 and 36 are formed by this layer, and a power supply potential ( Vc
c) It is connected to the wiring 4a of 37 and is connected to the memory cell nodes MC 41 and MC 42 through the second buried contact holes 5b and 5c.

Although not shown here, 7a and 7b are separate contact holes, but in the normal case, the bit line (BL) 39 and the bit line (BL) 40 made of aluminum or the like are connected to the respective MOSFETs.
(Q1, Q2) Connected to the drains of 31 and 32.

Next, FIG. 11 shows a cross-sectional view of the device configuration along the line XI-XI in FIG. 10 described above. In this case, in order to simplify the illustrated mode, each MOSFET (Q1, Q2, Q3 And Q
4) The respective portions formed after the gate electrode at 31, 32, 33 and 34 are omitted.

Here again, in FIG. 11, reference numerals 8a to 8d denote n ⁺ type diffusion regions formed on the main surface of the p type silicon semiconductor substrate 9, of which 8a and 8b are MOSFETs (Q3). The source and drain regions of 33, and 8d and 8c are MOSFET (Q4) 34
Source and drain regions. Further, 10 and 10 indicate respective gate oxide films.

[Problems to be Solved by the Invention]

A conventional high resistance load type SRAM configured as described above.
In memory cells, along with the increase in memory capacity, miniaturization is being made in each element configuration part, and this miniaturization is promoted not only in the planar direction but also in the stacking direction. It causes various problems as mentioned above.

a) Increase in sheet resistance in n ⁺ type diffusion region The channel length of the MOSFET tends to be reduced due to miniaturization. For example, the gate oxide film 10 Thin film, n ⁺ type diffusion regions 8a to 8d
However, it is necessary to form a shallow n ⁺ -p junction, but if the n ⁺ -type diffusion region is made shallow in this way, the sheet resistance of the region is increased, and as shown in FIG. As shown in Figure 10, on the other hand, this n ⁺ -type diffusion region is also used as each wiring connection in the memory cell and as the GND wiring of the memory cell, so the increase in parasitic resistance here This will affect the operation of the memory cell.

For example, if the sheet resistance from the channel in the drain of the MOSFET (Q3) 33 to the first buried contact hole 3c increases, the current drive capability of the MOSFET (Q3) 33 decreases substantially, resulting in symmetric There is a possibility that the so-called two stable states cannot be maintained due to the asymmetry generated in the memory cell configured in.

Further, the bit line 39 generates a potential between the bit line (BL) 39 and the bit line (BL) 40 in order to discharge the electric charge through each MOSFET (Q1, Q3) 31, 33, In the read operation for transmitting the stored contents to the outside, the increase in the sheet resistance at the drain increases the time taken to discharge the charges, which increases the access time in the SRAM. The above-mentioned asymmetry is likely to occur due to the parasitic resistance.

b) Increase in Subthreshold Current Generally, in MOSFET, it is known that when the channel length is shortened, the subthreshold current increases due to the short channel effect.

Here, in the circuit of FIG. 8, when the word line 43 is at the “Low” level, the MOSFETs (Q1, Q2) 31, 32 are turned off, and the MOSFETs (Q1, Q2) 31, 32 are turned off. Considering to hold the data by ignoring, for example, when the memory cell node MC 41 is at “High” level and the memory cell node MC 42 is at “Low” level, the MOSFET (Q3) 33 is turned off and the memory cell The node MC 41 is charged by the high resistance (R1) 35 and “Hig
The potential of the h "level can be held, that is, the data can be held.

In this case, if the power consumption of the entire chip is reduced along with the increase in memory capacity, high resistance (R1, R2) 3
The value of 5,36 increases, and there is a 1Mbit SRAM with a resistance value of several TΩ per resistor. In this case, on the other hand,
Since the channel length is reduced with the increase in capacity,
Originally, the off-state leakage current of each MOSFET (Q3, Q4) 33, 34, which could be ignored compared to the charging current of high resistance (R1, R2) 35, 36, is ignored as the sub-threshold current increases. It becomes impossible, and as a result, data retention becomes impossible.

c) Junction leak As described in the above item b), as the memory capacity increases, the values of the high resistances (R1, R2) 35 and 36 are set to maintain the power consumption of the entire chip reasonably. Is being considered,
For example, each time the memory capacity is quadrupled, its resistance value is also at least quadrupled in proportion to this, but on the other hand, the leak current value at this time is quadrupled in inverse proportion to this. It is extremely difficult to achieve this, and one of the factors is so-called junction leak in addition to the subthreshold leak described above.

That is, the drain in the MOSFET is the region 8 in FIG.
As can be seen in b and 8c, there is inevitably an n ⁺ -p junction with the silicon semiconductor substrate 9, and the reverse leakage of this junction is physically unavoidable. The junction leak at this time is proportional to the junction area and the edge length of the junction. Of these, the junction area is reduced as the element structure becomes finer, but the edge length is reduced. Has not been reduced so much, and it has become very difficult to reduce the junction leak.

d) Increase in soft error rate As memory cell area shrinks, memory cell node MC
Since the area of the gate electrode or the junction forming the capacitance in 41, MC42 decreases in proportion to this, the node capacitance decreases in inverse proportion to the increase in memory capacitance. The decrease in the node capacity also means a decrease in the accumulated charge in the memory cell node, and as a result, there is a disadvantage that it becomes weak against a soft error caused by noise charge such as so-called extraneous α rays.

e) Isolation between elements Needless to say, the miniaturization of the element structure also requires the miniaturization of the isolation width in the element isolation region 1, which results in a decrease in the breakdown voltage between elements and a leakage current. Will result in an increase.

The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a static semiconductor memory device of this type which is suitable for large capacity and low power consumption. , To provide a high resistance load type SRAM memory cell.

[Means for Solving the Problems]

In the first aspect of the present invention, a pair of drain regions are connected to a power source through a load element, and respective gates are cross-connected to other drain regions.
In a static semiconductor memory device having a memory cell configured to store data information by a MOS field effect transistor, each MOS field effect transistor is independently provided on a main surface of a first conductivity type semiconductor substrate. A polysilicon layer containing impurities of the second conductivity type formed to be separated from each other so as to define a channel region, and formed on the main surface of the semiconductor substrate below the polysilicon layer by impurity diffusion from the polysilicon layer, The source and drain regions whose ends are defined by the edges of the polysilicon layer, and the channel region and the polysilicon layer located between the source and drain regions of the semiconductor substrate, via the gate insulating film. And a formed gate electrode,
Further, it is provided on the main surface of the semiconductor substrate between the polysilicon layers of the pair of MOS field effect transistors, and is provided with an element isolation region having substantially the same thickness as the thickness of the polysilicon layer.

A static semiconductor memory device according to a second aspect of the present invention is a semiconductor substrate of a first conductivity type having a main surface, a source region of a second conductivity type formed on the main surface of the semiconductor substrate, In contact with a first polysilicon wiring formed of a first polysilicon layer containing a conductivity type impurity,
A gate insulating film is formed on the drain region of the second conductivity type formed on the main surface of the semiconductor substrate by impurity diffusion from the polysilicon wiring and on the channel region of the main surface of the semiconductor substrate sandwiched by the source and drain regions. A first driver transistor having a gate electrode formed of a first conductive layer, a source region of a second conductivity type formed on the main surface of the semiconductor substrate, and a first polysilicon wiring It is in contact with a polysilicon member formed of the first polysilicon layer, is formed on the main surface of the semiconductor substrate by impurity diffusion from the polysilicon member, and is formed as a second layer above the first polysilicon layer.
Drain region of the second conductivity type connected to the gate electrode of the first driver transistor by the second polysilicon wiring formed from the polysilicon layer and the main surface of the semiconductor substrate sandwiched between the source and drain regions. A second driver transistor having a gate electrode formed on the channel region of the first conductive layer via a gate insulating film and connected to the first polysilicon wiring; and a drain region of the first driver transistor. A first load element connected between a predetermined potential wiring to which a predetermined potential is applied and a second load element connected between the drain region of the second driver transistor and the predetermined potential wiring. is there.

[Action]

According to a first aspect of the present invention, a MOS field effect transistor for storing data information has source and drain regions formed by diffusion from a polysilicon layer formed on a semiconductor substrate and defining a channel region. Therefore, the leakage current due to the parasitic resistance and the short channel effect can be reduced, and the stability and the data retention characteristic can be improved.

Also in the second aspect of the present invention, since the first and second driver transistors have the drain region diffused and formed from the first polysilicon layer, the parasitic resistance and the leak current due to the short channel effect are caused respectively. The stability and the data retention characteristic can be improved.

〔Example〕

Each embodiment of the static semiconductor memory device according to the present invention will be described in detail below with reference to FIGS. 1 to 7.

FIG. 1 is a plan view schematically showing a pattern of a high resistance load type SRAM memory cell corresponding to FIG. 10 to which the first embodiment of the present invention is applied, and FIG. 2 is a line II-II in FIG. FIG. 3 is a cross-sectional view showing an outline of a device configuration up to formation of a gate electrode in a portion, and FIG. 3 is a high resistance load type SRAM memory cell corresponding to FIG. 8 to which a second embodiment of the present invention is applied. FIG. 4 is a circuit connection diagram showing a connection state of elements, and FIG. 4 is a high resistance load type SR corresponding to FIG. 10 according to the second embodiment.
FIG. 5 is a schematic plan view showing a simplified plan pattern of an AM memory cell, FIG. 5 is a cross-sectional view showing an outline of a device configuration up to formation of a gate electrode in a VV line portion of FIG. 4, and further, FIG. Is the tenth embodiment to which the third embodiment of the present invention is applied.
FIG. 7 is a schematic plan view showing a simplified plan pattern of a high resistance load type SRAM memory cell corresponding to FIG.
FIG. 7 is a cross-sectional view showing an outline of a device configuration up to formation of a gate electrode in the I-VII line portion.

In each of the configurations of the embodiments shown in FIGS. 1 to 7, the same reference numerals as those in the conventional configuration shown in FIGS. 8 to 11 indicate the same or corresponding portions.

In each of the configurations of these embodiments, the present invention has source / drain regions formed of impurity regions diffused from a base polysilicon layer on a semiconductor substrate, instead of the MOSFET used in the conventional configuration, and A MOSFET having a structure in which a channel region is defined by the base polysilicon layer (hereinafter, this structure is referred to as a poly source / drain structure) is used.

By the way, as the prior art of MOSFET directly related to this poly source / drain structure, IEEE ELECTRON DE
VICE LETTERS, VOL.EDL-5, NO.10 p400-402 (OCTOBER 1
984), VOL.EDL-7, NO.5 p314-316 (MAY 1986) and V
A detailed description is given in OL.EDL-8, NO.4 p165-167 (APRIL 1987).

First, the structure of the first embodiment shown in FIGS. 1 and 2 is a high resistance load type SRAM memory cell using the MOSFET of the poly source / drain structure.

That is, the first of the configurations shown in FIGS. 1 and 2 is used.
The poly-source / drain structure MOSFET of the embodiment has a base polysilicon layer 11 containing n ⁺ -type impurities deposited and formed on a p-type silicon semiconductor substrate 9. The base polysilicon layer 11 is It becomes the base member of the MOSFETs (Q1, Q2, Q3 and Q4) 31, 32, 33 and 34 having the poly source / drain structure.

That is, the base polysilicon layer 11 is selectively etched away at a predetermined portion, and the desired element isolation region 12 is formed.
And at the same time, the gate region corresponding part 13 is selectively and partially etched away to form a thin gate oxide film 10 and then heat-treated to remove the remaining base polysilicon layer 11 Part, here
Due to the diffusion of impurities from the base polysilicon layer 11 corresponding to the source / drain regions, in the case of the cross section of FIG.
(Q3, Q4) 33 and 34 source and drain regions
8a to 8d are formed, and although not shown again, the source regions and drain regions of the MOSFETs (Q1, Q2) 31 and 32 are also formed in the same manner.

Here, a brief description will be given of the main manufacturing steps up to the formation of the gate electrode in the structure of the first embodiment using the MOSFET of the poly source / drain structure.

On the silicon semiconductor substrate 9, first, a base polysilicon layer 11 containing n ⁺ -type impurities is formed, and then the polysilicon layer 11 corresponding to the isolation region is selectively formed by photolithography and etching techniques. By patterning by removing by etching, an insulating material is selectively embedded in the removed portion to form an element isolation region 12.

Then, the layer portion 13 corresponding to the gate region except at least the portions corresponding to both the source and drain regions of the base polysilicon layer 11 is selectively and partially etched away and patterned by the same means. Then, the corresponding main surface on the silicon semiconductor substrate 9 is exposed by the gate width, and by extension, the channel length equivalent range, under the restriction of both end dimensions by these remaining source and drain regions.

Further, a thin oxide film is formed by heat-treating the main surface portion of the silicon semiconductor substrate 9 and the surface including the end surface portion of the patterned base polysilicon layer 11 as appropriate to generate a thin oxide film. A thin gate oxide film 10 is formed on the main surface portion of the substrate, and an oxide film 10a is formed on the surface including the end surface portion of the base polysilicon layer 11, and at the same time, this is left. Diffusion of n ⁺ type impurities from the base polysilicon layer 11 forms n ⁺ type source regions and drain regions 8a to 8d in the respective regions, and then the word line 2a and the gate electrode 2b are similarly formed by polysilicon or the like. , 2c are respectively formed.

Therefore, in the case of the configuration of the first embodiment, as described above, by using the MOSFET having the poly source / drain structure in the high resistance load type SRAM memory cell, the conventional n ⁺
The portion determined by the sheet resistance of the type diffusion region is now determined by the resistance of the base polysilicon layer 11, and the resistance value is changed by means such as siliciding the surface of the base polysilicon layer 11. In addition to eliminating the disadvantages such as the asymmetry of the memory cell due to the parasitic resistance and the increase in access time, which are seen in the above-mentioned conventional configuration, the poly source / drain structure can be reduced extremely easily. Is capable of forming a very shallow junction depth in the n ⁺ diffusion region, so that the short channel effect can be reduced and the subthreshold current can also be reduced.
The stability and data retention characteristics of the high resistance load type SRAM memory cell can be improved, and a device with large capacity and low power consumption can be obtained.

Next, the configuration of the second embodiment shown in FIG. 3 to FIG.
In addition to the structure of the first embodiment, the MOSFET in the structure of the conventional example is cross-connected with the polysilicon layer and the diffusion layer.
(Q3, Q4) Of the wirings between the source and gate of 33 and 34, what was the diffusion layer wiring is not used as the diffusion layer wiring, but the base polysilicon layer is used as the wiring.

In this second embodiment as well, the main manufacturing steps up to the formation of the gate electrode will be briefly described. First, for the silicon semiconductor substrate 9 on which the element isolation regions 1 are formed, first, n ^After forming the base polysilicon layer 11 containing ⁺ type impurities, the polysilicon layer 11 of the portion corresponding to the element isolation region 1 and the layer portion 13 corresponding to the gate region 13 is selected by photolithography and etching technique. By partially and partially etching away and patterning the corresponding main surface on the silicon semiconductor substrate 9 under the control of the dimension of both ends by the remaining source and drain regions, the gate width, and eventually the channel. Only a long-corresponding range is exposed, and then, similarly to the previous example, on the main surface portion of these silicon semiconductor substrate 9 and the end surface of the patterned base polysilicon layer 11 A thin oxide film is generated by appropriately heat-treating the surface including the components, and thus a thin gate oxide film having a regulated channel length is formed on the main surface portion of the silicon semiconductor substrate 9. 10 on the surface including the end face portion of the base polysilicon layer 11 and the oxide film 10
a respectively, and at the same time, by diffusion of n ⁺ type impurities from the remaining base polysilicon layer 11,
The n ⁺ type source and drain regions 8a to 8d are formed in the respective regions, and then the word line 2a and the gate electrodes 2b and 2c are similarly formed in the same by using polysilicon or the like.

Therefore, also in the case of the structure of the second embodiment, as in the case of the structure of the first embodiment, the portion which is conventionally determined by the sheet resistance of the n ⁺ type diffusion region is the base polysilicon layer 11. The resistance value of the base polysilicon layer 11 can be extremely easily lowered by siliciding the surface of the base polysilicon layer 11, and asymmetry of the memory cell due to parasitic resistance, increase in access time, etc. In addition, the junction depth in the n ⁺ diffusion region can be made very shallow, the short channel effect is reduced, and the subthreshold current can be reduced.
Area of drain regions 8b, 8c in ET (Q3, Q4) 33, 34,
In addition, the edge length can be shortened and the junction leakage can be reduced. Again, these results can effectively improve the stability and data retention characteristics in the high resistance load type SRAM memory cell.

The configuration of the third embodiment shown in FIGS. 6 and 7 is the same as that of the first embodiment except that the drain region 8
A thin oxide film 12a (corresponding to the element isolation region 12) as thin as the gate oxide film 10 is formed on the surface of the semiconductor substrate 9 in contact with the element isolation region 12 between b and 8c. In addition to obtaining the same operation and effect as in the embodiment, since a capacitance is formed between the base polysilicon layer 11 and the semiconductor substrate 9 which are opposed to each other through the thin oxide film 12a, the capacity of the memory cell is reduced. The node capacity can be increased and the soft error resistance can be improved.

〔The invention's effect〕

As described above in detail, in the first aspect of the present invention, a MOS field effect transistor for storing data information is formed by diffusion of a source formed from a polysilicon layer formed on a semiconductor substrate and defining a channel region. Since it has the drain region and the drain region, a static semiconductor memory device having improved stability and data retention characteristics can be obtained.

Also in the second aspect of the present invention, since the first and second driver transistors have the drain region diffused from the first polysilicon layer, the static type with improved stability and data retention characteristics is provided. A semiconductor memory device can be obtained.

[Brief description of drawings]

FIG. 1 shows a high resistance load type to which the first embodiment of the present invention is applied.
FIG. 2 is a schematic plan view showing a simplified pattern of an SRAM memory cell, FIG. 2 is a cross-sectional view showing an outline of a device structure up to formation of a gate electrode in the II-II line portion of FIG. 1, and FIG. A circuit connection diagram showing a connection state of each element of a high resistance load type SRAM memory cell to which the second embodiment is applied, and FIG. 4 shows a simplified pattern of the high resistance load type SRAM memory cell according to the second embodiment. Plane pattern diagram, FIG.
FIG. 5 is a sectional view showing an outline of a device configuration up to formation of a gate electrode in a VV line portion, and FIG. 6 shows a simplified pattern of a high resistance load type SRAM memory cell to which a third embodiment of the present invention is applied. The plane pattern diagram shown in FIG. 7 is shown in FIG. 6 VII-V.
FIG. 8 is a cross-sectional view showing an outline of a device configuration up to formation of a gate electrode in a II line portion, and FIG. 8 is a circuit connection diagram showing a connection state of each element of a conventional high resistance load type SRAM memory cell, Figure 9 shows a high resistance load type SR according to this conventional example.
FIG. 10 is a plan view showing the AM memory cell pattern. FIG. 10 is a plan view showing a simplified pattern of FIG. 9.
FIG. 11 is a cross-sectional view showing the outline of the device configuration up to the formation of the gate electrode along the line XI-XI in FIG. 1, 12 ... element isolation regions, 2a to 2c ... first polysilicon layer, 4a to 4c ... second polysilicon layer,
6 ... third polysilicon layer, 8a to 8d ... n ⁺ type diffusion regions (source region, drain region), 9 ... p type silicon semiconductor substrate, 10 ... gate oxide film, 11 …… Base polysilicon layer, 12a …… Thin oxide film (element isolation region), 13 …… Gate region corresponding part, 31 to 34 …… MOSFET
(Q1 to Q2), 35, 36 ... High resistance (R1, R2), 37 ... Power supply potential (Vcc), 38 ... Ground potential (GND), 39 ... Bit line (BL), 40 ... bit Lines (BL), 41, 42 ... Memory cell nodes MC, 43 ... Word lines (WL).

Claims (2)

[Claims] 1. A pair of MOS field effect transistors each having a drain region connected to a power source through a load element and having respective gates cross-connected to the other drain regions to store data information. In the static semiconductor memory device having the memory cell, each of the MOS field effect transistors is formed separately from each other on the main surface of the first conductivity type semiconductor substrate so as to define independent channel regions. And a polysilicon layer containing impurities of the second conductivity type formed on the main surface of the semiconductor substrate below the polysilicon layer by impurity diffusion from the polysilicon layer. A source region and a drain region defined by, and a channel located between the source region and the drain region of the semiconductor substrate A gate electrode formed on the region and on the polysilicon layer via a gate insulating film, and provided on the semiconductor substrate main surface between the polysilicon layers of the pair of MOS field effect transistors; A static semiconductor memory device comprising an element isolation region having a thickness substantially the same as that of the polysilicon layer. 2. A first conductivity type semiconductor substrate having a main surface, a second conductivity type source region formed on the main surface of the semiconductor substrate, and first polysilicon containing impurities of the second conductivity type. Contacting a first polysilicon line formed from a layer,
On the drain region of the second conductivity type formed on the main surface of the semiconductor substrate by impurity diffusion from the first polysilicon wiring, and on the channel region of the main surface of the semiconductor substrate sandwiched by the source and drain regions. A first driver transistor having a gate electrode formed of a first conductive layer via a gate insulating film, a second conductive type source region formed on a main surface of the semiconductor substrate, and the first driver transistor. The first polysilicon layer is formed on the main surface of the semiconductor substrate by being separated from the polysilicon wiring and in contact with a polysilicon member formed of the first polysilicon layer and diffusing impurities from the polysilicon member. Second conductive layer connected to the gate electrode of the first driver transistor by a second polysilicon wiring formed from a second polysilicon layer above Type drain region and the channel region of the main surface of the semiconductor substrate sandwiched by the source and drain regions, the first conductive layer being formed via the gate insulating film, and the first polysilicon wiring being formed. A second driver transistor having a gate electrode connected thereto; a first driver transistor connected between a drain region of the first driver transistor and a predetermined potential wiring to which a predetermined potential is applied.
And a second load element connected between the drain region of the second driver transistor and the predetermined potential wiring.