JPH1084047A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance flatness, high integration and acceleration by a method wherein a transistor is formed of the first electrode, the first and second impurity diffused regions while another transistor is formed of the second and fourth electrodes, the first and second semiconductor layers furthermore, the semiconductor region is formed into a channel region of the latter transistor. SOLUTION: A substrate MOSFET 30 is composed of a gate electrode 4, impurity diffused regions 5a, 5b. Next, the impurity diffused region 5b is connected to a semiconductor film 13b as a bit line so as to compose a TFT of a wiring 15 as an upper gate electrode, a plug 11 as a lower gate electrode and source.drain electrodes 18a, 18b. Next, the impurity diffused region 5a is electrically connected to the plug 11 so as to connect the wiring 15 to the gate electrode 4 as a word line. Finally, the gate electrode 4 is impressed with a voltage exceeding a threshold value to turn the MOSFET 30 on while another wiring 16 is impressed with a positive charge so as to supply a current from the impurity diffused layer 5b to 5a for the accumulation of the charge as the plug 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor memory device and a method of manufacturing the same.

[0002]

2. Description of the Related Art As semiconductor devices become more highly integrated and consume less power, write and read margins for noise of dynamic random access memories (hereinafter referred to as DRAMs) are becoming smaller. In other words, the miniaturization of the pattern makes it difficult to make the capacitance of the capacitor that holds the charge as information sufficiently large relative to the parasitic capacitance of the wiring. As a result, the amount of charge stored in the capacitor is not sufficient, and there is a problem that the voltage at the time of reading is buried in the noise of the wiring.
To solve such a problem, a gain cell in which the capacitor is replaced with a transistor (hereinafter referred to as TFT) has been proposed.

Therefore, as one example, Japanese Patent Application Laid-Open No. 7-176
The semiconductor device disclosed in Japanese Patent No. 184 will be described.

FIG. 37 is a block diagram of a semiconductor device disclosed in the above publication, and FIG. 38 shows a cross section of the semiconductor device. Referring to FIG. 37, each memory cell MC has a storage node SN, storage SN holding high potential VH or low potential VL representing a binary signal.
And a read transistor Q2 for reading potential VH or VL of storage SN. The gate of write transistor Q1 of each memory cell MC is connected to write word line WL1 or WL2 of the memory cell row, the source is connected to write bit line BL1 or BL2 of the memory cell column, and the drain is Storage node S
N. The gate of read transistor Q2 of each memory cell MC is connected to storage node S2, its drain is grounded, its source is connected to read bit line BL1 'or BL2' of that memory cell column, and its back gate is It is connected to read word line WL1 'or WL2' of that memory cell row. Also,
One ends of read bit lines BL1 'and BL2' are connected to sense amplifiers S / A1 and S / A2, respectively.
1 'and BL2' are connected to transistors QB1 and QB2, respectively.
Is connected to the precharge line PCL.

[0005] Next, referring to FIG.
01 on the active region partitioned by the silicon oxide film 110, the gate electrode 102 (write word line WL) and the source region 1
01a and a drain transistor 101b having a drain region 101b are formed. Write bit line BL is connected to source region 101a. Drain region 101
b is connected to the storage node SN. The upper end of the storage node SN protrudes from the interlayer insulating film 111. A silicon insulating film 105 such as a thermal oxide film is interposed on the surface of the protruding storage node SN to form a silicon thin film 1.
06 is formed. A back gate 107 made of silicon is formed on the silicon thin film 106 with a thin insulating film 108 such as a thermal oxide film interposed therebetween. Silicon thin film 1
In 06, a source region 106a and a drain region 106b are formed by an ion implantation method. The silicon thin film 106 becomes a channel region of the read transistor Q2. The storage node SN also functions as the gate electrode of the read transistor Q2.

Next, the operation will be briefly described. FIG.
, Gate electrode 102 of write transistor Q1
When a predetermined voltage is applied to the bit line BL and a positive charge is applied to the bit line BL, a current flows from the source region 101a to the drain region 101b, and the positive charge is accumulated in the storage node SN. At this time, the upper portion of storage node SN applies an electric field to the channel region of read transistor Q2. If the read transistor Q2 is a PMOS transistor, a negative potential needs to be applied to the gate electrode in order to allow a current to flow between the source region 106a and the drain region 106b of the read transistor Q2. At this time, when a positive charge is accumulated in the storage node SN, a positive charge is applied to the channel region from the storage node SN side, so that a negative voltage having an absolute value larger than that for canceling this electric field is applied. It is necessary to. That is, the threshold voltage of read transistor Q2 when no positive charge is stored in storage node SN is V _0, and the threshold voltage when positive charge is stored in storage node SN is V ₁ Then, 0> V ₀ > V ₁ holds.

Here, when a voltage V that satisfies the relationship of V ₀ >V> V ₁ is applied to the gate electrode of the read transistor Q2, if a positive charge is stored in the storage node SN, 0>V> V _Since there is a relation of _1, no current flows between the source region and the drain region. On the other hand, if no positive charge is stored in the storage node SN, 0
> V ₀ > V, a current flows between the source region and the drain region. In this manner, the voltage V is applied to the gate voltage of the read transistor Q2, and it is possible to determine whether or not the charge is accumulated in the storage node SN based on the current between the source region and the drain region.

In the cited reference, write word lines WL1 and WL2 and read word lines WL1 ',
WL2 'and the write bit lines BL1 and BL2 and the read bit lines BL1' and BL1.
2 'and FIG.
0, each is disclosed. These are all intended to achieve high integration of the semiconductor device by sharing the word lines and the bit lines.

Next, as another example of the prior art, a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 7-99251 will be described.

FIG. 41 is a diagram showing the principle of a semiconductor device disclosed in the same publication, and FIG. 42 is a schematic sectional view of the semiconductor device. Referring to FIG. 41, this semiconductor device includes an information storage transistor TR1 and a switching transistor TR2. Information storage transistor T
R1 is formed of, for example, a p-type transistor, and switching transistor TR2 is formed of an n-type transistor. Referring to FIG. 41 and FIG. 42, the information storage transistor TR ₁ includes a semiconductor channel layer Ch ₁ , a first conductive gate G ₁ and a second conductive gate G _2, and both ends of the semiconductor channel layer Ch ₁ . The _first and second conductive layers L ₁ and L ₂ are connected. The switching transistor TR ₂ includes a semiconductor channel formation region Ch ₂ and a third transistor
The conductive gate G _3, third contact to form and rectifying junction formed in a surface region of the semiconductor channel forming region Ch ₂
Consisting of the conductive layer L ₃ and the fourth conductive layer L ₄ Prefecture. Semiconductor channel layer Ch ₁ has two main surfaces MS _1, MS ₂ to the first and second opposed. First conductive gate G ₁
Through the first barrier layer BL _1, is provided opposite to the main surface MH ₁ of the semiconductor channel layer. The second conductive gate G ₂ is, via the second barrier layer BL _2, is provided opposite to the main surface MS ₂ of the semiconductor channel layer. The semiconductor channel formation region Ch ₂ has a third main surface MS
_{With 3} . A third conductive gate G ₃ are, through the third barrier layer BL _3, the third semiconductor channel forming region Ch ₂
It is provided opposite to the main surface MS _3. The fourth conductive layer L ₄ are, is connected to the second conductive gate G _2. First
Conductive gate G ₁ and the third conductive gate G ₃ is connected to the first wiring in the memory cell selected (word line). The first conductive layer L ₁ and the third conductive layer L ₃ is connected to the second wiring for memory cell selection (bit line). The second conductive layer L ₂ is connected to a predetermined potential including zero potential. Semiconductor channel forming region Ch ₂ is connected to the write / read selection lines.

Next, the operation will be briefly described. If the second conductive gate G ₂ to the charges are not accumulated, in order to flow a current between the first conductive layer of the p-type of the information storage transistor TR ₁ L ₁ and the second conductive layer L _{2 May} be applied by applying a predetermined threshold voltage V _th to the second conductive gate G ₂ . In the case where charge is stored in the _second conductive gate G2, a negative voltage having an absolute value larger than the threshold voltage _Vth may be applied. That is, the information storage transistor T
By utilizing a change in the threshold voltage of the R _1, it is possible to determine the presence or absence of accumulation of the charges as information of the second to the conductive gate G _2.

[0012] In this reference example, also serves as the first conductive gate G ₁ and a third gate electrode conductive gate G ₃ and the switching transistor TR ₂ is a readout gate electrode of the information storing transistor TR ₁ can do.
Further, it is possible to the fifth conductive layer L ₅ which is a first conductive layer L ₁ and the bit line switching transistor TR ₂ is a bit line of the information storage transistor TR ₁ in common.

[0013]

However, the above-described conventional semiconductor device and the method of manufacturing the same have the following problems.

First, in Japanese Unexamined Patent Publication No. 7-176184, as shown in FIG. 38, the upper portion of the storage node SN for storing electric charge as information protrudes from the interlayer insulating film 111. Therefore, the storage node SN
When the silicon thin film 106 is formed on the interlayer insulating film 111 including the silicon nitride layer 106, when the silicon thin film 106 is patterned, there is a problem that the patterning is not properly performed in the vicinity of the protrusion of the storage node SN.

The wiring of the gate electrode 107 of the read transistor Q2, the source region 106a and the drain region 1
In addition, it was necessary to separately form a wiring to be connected to the H.06b. Therefore, the wiring structure becomes complicated, and it is disadvantageous to achieve high integration of the semiconductor device.

There is no specific description on the method of forming the semiconductor device shown in FIGS. Therefore, when a semiconductor film for forming the channel region 106, the source region 106a, and the drain region 106b of the read transistor Q2 is used as a bit line, the wiring resistance of the bit line is high and the speed of the semiconductor device is increased. Can be difficult.

Next, in Japanese Patent Application Laid-Open No. 7-99251, as shown in FIG.
A second conductive gate G ₂ of R ₁ extends in the gate length direction (parallel to the page). In Therefore, to form the information storing transistor TR _1, the information storage transistor T
Mask for forming the mask and the second conductive gate G ₂ to form a channel region Ch ₁ of R ₁ is required, which is disadvantageous to reduce the manufacturing cost.

Further, the flatness of the semiconductor device is not good,
In the formation of wiring and the like, there has been a problem that patterning is not performed accurately.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor device which is excellent in flatness and can achieve high integration and high speed, and a method of manufacturing the same. .

[0020]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: first and second impurity diffusion regions of a second conductivity type; a first electrode; a second insulating film; The semiconductor device includes a third electrode, a second conductivity type semiconductor region, a fourth electrode, a first conductivity type first semiconductor layer, and a first conductivity type second semiconductor layer. The first and second impurity diffusion regions of the second conductivity type are formed at predetermined intervals on the main surface of the semiconductor substrate of the first conductivity type. The first electrode is formed on a region sandwiched between the first and second impurity diffusion regions with a first insulating film interposed. The second insulating film is formed on the main surface so as to bury the first electrode. The second and third electrodes are formed so as to fill the openings formed in the second insulating film exposing the surfaces of the first and second impurity diffusion regions, respectively. The semiconductor region of the second conductivity type is formed on the second electrode with a third insulating film interposed. The fourth electrode is electrically connected to the first electrode, and is formed on the semiconductor region with a fourth insulating film interposed. The first and second semiconductor layers of the first conductivity type are formed on the second insulating film, respectively, and are provided so as to sandwich the semiconductor region. The second semiconductor layer is a third semiconductor layer.
It is electrically connected to the electrodes.

According to the above configuration, the first electrode and the first and second impurity diffusion regions form one transistor, and the second and fourth electrodes and the first and second semiconductor layers form the other transistor. I have. The semiconductor region forms a channel region of the other transistor. By applying a voltage higher than the threshold value to the first electrode, one of the transistors
Then, electric charge as information is accumulated in the second electrode. In the other transistor, the threshold voltage of the fourth electrode for turning on the transistor changes depending on the presence / absence of charge accumulation in the second electrode. The presence or absence of charge, that is, information can be read by the change in the threshold voltage. The second electrode is formed so as to fill an opening provided in the second insulating film. Therefore, the surface of the second insulating film including the upper surface of the second electrode is almost flat, and thereafter, the semiconductor region formed above the second electrode and the fourth electrode can be accurately patterned. as a result,
High integration of the semiconductor device can be achieved.

Preferably, a metal silicide layer formed on each of the first and second semiconductor layers is further provided. In that case, the electrical resistance of the first and second semiconductor layers decreases,
As a result, the speed of the semiconductor device can be increased.

In a semiconductor device according to a second aspect of the present invention, the first and second impurity diffusion regions of the second conductivity type, the first electrode, the second and third electrodes, the second insulating film, 4
An electrode and a fifth electrode, a semiconductor region of the second conductivity type, a third insulating film, third and fourth impurity diffusion regions of the first conductivity type, a fourth insulating film, a first wiring layer, And two wiring layers. The first and second impurity diffusion regions of the second conductivity type are formed at predetermined intervals on a semiconductor substrate of the first conductivity type. The first electrode is formed on a region sandwiched between the first and second impurity diffusion regions with a first insulating film interposed. The second and third electrodes are electrically connected to the first and second impurity diffusion regions, respectively. The second insulating film is formed on the main surface so as to embed the first to third electrodes. The fourth electrode is formed on the second insulating film and is electrically connected to the first electrode. The fifth electrode is formed on the second insulating film and is electrically connected to the third electrode. The semiconductor region of the second conductivity type is sandwiched between the fourth electrode and the fifth electrode. The third insulating film is sandwiched between the fourth electrode and the semiconductor region and between the fifth electrode and the semiconductor region. Third and fourth of the first conductivity type
The impurity diffusion region sandwiches the semiconductor region from a direction substantially orthogonal to a direction from the fourth electrode to the fifth electrode. The fourth insulating film is formed on the second insulating film, and buries the semiconductor region, the fourth electrode, the fifth electrode, the third and the fourth impurity diffusion regions. The first wiring layer is formed on the fourth insulating film and is electrically connected to the third impurity diffusion region. The second wiring layer is formed on the fourth insulating film, and is electrically connected to the fourth impurity diffusion region and the third electrode.

According to the above configuration, the first electrode, the first and second impurity diffusion regions form one transistor, and the fourth and fifth electrodes and the third and fourth impurity diffusion regions form the other transistor. . One transistor is turned on by applying a voltage higher than the threshold value to the first electrode.
Then, charge as information is accumulated in the third electrode. In the other transistor, the threshold voltage of the fourth electrode for turning on the transistor changes depending on the presence or absence of charge accumulation on the third electrode. By the change in the threshold voltage, the presence or absence of charge, that is, information can be read.

The other transistor is embedded in a fourth insulating film, and furthermore, a fourth electrode and a fifth electrode sandwich a semiconductor region as a channel region of the transistor from one direction parallel to the main surface. The third impurity diffusion region and the fourth impurity region are sandwiched from a direction substantially orthogonal to the direction. Therefore, the surface of the fourth insulating film including the other transistor formation region becomes substantially flat. This allows
The patterning of the first and second wiring layers formed thereafter can be accurately performed. As a result, high integration of the semiconductor device can be achieved.

The method for manufacturing a semiconductor device according to the third aspect of the present invention includes the following steps. A first conductive type semiconductor substrate is separated from a main surface of a first conductive type semiconductor substrate by a predetermined distance.
And forming a second impurity diffusion region. The first surface is formed on the main surface between the first and second impurity diffusion regions.
A first electrode is formed with an insulating film interposed. A second insulating film is formed on the main surface so as to fill the first electrode. First and second openings are formed in the second insulating film so as to expose the surfaces of the first and second impurity diffusion regions, respectively. Second and third electrodes are formed to fill the first and second openings, respectively. The surface of the second insulating film and the second and third
Substantially aligned with the top surface of the electrode. A third insulating film is formed on the second insulating film including the upper surfaces of the second and third electrodes. Second
A first and second semiconductor layers of the second conductivity type connected to each other are formed on the third insulating film above the electrodes. The third electrode and the second semiconductor layer are electrically connected. On the semiconductor layer sandwiched between the first and second semiconductor layers, a fourth electrode electrically connected to the first electrode is formed with a fourth insulating film interposed. Using the fourth electrode as a mask, a first conductivity type impurity is introduced into the first and second semiconductor layers to form third and fourth impurity diffusion regions, respectively.

According to the above manufacturing method, the second and third
Since the electrodes are embedded in the second insulating film, the surface of the second insulating film becomes substantially flat. Therefore, patterning of the fourth electrode and the first and second semiconductor layers formed on the second insulating film thereafter can be accurately performed. as a result,
High integration of the semiconductor device can be achieved.

Further, since the third and fourth impurity diffusion regions are formed using the fourth electrode as a mask, a mask for forming only the third and fourth impurity diffusion regions is not required, and the production cost is reduced. be able to.

A method of manufacturing a semiconductor device according to a fourth aspect of the present invention includes the following steps. First and second impurity diffusion regions of the second conductivity type are formed on the main surface of the semiconductor substrate of the first conductivity type at predetermined intervals. A first electrode is formed on a region of the main surface between the first and second impurity diffusion regions with a first insulating film interposed. A second insulating film is formed on the main surface so as to fill the first electrode. First and second openings are formed in the second insulating film so as to expose the surfaces of the first and second impurity diffusion regions, respectively. The second and third electrodes are formed so as to fill the first and second openings, respectively. The surface of the second insulating film and the upper surfaces of the first to third electrodes are substantially aligned. A third insulating film is formed on the second insulating film including the upper surfaces of the first to third electrodes. For the third insulating film,
A third opening is formed to expose the surfaces of the first and third electrodes, respectively. In the third opening, a fourth electrode electrically connected to the first electrode, a fifth electrode electrically connected to the third electrode, and a fourth electrode between the fourth and fifth electrodes. A semiconductor region of the second conductivity type with the fourth insulating film interposed therebetween, and third and fourth impurity diffusion regions of the first conductivity type facing each other in a direction substantially orthogonal to the direction from the fourth electrode to the fifth electrode. To form A third insulating film is formed on the third insulating film.
A first wiring layer electrically connected to the impurity diffusion region is formed. On the third insulating film, a second wiring layer electrically connected to the third electrode and electrically connected to the fourth impurity diffusion region is formed.

According to the above configuration, the fourth and fifth electrodes, the semiconductor region of the second conductivity type, and the third and fourth impurity diffusion regions are buried in the third insulating film. It becomes almost flat. Therefore, patterning of the first and second wiring layers formed on the third insulating film thereafter is performed with high accuracy, and high integration of the semiconductor device can be facilitated.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) A method of manufacturing a semiconductor device according to Embodiment 1 of the present invention and the operation of the semiconductor device obtained by the method will be described with reference to the drawings.

First, referring to FIG.
A silicon oxide film 2 as an element isolation insulating film is formed by the COS method. When the LOCOS method is used, the thickness of the silicon oxide film is 200 to 500 nm.

Next, referring to FIG. 2, a silicon oxide film 3 as a gate insulating film is formed to a thickness of 5 to 10 nm by a CVD method. Thereafter, a silicon film or a metal silicide film as a conductive film is formed to a thickness of 200 nm, and photolithography and etching are performed to form a gate electrode 4 as a first electrode according to the first or third aspect of the present invention. next,
By ion implantation, BF ₂ is set to 5 to 30 KeV, 1 × 1
Implantation is performed at a rate of 0 ¹³ to 1 × 10 ¹⁶ / cm ² to form impurity diffusion regions 5a and 5b. Thereby, the substrate MOSFET
Is formed.

Next, referring to FIG. 3, a 400 nm-thick silicon oxide film 6 is formed by the CVD method. Then, the first 0.5 μm-size first silicon oxide film 6 is exposed to the surface of the impurity diffusion region 5a by photolithography and etching.
The connection hole 7 is opened.

Next, referring to FIG. 4, a silicon film or a metal silicide film is formed so as to be buried in first connection hole 7 by a CVD method, and the first connection hole 7 is formed by an etch back or polishing method.
The silicon film or the metal silicide film is left only in the connection hole 7, and the plug 11 as the second electrode according to the first or third aspect of the present invention is formed.

Next, referring to FIG. 5, a silicon oxide film 12 as a lower gate insulating film is
nm. After that, the silicon film is
The semiconductor film 13 as the first and second semiconductor layers in the third aspect of the present invention is formed by forming a film having a thickness of 0 to 100 nm and performing photolithography and etching. As the semiconductor film, silicon germanium may be used instead of the silicon film. FIG.
FIG. 4 is a diagram showing a plane of the semiconductor device in this step. FIG. 5 shows a cross section taken along the line AA shown in FIG.

Referring to FIG. 6, semiconductor film 13 includes two wiring portions 13a extending in a direction intersecting gate electrode 4.
13b and a region sandwiched between the two wiring portions 13a and 13b. That area is the first of the present invention.
Region 13c as a semiconductor region in the aspect of FIG.
Becomes

Next, referring to FIG. 7, the thermal oxidation method or C
A silicon oxide film 14 as an upper gate insulating film is formed to a thickness of 5 to 10 nm by the VD method.

Thereafter, referring to FIG. 8, a contact hole 20 exposing the surface of gate electrode 4 is formed by photolithography and etching. The size of this connection hole 20 is, for example, 0.4 μm. Further referring to FIG.
At the same time, the connection hole 22 exposing the surface of the impurity diffusion region 5b is also opened. FIG. 9 is a diagram showing a cross section taken along line BB shown in FIG.

Next, referring to FIG. 10 and FIG. 11, a silicon film or a metal silicide film
After the formation by the VD method, the wirings 15 and 16 are formed by photolithography and etch back. FIG. 12 is a diagram showing a plane of the semiconductor device in this step. Further FIG.
FIG. 3 is a diagram showing a cross section taken along line CC shown in FIG. The wiring 15 located above the channel region 13c forms a gate electrode of a TFT to be formed later as a fourth electrode according to the first or third aspect of the present invention. Further, the wiring 16 located above the impurity diffusion region 5b forms a third electrode according to the first or third aspect of the present invention.

Next, referring to FIG. 14, for example, BF ₂ is implanted by ion implantation at an energy of 5 to 20 KeV and a dose of 1 × 10 ^{14 to} 5 × 10 ¹⁵ / cm ^{2 using} wiring 15 as a mask. Then, the first and second semiconductor layers according to the first aspect of the present invention, or the source / drain regions 18a and 18b as third and fourth impurity diffusion regions according to the third aspect are formed. Thereby, a TFT is formed.

Next, referring to FIG. 15, a silicon oxide film 22 is formed to a thickness of 100 to 200 nm by the CVD method.

Thereafter, referring to FIG. 16, dry etching is performed on the silicon oxide film to form sidewalls 24 near the steps of wiring 15 and the steps of source / drain regions 18a and 18b.

Next, referring to FIG. 17, titanium 26 serving as a metal film is deposited by sputtering or CVD.
It is formed to a thickness of 50 nm. As the metal film, cobalt or nickel may be used in addition to titanium.

Next, referring to FIG.
A heat treatment is performed at 00 ° C. for 1 minute, and the wiring 15 made of a silicon film and titanium are replaced with a source material made of silicon.
The drain regions 18a and 18b are reacted with titanium to form titanium silicide 28. Thereafter, unreacted titanium is removed with, for example, a mixed solution of sulfuric acid and hydrogen peroxide solution. FIG. 19 is a diagram showing a plane of the semiconductor device in this step. The hatching of each member shown in FIG. 19 is the same as the hatching of each member shown in FIG. Through the above steps, a basic structure of the semiconductor device is obtained.

The above-described semiconductor device manufacturing method has the following advantages. First, in the step shown in FIG. 4, since the upper surface of plug 11 is formed so as to substantially coincide with the surface of silicon oxide film 6, semiconductor film 13 formed in the step shown in FIG. The wiring 15 formed in the step shown in FIG. 10 can be patterned with high accuracy.

Further, using the wiring 15 as a mask,
Since the drain regions 18a and 18b are formed in a self-aligned manner, a mask for forming only the source / drain regions is not required, and the manufacturing cost can be reduced.

Next, the semiconductor films 13a and 13b made of silicon and the wiring 15 made of silicon or metal silicide shown in FIG. 13 are formed on the gate electrode 15a and both side walls of the gate electrode 15a in the step shown in FIG. Source / drain region 18 under the formed sidewall 24
The metal silicide 28 is changed leaving a and 18b.
Therefore, the electric resistance of the wiring can be reduced, and the speed of the semiconductor device can be increased.

The metal silicide 28 is electrically connected to the impurity diffusion region 5b via the wiring 16 shown in FIG. Therefore, this metal silicide 28
It also serves as the bit line of the OSFET. The word line of the substrate MOSFET is constituted by the gate electrode 4. These make it possible to form a semiconductor device having a simpler structure and low-resistance wiring.

Next, the operation of the semiconductor device obtained by the above-described manufacturing method will be described. FIG. 20 illustrates an example of a circuit of a semiconductor device. Referring to FIG. 20, gate electrode 4 and impurity diffusion regions 5a and 5b are connected to substrate MOSFET 3
0 is configured. The impurity diffusion region 5b is connected to the semiconductor film 13b as a bit line. Gate electrode 4
Form a word line. A wiring 15 as an upper gate electrode,
The TFT is composed of the plug 11 as the lower gate electrode and the source / drain regions 18a and 18b. Impurity diffusion region 5a is electrically connected to plug 11. The wiring 15 is electrically connected to the gate electrode 4 as a word line.

Positive charges as information are accumulated in the plug 11 by the switching action of the MOSFET 30.
T when positive charge is accumulated in plug 11
The relationship between the voltage of the gate electrode 15a of the FT and the drain current is represented by a curve Y shown in FIG. When no positive charge is stored in the plug 11, the relationship is a curve X.

Referring to FIG. 21, when voltage V1 is applied to gate electrode 15a, a drain current corresponding to the intersection of curve X and dotted line V1 flows when no charge is accumulated in plug 11. On the other hand, when no electric charge is accumulated in the plug 11, there is no intersection between the curve Y and the dotted line V1, and no drain current flows. This is an information reading operation, and it is determined whether or not charge is accumulated in the plug 11.

In order to store charge in the plug 11 as an information writing operation, a voltage higher than a threshold value is applied to the gate electrode 4 to turn on the MOSFET. next,
By applying a positive charge to the wiring 16, a current flows from the impurity diffusion layer 5b connected to the wiring 16 to the impurity diffusion layer 5a, and the plug 1 connected to the impurity diffusion layer 5a
The electric charge as information is stored in 1.

(Embodiment 2) In the manufacturing method described in Embodiment 1, a gate electrode is formed on a channel region made of a semiconductor film of a TFT. Therefore, it is necessary to pattern the gate electrode at the step portion of the channel region. Etching at the step portion may result in an etching residual film, which may make it difficult to perform accurate patterning. Thus, an example of a method for solving this will be described with reference to the drawings.

Referring to FIG. 22, in the step shown in FIG. 3, in addition to the first connection hole 7, the second connection hole 10 exposing the surface of the impurity diffusion region 5b is simultaneously opened. A silicon film as a conductive film is formed by a CVD method so as to fill the two connection holes 7 and 10. The conductive film may be a metal silicide film other than the silicon film. Thereafter, the entire surface is etched back to leave the silicon film only in the first and second connection holes 7 and 10, and the first burying as the second or third electrode in the second and fourth aspects of the present invention. The electrode 34 and the second embedded electrode 36 are formed respectively.

Next, referring to FIG. 23, a silicon oxide film 38 is formed to a thickness of 500 nm by the CVD method. Next, photolithography and etching are performed on the silicon oxide film 38 to form a third connection hole 40 exposing the surfaces of the gate electrode 4 and the second buried electrode 36. FIG. 24 is a diagram showing a plane in this step.

Next, referring to FIG. 25, a silicon film as a conductive film is formed by CVD so as to fill the third connection hole. As the conductive film, a metal silicide film may be used instead of the silicon film. Thereafter, the silicon film on the silicon oxide film 38 is removed by an etch-back method or a polishing method, so that the silicon film is left only in the third connection hole 40, and the third buried electrode 42 is formed.

Next, referring to FIG. 26, photolithography and etching are performed on the third buried electrode, and gate electrode 4 and second buried electrode are formed.
An opening 44 exposing a part of the surface of the embedded electrode 36 is formed. FIG. 27 is a diagram showing a plane in this step.
Referring to FIG. 27, width L1 of opening 44 is, for example, 8
0 to 150 nm. The opening 44 divides the third buried electrode into two separated portions, and the first side gate electrode 46 as the fifth electrode according to the second or fourth aspect of the present invention, and the fourth electrode And the second side gate electrode 47 is formed. First side gate electrode 46
Are electrically connected to the second embedded electrode 36. The second side gate electrode 47 is electrically connected to the gate electrode 4. The distance L2 between one end of the opening 44 and the first and second side gate electrodes 46 and 47 is, for example, 250
nm and larger than the width L1.

Next, referring to FIG. 28, after forming a silicon oxide film 48 as a gate insulating film to a thickness of 10 nm, a silicon film 49 as a semiconductor film is formed by a CVD method so as to fill the opening. As the semiconductor film, germanium or a silicon germanium alloy may be used in addition to the silicon film.

Next, referring to FIG.
Etch back all over the silicon film 4
Leave 9 FIG. 30 is a diagram showing a plane in this step. Referring to FIG. 30, L1 and L2 shown in FIG.
<L2, the first side gate electrode 4
Except for the silicon 49 a sandwiched between 6 and the second side gate electrode 47, there is an opening 45 that is not completely buried with silicon and is surrounded by silicon 49. Silicon 4
9a forms a semiconductor region in the second or fourth aspect of the present invention. Next, referring to FIG. 31, fourth connection hole 41 having a size of, for example, 0.4 μm, so as to expose the surface of first embedded electrode 34 by photolithography and etching.
To form Thereafter, phosphorus-doped silicon as a conductive film is formed to a thickness of 0.2 μm by a CVD method. As the conductive film, phosphorus-doped metal silicide may be used instead of phosphorus-doped silicon. Photolithography and etching are performed on the phosphorus-doped silicon to form wirings 50 and 51 as first and second wiring layers according to the second and fourth aspects of the present invention. FIG. 32 is a diagram showing a plane in this step. FIG. 31 shows a cross section taken along the line AA shown in FIG. Referring to FIG. 32, a wiring 50 forms a bit line, and a wiring 51 forms a ground line. Then, heat treatment is performed to diffuse phosphorus contained in the wirings 50 and 51 into silicon other than the silicon 49a. As a result, the regions where phosphorus is diffused into silicon become the source / drain regions 49b and 49c as the third and fourth impurity regions in the second or fourth aspect of the present invention.

Thus, the second side gate electrode 47 electrically connected to the gate electrode 4, silicon 49a as a channel region, and the first side gate electrode electrically connected to the impurity diffusion region 5b. Thus, a TFT having the TFT 46 is formed. The second side gate electrode 47, silicon 49
a, the first side gate electrodes 46 are arranged in order in a direction substantially transverse to the semiconductor substrate surface.

In the semiconductor device formed as described above, as shown in FIG.
The gate electrode 4 of the SFET and the second side gate electrode 47 of the TFT are electrically connected. Since the gate electrode 4 forms a word line, the word line of the substrate MOSFET and the word line of the TFT can be used. Furthermore, the substrate MOSFE
The T impurity diffusion region 5a and the source / drain region 49b of the TFT are electrically connected via a wiring 50. The wiring 50 is formed of a substrate MOS to form a bit line.
The bit line of the FET and the TFT can be shared. Thus, the wiring structure is simplified, and the semiconductor device can be easily formed.

Further, since the channel region and the gate electrode of the TFT are formed in the opening of the interlayer insulating film so as to be arranged in a lateral direction substantially in parallel with the surface of the semiconductor substrate, a step is formed on the upper surface of the TFT. Does not occur. As a result, miniaturization of the semiconductor device can be easily achieved.

(Embodiment 3) With the miniaturization of a semiconductor device, the opening 45 may be completely buried by the silicon 49 in the process shown in FIG. In that case, the source / drain region of the TFT cannot be formed. Therefore, an example of a method for solving this problem will be described with reference to the drawings.

First, the opening 45 formed in the step shown in FIG. 30 is filled with silicon 49 as shown in FIG. 33 in the case of the present embodiment.

Next, referring to FIG. 34, a resist film 52 is formed in a predetermined region. Thereafter, referring to FIG.
Silicon is anisotropically etched using the resist film 52 as a mask to form an opening 53. After that, the resist film 5
Remove 2. Unetched silicon becomes silicon 49a as a channel region.

Thereafter, referring to FIG. 36, after forming a semiconductor film of a conductivity type opposite to the conductivity type of silicon 49a as a channel region, wirings 50 and 51 are formed by photolithography and etching. The wirings 50 and 51 in the portions buried in the openings 53 shown in FIG. 35 form source / drain regions.

After that, the surfaces of the wirings 50 and 51 may be converted to metal silicide by the salicide method as described in the first embodiment.

The wirings 50 and 51 are made of metal silicide having an impurity of a conductivity type opposite to the conductivity type of the silicon 49a, and are diffused into the silicon 49a near the interface between the opening 53 and the silicon 49a. A region may be formed.

In the first, second and third embodiments, a PMOS transistor is used as the substrate MOSFET, and
Although the case where the NMOS transistors are formed as the FTs has been described, the same effects can be obtained even if the conductivity types are switched. In this case, one of the transistors is N
If it is a MOS, the other transistor must be a PMOS.

The embodiment disclosed this time is merely an example, and it is intended that various embodiments can be taken within an equivalent scope of the invention described in the claims.

[0072]

According to the semiconductor device of the first aspect of the present invention, the first electrode and the first and second impurity diffusion regions form one transistor, and the second and fourth electrodes and the first electrode have the same structure.
And the second semiconductor layer forms the other transistor. The semiconductor region forms a channel region of the other transistor. When a voltage equal to or higher than the threshold is applied to the first electrode, one of the transistors is turned on, and electric charge as information is stored in the second electrode. In the other transistor, the threshold voltage of the fourth electrode for turning on the transistor changes depending on the presence / absence of charge accumulation in the second electrode. Information can be read from the change in the threshold voltage. The second electrode is formed so as to fill an opening provided in the second insulating film. Therefore, the second
The surface of the second insulating film including the upper surface of the electrode becomes almost flat, and then the semiconductor region formed above the second electrode and the fourth
Electrode patterning can be performed with high accuracy. As a result, high integration of the semiconductor device can be achieved.

Preferably, the semiconductor device further includes a metal silicide layer formed on each of the first and second semiconductor layers. In that case, the electrical resistance of the first and second semiconductor layers decreases,
As a result, the speed of the semiconductor device can be increased.

According to the semiconductor device of the second aspect of the present invention, the first electrode, the first and second impurity diffusion regions form one transistor, and the fourth and fifth electrodes are connected to the third and fourth impurity diffusion regions. The region forms the other transistor.
By applying a voltage higher than the threshold value to the first electrode,
One of the transistors is turned on, and charges as information are stored in the third electrode. In the other transistor, the threshold voltage of the fourth electrode for turning on the transistor changes depending on the presence or absence of charge accumulation on the third electrode. Information can be read from the change in the threshold voltage.

The other transistor is embedded in the fourth insulating film, and the fourth and fifth electrodes sandwich the semiconductor region as the channel region of the transistor from one direction parallel to the main surface. The third impurity diffusion region and the fourth impurity region are sandwiched from a direction substantially orthogonal to the direction. Therefore, the surface of the fourth insulating film including the other transistor formation region becomes substantially flat. This allows
Patterning of the first and second wiring layers formed thereafter can be performed with high accuracy, and high integration of the semiconductor device can be achieved.

According to the method of manufacturing a semiconductor device according to the third aspect of the present invention, since the second and third electrodes are embedded in the second insulating film, the surface of the second insulating film becomes substantially flat. Therefore, patterning of the fourth electrode and the first and second semiconductor layers formed on the second insulating film thereafter can be accurately performed. As a result, high integration of the semiconductor device can be achieved. Further, since the third and fourth impurity diffusion layers are formed in a self-aligned manner using the fourth electrode as a mask, a mask for forming only the third and fourth impurity diffusion regions is not required, and the manufacturing cost can be reduced. Can be planned.

According to the method of manufacturing a semiconductor device according to the fourth aspect of the present invention, the fourth and fifth electrodes, the semiconductor region of the second conductivity type, and the third and fourth impurity diffusion regions are embedded in the third insulating film. Therefore, the surface of the third insulating film becomes substantially flat. Therefore, after the first insulating film is formed on the third insulating film,
And the patterning of the second wiring layer is accurately performed,
High integration of the semiconductor device can be achieved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a step performed after the step shown in FIG. 1 in Embodiment 1;

FIG. 3 is a cross-sectional view showing a step performed after the step shown in FIG. 2 in the embodiment.

FIG. 4 is a cross-sectional view showing a step performed after the step shown in FIG. 3 in the embodiment.

FIG. 5 is a cross-sectional view showing a step performed after the step shown in FIG. 4 in the embodiment.

FIG. 6 is a diagram showing a plane in a process shown in FIG. 5 in the embodiment.

FIG. 7 is a cross-sectional view showing a step performed after the step shown in FIG. 5 in the embodiment.

FIG. 8 is a cross-sectional view showing a step performed after the step shown in FIG. 7 in the embodiment.

FIG. 9 is a cross-sectional view showing a step performed after the step shown in FIG. 8 in the embodiment.

FIG. 10 is a cross-sectional view showing a step performed after the step shown in FIG. 9 in the embodiment.

FIG. 11 is a second cross-sectional view showing a step performed after the step shown in FIG. 9 in the embodiment.

FIG. 12 is a diagram showing a plane in a process shown in FIG. 10 in the embodiment.

FIG. 13 is a cross-sectional view showing a step performed after the step shown in FIG. 10 in the embodiment.

FIG. 14 is a cross-sectional view showing a step performed after the step shown in FIG. 13 in the embodiment.

FIG. 15 is a cross-sectional view showing a step performed after the step shown in FIG. 14 in the embodiment.

FIG. 16 is a cross-sectional view showing a step performed after the step shown in FIG. 15 in the embodiment.

FIG. 17 is a cross-sectional view showing a step performed after the step shown in FIG. 16 in the embodiment.

FIG. 18 is a cross-sectional view showing a step performed after the step shown in FIG. 17 in the embodiment.

FIG. 19 is a diagram showing a plane in a process shown in FIG. 18 in the embodiment.

FIG. 20 is a diagram showing a circuit of the semiconductor device in the embodiment.

FIG. 21 is a diagram illustrating the operation of the semiconductor device in the embodiment.

FIG. 22 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device in the second embodiment of the present invention.

FIG. 23 is a cross-sectional view showing a step performed after the step shown in FIG. 22 in the embodiment.

FIG. 24 is a diagram showing a plane in a process shown in FIG. 23 in Embodiment 3;

FIG. 25 is a cross-sectional view showing a step performed after the step shown in FIG. 23 in the embodiment.

FIG. 26 is a cross-sectional view showing a step performed after the step shown in FIG. 25 in the embodiment.

FIG. 27 is a diagram showing a plane in the process shown in FIG. 26 in Embodiment 3;

FIG. 28 is a cross-sectional view showing a step performed after the step shown in FIG. 26 in the embodiment.

FIG. 29 is a cross-sectional view showing a step performed after the step shown in FIG. 28 in the embodiment.

FIG. 30 is a diagram showing a plane in a process shown in FIG. 29 in Embodiment 3;

FIG. 31 is a cross-sectional view showing a step performed after the step shown in FIG. 29 in the embodiment.

FIG. 32 is a diagram showing a plane in the process shown in FIG. 31 in Embodiment 3;

FIG. 33 is a plan view showing one step of a method for manufacturing a semiconductor device in the third embodiment of the present invention.

FIG. 34 is a plan view showing a step performed after the step shown in FIG. 33 in the embodiment.

FIG. 35 is a plan view showing a step performed after the step shown in FIG. 34 in the embodiment.

FIG. 36 is a plan view showing a step performed after the step shown in FIG. 35 in the embodiment.

FIG. 37 is a block diagram showing a circuit of a first semiconductor device in the related art.

FIG. 38 is a view showing a cross section of a first semiconductor device in a conventional technique.

FIG. 39 is a block diagram showing a circuit of a second semiconductor device in the related art.

FIG. 40 is a block diagram showing a circuit of a third semiconductor device in the related art.

FIG. 41 is a block diagram showing a fourth semiconductor circuit in the related art.

FIG. 42 is a view showing a cross section of a fourth semiconductor device according to a conventional technique.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate, 2 silicon oxide film, 3 gate insulating film, 4 gate electrode, 5a, 5b impurity diffusion region, 1
1 plug, 15, 16 wiring, 13c channel region, 18a, 18b source / drain region.

Claims (5)

[Claims] A second conductive type first and second impurity diffusion region formed on a main surface of a first conductive type semiconductor substrate at predetermined intervals; and a first and a second impurity diffusion region. A first electrode formed on a region sandwiched by the first insulating film with a first insulating film interposed therebetween; a second insulating film formed on the main surface so as to fill the first electrode; (2) a second and a third electrode respectively formed so as to fill an opening formed in the second insulating film exposing a surface of the impurity diffusion region; and a third insulating film on the second electrode. A second conductivity type semiconductor region formed interposed therebetween; a fourth electrode electrically connected to the first electrode, formed on the semiconductor region with a fourth insulating film interposed therebetween; Formed on the insulating film and sandwiching the semiconductor region. A first conductive type first semiconductor layer and a first conductive type second semiconductor layer electrically connected to the third electrode. 2. The semiconductor device according to claim 1, further comprising a metal silicide layer formed on each of the first and second semiconductor layers.
3. The semiconductor device according to claim 1. 3. The first and second conductive type first and second conductive type semiconductor substrates are formed at predetermined intervals on a main surface of a first conductive type semiconductor substrate.
An impurity diffusion region, a first electrode formed on a region sandwiched between the first and second impurity diffusion regions with a first insulating film interposed therebetween, and electrically connected to the first and second impurity diffusion regions. A second insulating film formed on the main surface so as to embed the first to third electrodes, a second insulating film formed on the main surface so as to embed the first to third electrodes, a second insulating film formed on the second insulating film, A fourth electrode electrically connected to the first electrode, a fifth electrode electrically connected to the third electrode, and a second conductivity type semiconductor region sandwiched between the fourth electrode and the fifth electrode And a third insulating film sandwiched between the fourth electrode and the semiconductor region and between the fifth electrode and the semiconductor region, respectively, from a direction substantially orthogonal to a direction from the fourth electrode to the fifth electrode. Third of the first conductivity type sandwiching the semiconductor region And a fourth impurity diffusion region formed on the second insulating film and the semiconductor region, a fourth electrode, a fifth electrode, and a third electrode.
And a fourth insulating film filling the fourth impurity diffusion region; a first wiring layer formed on the fourth insulating film and electrically connected to the third impurity diffusion region; A semiconductor device, comprising: a second wiring layer formed and electrically connected to the fourth impurity diffusion region and the second electrode. 4. A step of forming first and second impurity diffusion regions of a second conductivity type on a main surface of a semiconductor substrate of a first conductivity type at a predetermined interval, and forming the first and second impurity diffusion regions of the main surface. Forming a first electrode on a region interposed between the two impurity diffusion regions with a first insulating film interposed therebetween; and forming a second insulating film on the main surface so as to fill the first electrode. Forming first and second openings in the second insulating film so as to expose the surfaces of the first and second impurity diffusion regions, respectively, and filling the first and second openings. Forming a second and a third electrode respectively so as to fit in; a step of substantially aligning a surface of the second insulating film with an upper surface of the second and the third electrode; Forming a third insulating film on the second insulating film including an upper surface; Forming first and second semiconductor layers of a second conductivity type connected to each other on the third insulating film above the second electrode; and electrically connecting the third electrode and the second semiconductor layer to each other. Forming a fourth electrode electrically connected to the first electrode on a semiconductor layer sandwiched between the first and second semiconductor layers with a fourth insulating film interposed therebetween. Using the fourth electrode as a mask, introducing a first conductivity type impurity into the first and second semiconductor layers to form third and fourth impurity regions, respectively. . 5. A step of forming first and second impurity diffusion regions of a second conductivity type at predetermined intervals on a main surface of a semiconductor substrate of a first conductivity type; and forming the first and second impurity diffusion regions of the main surface. Forming a first electrode on a region interposed between the two impurity diffusion regions with a first insulating film interposed therebetween; and forming a second insulating film on the main surface so as to fill the first electrode. Forming first and second openings in the second insulating film so as to expose the surfaces of the first and second impurity diffusion regions, respectively, and filling the first and second openings. Forming the second and third electrodes, respectively; substantially aligning the surface of the second insulating film with the upper surfaces of the first to third electrodes; Forming a third insulating film on the second insulating film including the third insulating film; Forming a third opening in the film so as to expose the surfaces of the first and third electrodes, respectively; and a fourth electrically connected to the first electrode in the third opening. An electrode and a fifth electrode electrically connected to the third electrode.
An electrode; a second conductivity type semiconductor region having a fourth insulating film interposed between the fourth and fifth electrodes;
Forming third and fourth impurity diffusion regions of the first conductivity type facing each other in a direction substantially orthogonal to the direction from the electrode toward the fifth electrode; and forming the third impurity diffusion region on the third insulating film. Forming a first wiring layer electrically connected to the impurity diffusion region; and electrically connecting to the third electrode on the third insulating film and electrically connecting to the fourth impurity diffusion region. Forming a second wiring layer connected to the semiconductor device.