JPH07321204A - Semiconductor device and manufacture - Google Patents

Abstract

PURPOSE:To obtain a through contact construction having high reliability at the contacts between interconnection layers. CONSTITUTION:On the occasion of etching interlayer insulating films 12 and 14 and etching an interconnection layer 13 in the direction of its film thickness up to its midway part, etching is performed on condition of high etching selection ratios of the interlayer insulating films 12 and 14 to the interconnection layer 13. Only on the occasion of etching penetrating the wiring layer 13, it is performed on condition of these etching selection ratios being low. As a result of this, a part penetrating the interconnection layer 13 of a contact hole 15 becomes to have a forward tapering shape, and the contact area of this wiring layer 13 with an interconnection layer 16 is wide, even if the film thickness of the layer 13 is thin.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a so-called through contact structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art A shared contact structure or a so-called through contact structure is known as a structure effective for reducing the number of steps for opening contact holes and reducing the required area because three or more wiring layers can be simultaneously connected. Has been.

FIG. 6 shows a shared contact structure among them. In order to form this shared contact structure, the first wiring layer 11 is patterned on a base (not shown), and this wiring layer 11 is covered with an interlayer insulating film 12. Then, the second wiring layer 13 is patterned on the interlayer insulating film 12, and the wiring layer 13 is covered with the interlayer insulating film 14.

After that, the interlayer insulating films 14 and 12 are continuously etched by using the wiring layer 13 as a stopper, and the wiring layer 1
The contact hole 15 reaching 1 is opened. Then, the third wiring layer 16 that contacts both the wiring layers 11 and 13 in the contact hole 15 is patterned on the interlayer insulating film 14.

FIG. 7 shows a through contact structure. Also in the formation of this through contact structure, substantially the same steps as in the case of the shared contact structure are executed until the formation of the interlayer insulating film 14. Then, the interlayer insulating film 14, the wiring layer 13, and the interlayer insulating film 12 are continuously etched to form a contact hole 15 penetrating the wiring layer 13 and reaching the wiring layer 11, and thereafter, a first layer is formed on the interlayer insulating film 14. Three
The wiring layer 16 of the first layer is patterned.

By the way, in the shared contact structure shown in FIG. 6, when the diameter of the contact hole 15 is small and the alignment accuracy of lithography with respect to this diameter is low, the wiring layer 13 may be displaced from the contact hole 15. . Therefore, it is difficult to improve both reliability and fineness of contact between the wiring layers 13 and 16 at the same time.

On the other hand, in the through contact structure shown in FIG. 7, since the contact hole 15 penetrates the wiring layer 13, there is no possibility that the wiring layer 13 will be displaced from the contact hole 15. Therefore, the diameter of the contact hole 15 can be reduced and the fineness can be increased.

[0008]

However, as apparent from FIG. 7, since the wiring layers 13 and 16 are in contact with each other only on the side surface of the wiring layer 13 exposed in the contact hole 15, this contact is made. Since the area is small, the reliability of the contact between the wiring layers 13 and 16 is still low.

[0009]

According to another aspect of the present invention, there is provided a semiconductor device comprising: interlayer insulating films 12, 14, 25, 2 of lower and upper layers.
7, 32 and their interlayer insulating films 12, 14, 25, 2
Wiring layers 13, 26, 31 provided between 7, 32
In the semiconductor device in which the contact holes 15 and 51 pass through and the wiring layers 13, 26 and 31 are exposed in the contact holes 15 and 51, the contact hole 1
The portions of the wirings 5, 51 that penetrate the wiring layers 13, 26, 31 are the lower interlayer insulating films 12, 25, 27.
It is characterized in that it has a forward tapered shape that spreads from the side toward the upper interlayer insulating films 14, 27, 32.

In the method of manufacturing a semiconductor device according to a second aspect of the present invention, the lower and upper interlayer insulating films 12, 14, 25, 27 and 32 are provided between the interlayer insulating films 12, 14, 25, 27 and 32. The contact holes 15 and 51 penetrate through the wiring layers 13, 26 and 31 which are formed.
In the method of manufacturing a semiconductor device in which the wiring layers 13, 26 and 31 are exposed in the portions 5, 51, the contact hole 1
Using the mask layers 17 and 33 having the patterns of 5 and 51 as masks, the etching selection ratio of the interlayer insulating films 12, 14, 25, 27 and 32 to the wiring layers 13, 26 and 31 is relatively high, The upper interlayer insulating films 14 and 2
After performing the step of etching 7 and 32 and the etching of the upper interlayer insulating films 14, 27 and 32, the mask layers 17 and 33 are used as a mask under the condition that the etching selection ratio is relatively high. Wiring layer 13,
After the first etching of the wiring layers 13, 26, 31 by performing a first etching on the wiring layers 13, 26, 31 and the first etching of the wiring layers 13, 26, 31, the mask layer 17, 33 as a mask under the condition that the etching selection ratio is relatively low, the wiring layer 13, until the lower interlayer insulating films 12, 25, 27 are exposed.
The step of performing the second etching on 26 and 31 and the lower interlayer insulating film 1 under the condition that the etching selection ratio is relatively high using the mask layers 17 and 33 as a mask.
2, 25 and 27 are etched.

A method for manufacturing a semiconductor device according to a third aspect is the method for manufacturing a semiconductor device according to the second aspect, wherein a fluorocarbon-based gas is used as the gas for the etching, and a ratio of carbon in the gas is relatively set. It is characterized in that the etching selectivity is relatively high by increasing the ratio to a relatively high value, and the etching selectivity is relatively low by increasing the ratio of fluorine in the gas relatively.

A method for manufacturing a semiconductor device according to a fourth aspect is the method for manufacturing a semiconductor device according to the second aspect, wherein a fluorocarbon-based gas to which oxygen is added is used as the etching gas, and oxygen in the gas is added. It is characterized in that the etching selection ratio is made relatively high by making the ratio relatively low, and the etching selection ratio is made relatively low by making the ratio of oxygen in the gas relatively high. .

A method of manufacturing a semiconductor device according to a fifth aspect is the method of manufacturing a semiconductor device according to the second aspect, wherein a fluorocarbon-based gas is used as a gas for the etching, and silicon on an inner wall of a chamber 41 for performing the etching is used. By making the exposed area of 42 relatively large, the etching selection ratio is relatively high, and by making the exposed area relatively small, the etching selection ratio is relatively low.

[0014]

In the semiconductor device according to claim 1, the contact hole 1
Since the portions of the wirings 5, 51 that penetrate the wiring layers 13, 26, 31 are forward tapered, the wiring layers 13, 2
Even if the film thicknesses of 6, 31 are thin, the wiring layers 13, 26, 3
1 and another wiring layer 1 filling the contact holes 15 and 51
The contact area with 6, 52 is wide.

In the method of manufacturing a semiconductor device according to a second aspect of the present invention, when the interlayer insulating films 12, 14, 25, 27, 32 are etched and the wiring layers 13, 26, 31 are first etched, the wiring layers 13, 26, It is performed under the condition that the etching selection ratio of the interlayer insulating films 12, 14, 25, 27 and 32 with respect to 31 is relatively high.
Since the etching selectivity is relatively low only when the second etching is performed on the layers 6 and 31, the interlayer insulating film 12 of the contact holes 15 and 51,
The portions penetrating 14, 25, 27 and 32 have an anisotropic shape, and the portions penetrating the wiring layers 13, 26 and 31 have a forward tapered shape in a self-aligning manner.

In the method of manufacturing a semiconductor device according to the third aspect of the present invention, if the proportion of carbon in the fluorocarbon-based gas is increased, the deposition of the carbon-based compound increases and the amount of fluorine radicals generated decreases. As a result, the wiring layers 13 and 2
Since the film thickness of the carbon-based compound as the protective film for 6 and 31 is increased and the fluorine radicals as etching species for the wiring layers 13, 26 and 31 are reduced, the interlayer insulating film 12 for the wiring layers 13, 26 and 31 is reduced. , 14, 2
The etching selection ratio of 5, 27 and 32 is increased. vice versa,
The higher the proportion of fluorine, the lower this etching selectivity ratio.

In the method of manufacturing a semiconductor device according to a fourth aspect, dissociation of oxygen-containing fluorocarbon gas can be suppressed by reducing the proportion of oxygen in the gas. As a result, the number of fluorine radicals as etching species for the wiring layers 13, 26 and 31 is reduced, so that
Interlayer insulating films 12, 14, 25, 2 for 26, 31
The etching selection ratio of 7 and 32 becomes high. On the contrary, if the proportion of oxygen is increased, the dissociation of this gas is promoted and the etching selection ratio is lowered.

In the method of manufacturing the semiconductor device according to the fifth aspect, the silicon 4 on the inner wall of the chamber 41 for etching is used.
When the exposed area of 2 is increased, the rate of trapping the fluorine radicals generated by the dissociation of the fluorocarbon gas increases. As a result, the number of fluorine radicals as etching species for the wiring layers 13, 26 and 31 is reduced,
Interlayer insulating films 12, 1 for the wiring layers 13, 26, 31
The etching selection ratios of 4, 25, 27 and 32 are increased.
On the contrary, if the exposed area is made smaller, this etching selection ratio becomes lower.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First to fourth embodiments of the present invention will be described below with reference to FIGS. The components corresponding to those of the conventional example shown in FIG. 7 are designated by the same reference numerals.

FIG. 1 shows a first embodiment applied to a semiconductor device in which three wiring layers are simultaneously connected. This first
In the embodiment, as shown in FIG. 1A, a wiring layer 11 which is an n-type polycrystalline Si film is deposited by CVD on an underlayer (not shown) such as a SiO ₂ film to a thickness of 50 nm. Then, the wiring layer 11 is patterned by lithography and etching. Then, the interlayer insulating film 12, which is a SiO ₂ film, is deposited to a thickness of 230 nm by the low pressure CVD method.

After that, the wiring layer 13 which is an n-type polycrystalline Si film is deposited to a film thickness of 70 nm by the CVD method, and the wiring layer 13 is patterned by lithography and etching. Then, the interlayer insulating film 14 which is a SiO ₂ film is deposited to a film thickness of 150 nm by the low pressure CVD method.

Next, as shown in FIG. 1B, a resist 17 is applied on the interlayer insulating film 14, and the resist 17 is patterned by lithography in the pattern of the contact hole to be formed.

Next, by using the resist 17 as a mask and performing ECR plasma etching using a fluorocarbon gas such as C ₄ F ₈ as an etching gas, FIG.
As shown in (c), the contact hole 15 is formed in the interlayer insulating film 14.
And the wiring layer 13 is formed by overetching.
Etch halfway. At this time, since the etching selection ratio of SiO _{2 to} polycrystalline Si is high, the wiring layer 1
By the etching up to the middle of 3, the wiring layer 13 has a concave cross section.

Next, as shown in FIG. 1 (d), ECR plasma etching is performed using the resist 17 as a mask and a fluorocarbon-based gas containing oxygen such as C ₄ F ₈ / O ₂ as an etching gas. The wiring layer 13 is etched until the interlayer insulating film 12 is exposed. At this time,
Since the etching selection ratio of SiO _{2 to} polycrystalline Si is low, the portion of the contact hole 15 penetrating the wiring layer 13 has a forward tapered shape.

Next, under the same conditions as when the interlayer insulating film 14 was etched, as shown in FIG.
2 is etched to complete the contact hole 15 reaching the wiring layer 11. At this time, Si with respect to polycrystalline Si
Since the etching selectivity of O ₂ is high, the contact hole 15
Among these, the shape of the portion penetrating the wiring layer 13 is maintained in a forward tapered shape. Then, the resist 17 is peeled off.

Next, as shown in FIG. 1F, the wiring layer 16 which is an n-type polycrystalline Si film is deposited to a thickness of 30 nm by the CVD method, and is formed in the contact hole 15 by lithography and etching. The wiring layer 16 that contacts both the wiring layers 11 and 13 is patterned. Then, the semiconductor device is completed through conventionally known steps.

FIG. 2 shows a second example applied to a TFT load type SRAM having a double gate structure in which four wiring layers are simultaneously connected.
-The 4th example is shown. In any of these second to fourth embodiments, as shown in FIG.
A SiO ₂ film 22 is selectively formed on the surface of No. 1 to partition an element isolation region, and an SiO ₂ film 23 as a gate oxide film is formed on the surface of an element active region surrounded by the SiO ₂ film 22.

After that, the tungsten polycide layer 24 is processed into a pattern of gate electrodes of a driving transistor and a transfer transistor in a pair of inverters whose input and output are cross-coupled to form a flip-flop which constitutes a memory cell. After forming the source / drain (not shown) on the Si substrate 21, the tungsten polycide layer 24 and the like are covered with an interlayer insulating film 25 which is a SiO ₂ film.

Then, a polycrystalline Si layer 26 having a film thickness of 50 nm is processed on the interlayer insulating film 25 to form a pattern of the bottom gate electrode of the thin film transistor which is a load element of the inverter, and the interlayer insulating film 27 which is a SiO ₂ film is processed. And polycrystalline Si
Cover layer 26 and the like. The pattern of the active layer of the thin film transistor and the power supply line is made of polycrystalline S having a thickness of 30 nm.
The i layer 31 is processed on the interlayer insulating film 27, and the polycrystalline Si
After forming the source / drain (not shown) of the thin film transistor in the layer 31, the polycrystalline Si layer 31 and the like are covered with the interlayer insulating film 32 which is a SiO ₂ film.

After that, a pattern of contact holes for connecting the bottom gate electrode of the thin film transistor, the top gate electrode, the gate electrode of the driving transistor, and the drains of the other thin film transistors in the pair of inverters to each other is formed into a novolac-based i-line resist. 33 is processed on the interlayer insulating film 32.

In the second embodiment, from this state, the resist 33 is used as a mask to perform etching using the high frequency bias application type ECR plasma etching apparatus 34 shown in FIG. In this etching device 34, the magnetron 3
The microwave generated in 5 is guided into the chamber 41 through the waveguide 36 and the quartz window 37.

A Si layer 42 is applied to the inner wall of the chamber 41, and a cylindrical shutter 43 that can move up and down in the direction of the arrow in FIG. 3 is provided in the chamber 41 along the inner wall. Therefore, by raising and lowering the shutter 43, the exposed area of the Si layer 42 can be controlled.

In the chamber 41, a wafer stage 45 for mounting a wafer 44 and the wafer stage 4
Clamp 46 made of Si for fixing the wafer 44 to the wafer 5.
Are provided, and a high frequency power source 47 for applying a high frequency bias is connected to the wafer stage 45. Further, a solenoid coil 48 for generating a magnetic field in the chamber 41 is provided on the outer circumference of the chamber 41.

In the second embodiment, the etching apparatus 34 described above is used under the following first condition to open a contact hole 51 in the interlayer insulating film 32 as shown in FIG. The polycrystalline Si layer 31 is partially etched by etching. Etching gas C ₄ F ₈ = 50 SCCM Pressure 0.27 Pa Microwave output 1200 W High frequency bias 200 W (800 kHz) Wafer temperature 20 ° C. Chamber temperature 250 ° C. Shutter opening 0%

Under the above-mentioned first condition, since the etching selection ratio of SiO ₂ with respect to polycrystalline Si is high, the polycrystalline Si layer 3 is etched up to the middle thereof.
The cross section of 1 becomes concave.

After that, the etching gas was changed to C ₄ F ₈ / O ₂
= 50/2 SCCM, the polycrystalline Si layer 31 is etched under the second condition which is the same as the first condition, using the resist 33 as a mask until the interlayer insulating film 27 is exposed. At this time, since the etching selection ratio of SiO _{2 to} the polycrystalline Si is low, the portion of the contact hole 51 penetrating the polycrystalline Si layer 31 has a forward tapered shape.

Next, as shown in FIG. 2C, the same etching as that for the interlayer insulating film 32 and the polycrystalline Si layer 31 is repeated for the interlayer insulating film 27 and the polycrystalline Si layer 26. Since the amount of fluorine radicals generated under the second condition is larger than that under the first condition, the polycrystalline Si layer 3
When etching 1 and 26, the etching rate of the resist 33 also increases. However, as described above, since the polycrystalline Si layers 31 and 26 have thin film thicknesses of 30 and 50 nm, respectively, the etching time is short and there is no practical inconvenience.

Next, as shown in FIG. 2D, an etching similar to the etching on the interlayer insulating films 32 and 27 is performed on the interlayer insulating film 25, so that the tungsten polycide layer 24 is formed.
After completing the contact hole 51 reaching to
3 is peeled off. Then, the polycrystalline Si layer 52 is formed on the pattern of the top gate electrode of the thin film transistor by the interlayer insulating film 3
2 is processed, and then, through a conventionally known process, the double gate structure TFT load type SRAM is completed.

Next, a third embodiment will be described. The third embodiment is different from the second embodiment described above except for the etching apparatus used in the steps shown in FIGS. 2A to 2D and the first and second conditions when the etching apparatus is used. Substantially the same steps are performed. This third embodiment is shown in FIG.
In the steps (a) to (d), an inductively coupled plasma (ICP = Induction Coupled Plasma) type etching apparatus 53 shown in FIG. 4 is used.

In this etching apparatus 53, the chamber 4
An inductive coupling coil 54 is wound around the outer circumference of 1
A high frequency power supply 55 for applying a high frequency of Hz is connected to the inductive coupling coil 54. The lower surface of the upper electrode 56, which is a part of the chamber 41, that is, the inner wall of the chamber 41 is coated with a Si layer 42, and a shutter 43 movable along the inner wall in the direction of the arrow in FIG. It is provided inside. Therefore, the exposed area of the Si layer 42 can be controlled by moving the shutter 43.

Outside the chamber 41 and on the upper electrode 56
A heater 57 is provided on the top. The wafer stage 45, the clamp 46, the high frequency power source 47 and the like have substantially the same configuration as the high frequency bias application type ECR plasma etching apparatus 34 shown in FIG.

In the third embodiment, the following third condition is used instead of the first condition in the second embodiment. Etching gas C ₂ F ₆ = 50 SCCM Pressure 0.27 Pa Source output 2000 W High frequency bias 800 W Wafer temperature −50 ° C. Chamber temperature 270 ° C. Shutter opening 0%

Further, in this third embodiment, instead of the above-mentioned second condition in the above-mentioned second embodiment, the etching gas is C ₂ F ₆ / O ₂ = 50/5 SCCM, and the above-mentioned third embodiment. The same fourth condition as the condition is used.

Next, a fourth embodiment will be described. This fourth embodiment is also the above-mentioned second embodiment except for the etching apparatus used in the steps shown in FIGS. 2A to 2D and the first and second conditions when the etching apparatus is used. Substantially the same steps are performed. This fourth embodiment is shown in FIG.
In the steps (a) to (d), the helicon wave plasma type etching apparatus 61 shown in FIG. 5 is used.

In this etching apparatus 61, the chamber 4
The antenna 62 is provided so as to penetrate the wall surface of 1.
A source power supply 63 for applying a high frequency bias of 3.56 MHz is connected to the antenna 62. A Si layer 42 is applied to the inner wall of the chamber 41, and a shutter 43 movable along the inner wall in the direction of the arrow in FIG. 5 is provided in the chamber 41. Therefore, the shutter 4
By moving 3 the exposed area of the Si layer 42 can be controlled.

A solenoid coil 48 and a multi-pole magnet 64 are provided on the outer circumference of the chamber 41. The wafer stage 45, the clamp 46, the high frequency power source 47 and the like have substantially the same configuration as the high frequency bias application type ECR plasma etching apparatus 34 shown in FIG.

In such an etching device 61, the chamber 4 is operated by the action of the high frequency bias applied to the antenna 62 and the magnetic field generated by the solenoid coil 48.
Whistler (helicon) waves are generated in 1 and the resulting high density plasma reaches the wafer 44.

In the fourth embodiment, the following fifth condition is used instead of the first condition in the second embodiment. Etching gas CHF ₃ = 50 SCCM Pressure 0.1 Pa Microwave output 2500 W High frequency bias 300 W Wafer temperature 20 ° C. Chamber temperature 250 ° C. Shutter opening 100%

Further, in the fourth embodiment, instead of the second condition in the second embodiment, the sixth condition which is the same as the fifth condition except that the shutter opening is 50% is used. To use.

The high frequency bias application type ECR plasma etching apparatus 3 used in the above second and third embodiments.
The 4 and the inductively coupled plasma type etching apparatus 53 also have the shutter 43 for controlling the exposed area of the Si layer 42. By controlling only the opening, the same result as when the etching gas is switched can be obtained.

Further, in any of the above-mentioned first to fourth embodiments, in order to control the etching selection ratio of SiO ₂ with respect to polycrystalline Si, the ratio of the fluorine radical itself in the etching gas is directly controlled. However, the proportion of fluorine radicals may be indirectly controlled by controlling the proportion of fluorine in the fluorocarbon gas.

[0052]

According to the semiconductor device of the first aspect, even if the wiring layer penetrating the contact hole is thin, the contact area between this wiring layer and another wiring layer filling the contact hole is large. Therefore, the contact between wiring layers is highly reliable.

In the method of manufacturing a semiconductor device according to a second aspect, a portion of the contact hole that penetrates the interlayer insulating film has an anisotropic shape, and a portion that penetrates the wiring layer has a tapered shape. Even if the film thickness is thin, the contact area between this wiring layer and another wiring layer filling the contact hole can be increased. In addition, since the portion of the contact hole that penetrates the wiring layer is not an inverse tapered shape but a forward tapered shape, the wiring layer and another wiring layer that fills the contact hole can be reliably brought into contact with each other.

Furthermore, since the portion of the contact hole that penetrates the wiring layer is forward-tapered in a self-aligning manner, this forward-tapered shape can be formed even if the diameter of the contact hole is small. Therefore, in the method of manufacturing a semiconductor device according to the second aspect, it is possible to manufacture a fine and highly reliable semiconductor device in a contact between wiring layers.

In the method for manufacturing a semiconductor device according to the present invention, the etching selection ratio of the interlayer insulating film to the wiring layer can be controlled only by controlling the composition ratio of the fluorocarbon gas or the ratio of oxygen added to the fluorocarbon gas. Therefore, it is possible to manufacture a highly reliable and fine semiconductor device in contact between wiring layers with high throughput.

In the method of manufacturing a semiconductor device according to a fifth aspect, the etching selection ratio of the interlayer insulating film to the wiring layer is mechanically and quickly controlled only by controlling the exposed area of silicon on the inner wall of the chamber for etching. Therefore, a highly reliable and fine semiconductor device in contact between wiring layers can be manufactured with higher throughput.

[Brief description of drawings]

FIG. 1 is a side sectional view showing a first embodiment of the present invention in the order of steps.

FIG. 2 is a side sectional view showing the second to fourth embodiments of the invention of the present application in the order of steps.

FIG. 3 is a schematic side sectional view of an etching apparatus used in a second embodiment.

FIG. 4 is a schematic side sectional view of an etching apparatus used in a third embodiment.

FIG. 5 is a schematic side sectional view of an etching apparatus used in a fourth embodiment.

FIG. 6 is a side sectional view of a reference example with respect to a conventional example of the present invention.

FIG. 7 is a side sectional view showing a conventional example of the present invention.

[Explanation of symbols]

 12 Interlayer Insulating Film 13 Wiring Layer 14 Interlayer Insulating Film 15 Contact Hole 17 Resist 25 Interlayer Insulating Film 26 Polycrystalline Si Layer 27 Interlayer Insulating Film 31 Polycrystalline Si Layer 32 Interlayer Insulating Film 33 Resist 41 Chamber 42 Si Layer 51 Contact Hole

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 21/302 M 21/88 D

Claims (5)

[Claims] 1. A contact hole penetrates through lower and upper interlayer insulating films and a wiring layer provided between these interlayer insulating films, and the wiring layer is exposed in the contact hole. In the semiconductor device, a portion of the contact hole that penetrates the wiring layer is a forward taper shape that spreads from the lower interlayer insulating film side toward the upper interlayer insulating film side. Semiconductor device. 2. A contact hole penetrates the lower and upper interlayer insulating films and a wiring layer provided between these interlayer insulating films, and the wiring layer is exposed in the contact hole. In the method for manufacturing a semiconductor device, the upper interlayer insulating film is etched under the condition that an etching selection ratio of the interlayer insulating film to the wiring layer is relatively high using the mask layer of the contact hole pattern as a mask. And the step of etching the upper interlayer insulating film, the first etching is performed on the wiring layer under the condition that the etching selection ratio is relatively high using the mask layer as a mask, After the step of making the cross section concave, and after the first etching of the wiring layer, the etching selectivity is relatively low using the mask layer as a mask. A step of performing a second etching on the wiring layer until the lower interlayer insulating film is exposed under the conditions; and using the mask layer as a mask, the etching selectivity ratio is relatively high, and the lower interlayer And a step of etching the insulating film. 3. A fluorocarbon-based gas is used as the gas for the etching, and the etching selection ratio is relatively increased by relatively increasing the ratio of carbon in the gas. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the etching selectivity is relatively lowered by relatively increasing the proportion of fluorine. 4. A fluorocarbon-based gas to which oxygen is added is used as the gas for the etching, and the etching selection ratio is relatively increased by relatively lowering the proportion of oxygen in the gas. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the etching selection ratio is relatively lowered by relatively increasing the proportion of oxygen in the gas. 5. A fluorocarbon-based gas is used as the gas for the etching, and the etching selectivity is relatively increased by relatively increasing the exposed area of silicon on the inner wall of the chamber for performing the etching. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the etching selection ratio is made relatively low by making the exposed area relatively small.