KR0124646B1 - Metal Film Manufacturing Method of Semiconductor Device - Google Patents
Metal Film Manufacturing Method of Semiconductor DeviceInfo
- Publication number
- KR0124646B1 KR0124646B1 KR1019940016477A KR19940016477A KR0124646B1 KR 0124646 B1 KR0124646 B1 KR 0124646B1 KR 1019940016477 A KR1019940016477 A KR 1019940016477A KR 19940016477 A KR19940016477 A KR 19940016477A KR 0124646 B1 KR0124646 B1 KR 0124646B1
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- Prior art keywords
- metal film
- metal
- film
- semiconductor device
- manufacturing
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- 239000002184 metal Substances 0.000 title claims abstract description 72
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 238000009792 diffusion process Methods 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 10
- 230000003667 anti-reflective effect Effects 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 239000011521 glass Substances 0.000 abstract description 2
- 230000002265 prevention Effects 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 230000004888 barrier function Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000010926 purge Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
제1도는 종래의 반도체 장치의 금속막 제조방법을 도시한 공정단면도.1 is a process cross-sectional view showing a metal film production method of a conventional semiconductor device.
제2도는 본 발명의 반도체 장치의 금속막 제조방법을 도시한 공정단면도.2 is a process cross-sectional view showing a metal film production method of a semiconductor device of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
15 : 반도체 기판 16 : 게이트전극15 semiconductor substrate 16 gate electrode
17 : 제1산화막 18 : 제2산화막17: first oxide film 18: second oxide film
19 : 제1확산방지금속막 20 : 제1절연산화막19: first diffusion preventing metal film 20: first insulating oxide film
21 : SOG 22 : 제2확산방지금속막21: SOG 22: second diffusion barrier metal film
23 : 1차 금속층 24 : 제1반사방지금속막23: primary metal layer 24: first antireflection metal film
25 : 제2절연산화막 26 : 제3확산방지금속막25 second insulating oxide film 26 third diffusion preventing metal film
27 : 2차 금속층 28 : 제2반사방지금속막.27: secondary metal layer 28: second antireflection metal film.
본 발명은 반도체 장치의 금속막 제조방법에 관한 것으로 특히, 고집적화, 초미세화, 그리고 다층 금속배선형성에 적당하도록 한 반도체 장치의 금속막 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a metal film of a semiconductor device, and more particularly, to a method of manufacturing a metal film of a semiconductor device, which is suitable for high integration, ultrafineness, and multilayer metal wiring formation.
반도체 장치의 기술이 갈수록 고집적화 및 초미세화가 되어감에 따라 제조공정의 정확성과 우수한 신뢰성이 요구된다. 그러나 종래의 반도체 장치는 정확성과 신뢰성의 저하로 금속막 제조시 차지하는 면적이 클뿐만 아니라 불필요한 문제점이 자연 발생적으로 생겨났다.As the technology of semiconductor devices becomes more integrated and ultra-fine, the accuracy and reliability of manufacturing processes are required. However, the conventional semiconductor device not only has a large area in manufacturing a metal film due to a decrease in accuracy and reliability, but also naturally causes unnecessary problems.
이중 종래에 사용하던 한가지 방법을 첨부된 도면을 참조하여 설명하면 다음과 같다.One method used in the related art will be described with reference to the accompanying drawings.
제1도는 종래의 반도체 장치의 금속막 제조방법을 도시한 공정단면도로써, 우선 제1도(a)와 같이 초기 산화막이 성장된 반도체 기판(1)상에 폴리실리콘을 증착하고 상기 초기산화막과 함께 게이트 패턴으로 패터닝하여 게이트전극(2)을 형성한 다음 전면에 제1산화막(3)과 제2산화막(4)을 차례로 증착한다.FIG. 1 is a process cross-sectional view illustrating a metal film manufacturing method of a conventional semiconductor device. First, polysilicon is deposited on a semiconductor substrate 1 on which an initial oxide film is grown, as shown in FIG. The gate electrode 2 is formed by patterning the gate pattern, and then the first oxide film 3 and the second oxide film 4 are sequentially deposited on the entire surface.
다음에 제1도(b)와 같이 상기 게이트전극(2)상에 형성된 상기 제1, 제2산화막(3,4)을 선택적으로 제거하여 콘택홀을 형성한 후 전면에 제1확산방지금속막(5), 1차 금속층(6), 그리고 제1반사방지금속막(7)을 차례로 증착한다. 이어서, 제1도(c)와 같이 상기 제1확산방지금속막(5), 1차 금속층(6), 그리고 제1반사방지금속막(7)을 사진 식각공정을 이용하여 선택적으로 제거함으로써 금속배선 패턴으로 패터닝한다.Next, as shown in FIG. 1 (b), the first and second oxide films 3 and 4 formed on the gate electrode 2 are selectively removed to form contact holes, and then the first diffusion preventing metal film is formed on the entire surface. (5), the primary metal layer 6, and the first antireflection metal film 7 are sequentially deposited. Subsequently, as shown in FIG. 1C, the first diffusion barrier metal film 5, the primary metal layer 6, and the first antireflection metal film 7 are selectively removed by using a photolithography process. Patterned by wiring pattern.
다음에 제1도(d)와 같이 전면에 제1절연산화막(8)을 증착하고, 금속배선간의 평탄화 및 얇은 금속배선절연막을 위해 전면에 SOG(Spin On Glass)(9)를 형성한 다음 상기 제1절연산화막(8)이 노출될때까지 상기 SOG(9)를 에치백한다.Next, a first insulating oxide film 8 is deposited on the front surface as shown in FIG. 1d, and a spin on glass 9 is formed on the front surface for planarization between the metal wirings and the thin metal wiring insulation film. The SOG 9 is etched back until the first insulating oxide film 8 is exposed.
그리고 상기 콘택홀 내부에 불량한 스텝-커버리지(Step-Coverage)로 인해 보이드(void)(10)가 발생한다.In addition, a void 10 is generated due to poor step-coverage in the contact hole.
이어서 제1도(e)와 같이 전면에 제2절연산화막(11), 제2확산방지금속막(12), 2차 금속층(13), 제2반사방지금속막(14)을 차례로 증착한다. 그리고 상기 제1, 제2확산방지금속막(5,12)과 제1,제2반사방지금속막(7,14)은 상기 1, 2차 금속층(6,13)의 스텝 커버리지, 오믹성, 그리고 열적 안정성을 고려하여 형성한다.Subsequently, a second insulating oxide film 11, a second diffusion preventing metal film 12, a secondary metal layer 13, and a second antireflection metal film 14 are sequentially deposited on the entire surface as shown in FIG. The first and second anti-diffusion metal films 5 and 12 and the first and second anti-reflective metal films 7 and 14 may include step coverage, ohmicity, And it forms in consideration of thermal stability.
이상에서 설명한 종래의 반도체 장치의 금속막 제조방법은 미세한 콘택홀 영역에서 제1확산방지금속막, 배선금속층 그리고 반사방지금속막 등의 중첩된 금속을 형성함으로써 불량한 스텝 커버리지가 발생하게 되고, 이로인해 보이드 발생을 초래하며 SOG의 에치백 공정에서 식각을 변화시 시간조절이 어려워 상기 SOG가 과다하게 식각될 경우, 결과적으로 반도체 장치의 신뢰성이 저하되는 문제점이 발생하였다.In the conventional method of manufacturing a metal film of a semiconductor device described above, poor step coverage is generated by forming an overlapping metal such as a first diffusion preventing metal film, a wiring metal layer, and an antireflective metal film in a fine contact hole region. When the SOG is excessively etched due to difficulty in controlling the etching during the etching back process of the SOG, the reliability of the semiconductor device is deteriorated.
본 발명은 상기의 문제점을 해결하기 위하여 인출한 것으로, 양호한 스텝 커버리지에 의해 보이드가 생성하지 않고 에치-앤드포인트(etch-endpoint)의 정화간 시간 관리에 적당한 반도체 장치의 금속막 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been drawn to solve the above problems, and provides a method for manufacturing a metal film of a semiconductor device suitable for time management between etch-endpoint purging without voids due to good step coverage. The purpose is.
상기 목적을 달성하기 위한 본 발명의 반도체 장치의 금속막 제조방법은 게이트전극이 형성된 반도체기판전면에 제1절연막을 형성한후, 상기 제1절연막을 패터닝하여 콘택홀을 형성하는 공정, 상기 콘택홀의 내면을 포함하여 상기 제1절연막상에 제1금속막, 제2절연막 그리고 평탄화물질을 순서로 형성하는 공정, 상기 기판전면을 에치백하여 상기 제1금속막을 노출시키는 공정과, 상기 기판전면에 배선금속층을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 한다.The metal film manufacturing method of the semiconductor device of the present invention for achieving the above object is a step of forming a contact hole by forming a first insulating film on the front surface of the semiconductor substrate on which a gate electrode is formed, patterning the first insulating film, the contact hole Forming a first metal film, a second insulating film, and a planarizing material in order on the first insulating film including an inner surface; etching the back surface of the substrate to expose the first metal film; and wiring on the front surface of the substrate. It comprises a process of forming a metal layer.
이하, 첨부된 도면으로 본 발명인 반도체 장치의 금속막 제조방법을 설명하면 다음과 같다.Hereinafter, a method of manufacturing a metal film of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.
제2도는 본 발명인 반도체 장치의 금속막 제조방법을 도시한 공정단면도로써, 우선 제2도(a)와 같이 초기산화막이 성장된 반도체 기판(15)상에 폴리실리콘을 증착하고 상기 초기산화막과 함께 게이트 패턴으로 패터닝하여 게이트 전극(16)을 형성한 다음 전면에 제1절연막을 증착한다. 여기서 상기 제1절연막을 제1산화막(17)과 제2산화막(18)의 적층으로 구성한다FIG. 2 is a process cross-sectional view showing a method of manufacturing a metal film of a semiconductor device according to the present invention. First, polysilicon is deposited on a semiconductor substrate 15 on which an initial oxide film is grown, as shown in FIG. The gate electrode 16 is formed by patterning the gate pattern, and then a first insulating layer is deposited on the entire surface. The first insulating film is formed by laminating the first oxide film 17 and the second oxide film 18.
다음에 제2도(b)와 같이 상기 게이트 전극 (2)사이에 형성된 상기 제1, 제2산화막(17,18)을 선택적으로 제거하여 콘택홀을 형성한 후 전면에 상기 반도체 기판과 접촉향상을 위해 제1확산방지금속층(19)을 증착하고 이어서 콘택홀 내부의 평탄화를 위해 제1절연산화막(20)을 형성하고, 금속배선간의 평탄화 및 얇은 금속 배선 절연을 위해 SOG(21)를 차례로 증착한다.Next, as shown in FIG. 2 (b), the first and second oxide films 17 and 18 formed between the gate electrodes 2 are selectively removed to form contact holes, and then contact with the semiconductor substrate is improved on the entire surface. The first diffusion barrier metal layer 19 is deposited to form a first insulating oxide film 20 to planarize the inside of the contact hole, and the SOG 21 is sequentially deposited to planarize the metal lines and to insulate the thin metal wiring. do.
이어서, 제2도(c) 와 같이 상기 SOG(21)를 에치백하면서 상기 제1확산방지금속층(19)이 노출되도록 상기 제1절연산화막(20)까지 제거한다.Subsequently, as illustrated in FIG. 2C, the SOG 21 is etched back and the first insulating oxide layer 20 is removed to expose the first diffusion preventing metal layer 19.
이와같이 함으로써, 콘택홀 내부에는 단지 상기 제1확산방지금속층(19)과 제1절연산화막(20)만이 형성되어 있기 때문에 평탄화물질인 SOG(21)를 도포할때에 보이드 발생을 막을 수 있게 된다.In this way, since only the first diffusion preventing metal layer 19 and the first insulating oxide film 20 are formed inside the contact hole, it is possible to prevent the generation of voids when the SOG 21 is applied.
다음에 제2도(d)와 같이 전면에 제2확산방지금속막(22), 배선 금속층인 1차 금속층(23), 그리고, 제1반사방지금속막(24)를 차례로 증착한다.Next, as shown in FIG. 2D, the second diffusion barrier metal film 22, the primary metal layer 23 as a wiring metal layer, and the first antireflection metal film 24 are sequentially deposited.
이어서 제2도(e)와 같이 전면에 제2절연산화막(25)과 제3확산방지금속막(26) 그리고 배선 금속층인 2차금속층(27) 및 제2반사방지금속막(28)을 차례로 증착한다.Subsequently, as shown in FIG. 2E, the second insulating oxide film 25, the third diffusion preventing metal film 26, the secondary metal layer 27, which is a wiring metal layer, and the second antireflection metal film 28 are sequentially disposed on the front surface. Deposit.
그리고, 상기 제1, 제2반사방지금속막(24,28)은 상기 1차, 2차금속층(23,27)의 스텝 커버리지, 오믹성, 그리고 열적 안정성을 고려하여 형성한다.The first and second anti-reflective metal layers 24 and 28 are formed in consideration of the step coverage, ohmicity, and thermal stability of the primary and secondary metal layers 23 and 27.
이상에서 설명한 바와같이 본 발명의 반도체 장치의 금속막 제조방법은 양호한 스텝-커버리지로 인해 보이드의 발생을 억제하며, 평탄하게 형성된 SOG의 에치백은 선택비가 다른 확산방지금속막의 노출까지 진행되므로 에치-앤드 포인트를 쉽게 설정할 수 있으며, 또한 SOG의 에치백시 빌드-업(Build-up)에 따른 제품의 신뢰성을 최소화하며 또한 평탄화된후에 금속배선을 함으로써 신뢰성을 향상시키는 효과가 있다.As described above, the metal film manufacturing method of the semiconductor device of the present invention suppresses the generation of voids due to good step-coverage, and the etch-back of the SOG which is formed flatly proceeds to the exposure of the diffusion preventing metal film having different selectivity. The end point can be easily set, and the reliability of the product due to build-up during etch back of SOG is minimized, and the metal wiring is improved after flattening, thereby improving reliability.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940016477A KR0124646B1 (en) | 1994-07-08 | 1994-07-08 | Metal Film Manufacturing Method of Semiconductor Device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940016477A KR0124646B1 (en) | 1994-07-08 | 1994-07-08 | Metal Film Manufacturing Method of Semiconductor Device |
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| KR0124646B1 true KR0124646B1 (en) | 1997-12-11 |
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| KR1019940016477A KR0124646B1 (en) | 1994-07-08 | 1994-07-08 | Metal Film Manufacturing Method of Semiconductor Device |
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1994
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