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JPH07211994A - Surface-mounting hybrid ic - Google Patents

Surface-mounting hybrid ic

Info

Publication number
JPH07211994A
JPH07211994A JP189394A JP189394A JPH07211994A JP H07211994 A JPH07211994 A JP H07211994A JP 189394 A JP189394 A JP 189394A JP 189394 A JP189394 A JP 189394A JP H07211994 A JPH07211994 A JP H07211994A
Authority
JP
Japan
Prior art keywords
circuit pattern
substrate
circuit
insulating film
rear surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP189394A
Other languages
Japanese (ja)
Inventor
Daiji Karakado
代治 唐門
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu General Ltd
Original Assignee
Fujitsu General Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu General Ltd filed Critical Fujitsu General Ltd
Priority to JP189394A priority Critical patent/JPH07211994A/en
Publication of JPH07211994A publication Critical patent/JPH07211994A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/368Assembling printed circuits with other printed circuits parallel to each other

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To provide the structure of a surface-mounting hybrid IC which shields a circuit pattern on the rear surface of a ceramic substrate with an insulating film so as to prevent the circuit pattern from coming into contact with a copper foil pattern on one printed wiring board. CONSTITUTION:In a surface-mounting hybrid IC in which a joining surface which joins a circuit and chip element, etc., to each other is formed of a circuit pattern 2 on the front surface of a ceramic substrate 1 and another circuit which is engaged with the circuit is formed of another circuit pattern 3 on the rear surface of the substrate, and then, the front surface of the substrate 1 is coated with a shell 5 and which is provided with a terminal section 4 extended from the circuit on its side face an insulating film 6 is formed on the rear surface of the substrate 1 by applying insulating paste to the rear surface and baking the paste. The insulating film 6 can be formed by sticking and fixed an insulating sheet to the rear surface of the substrate 1. The insulating film 6 can be also formed by applying and fixing an epoxy resin to the rear surface.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は面実装ハイブリッドIC
に係わり、より詳細には外装の絶縁構造に関する。
FIELD OF THE INVENTION The present invention relates to a surface mount hybrid IC.
The present invention relates to an exterior insulating structure in more detail.

【0002】[0002]

【従来の技術】従来の面実装ハイブリッドICに代表さ
れる組立品の構造は、図3の側面図に示すように、例え
ば、セラミック基板21の表面に回路パターン22にて
回路とチップ素子等を接合する接合面を形成し、裏面に
回路パターン23にて前記回路に係合する回路を形成
し、側面に前記両回路から延出して外部に接続する電極
24を備え、前記セラミック基板21の表面の前記回路
に、素材を樹脂系にて底面を開放した箱状のシェル25
を被せ、このシェル25の開口縁を前記セラミック基板
21の表面にエポキシ系の樹脂にて接着することによ
り、前記セラミック基板21の表面の前記回路パターン
22とチップ素子等の装着部品を封止して完成体として
いるのが一般的である。しかしながら、これらの面実装
ハイブリッドICの底面、即ち、前記セラミック基板2
1の裏面に形成された前記回路パターン23は、焼成し
たガラス膜等により保護されているものもあるが、膜厚
も薄く、印刷抵抗を有する場合には、このガラス膜上か
らレーザーによるトリミングを行うため、印刷抵抗の切
断面が露出している。このため、一方の回路を構成した
プリント配線基板26の回路パターン27上に、この面
実装ハイブリッドICを載置して半田リフロー等の組立
工程を経る間に、裏面の前記回路パターン23と表面の
前記回路パターン27との間隙に金属粉等の異物が混入
し、前記回路パターン23の切断面と前記回路パターン
27とをショートすると言う障害を起こすことがある。
また、回路パターン27に微細な突起等があると半田溶
融時に、この突起を介して、前述同様に前記セラミック
基板21の裏面の前記回路パターン23に接触すること
が多々あった。
2. Description of the Related Art As shown in the side view of FIG. 3, the structure of an assembly typified by a conventional surface mount hybrid IC has a circuit pattern 22 on a surface of a ceramic substrate 21, for example, a circuit and a chip element. A bonding surface to be bonded is formed, a circuit that engages with the circuit is formed on the back surface by the circuit pattern 23, and electrodes 24 that extend from both circuits and are connected to the outside are provided on the side surface, and the front surface of the ceramic substrate 21. A box-shaped shell 25 whose bottom is opened with a resin material for the above circuit.
Then, the opening edge of the shell 25 is adhered to the surface of the ceramic substrate 21 with an epoxy resin to seal the circuit pattern 22 on the surface of the ceramic substrate 21 and a mounting component such as a chip element. It is generally done as a completed body. However, the bottom surface of these surface mount hybrid ICs, that is, the ceramic substrate 2
The circuit pattern 23 formed on the back surface of 1 may be protected by a fired glass film or the like, but if the film thickness is thin and printing resistance is present, trimming with a laser is performed on this glass film. Because of this, the cut surface of the printing resistor is exposed. Therefore, while the surface mount hybrid IC is placed on the circuit pattern 27 of the printed wiring board 26 that constitutes one circuit and the assembly process such as solder reflow is performed, Foreign matter such as metal powder may enter the gap between the circuit pattern 27 and short-circuit the cut surface of the circuit pattern 23 and the circuit pattern 27.
In addition, when the circuit pattern 27 has fine protrusions or the like, when the solder melts, the solder often comes into contact with the circuit pattern 23 on the back surface of the ceramic substrate 21 via the protrusions.

【0003】[0003]

【発明が解決しようとする課題】本発明はこのような点
に鑑みなされたもので、面実装ハイブリッドICの底面
の回路パターンを絶縁膜にて遮蔽することにより、一方
のプリント配線基板の回路パターンとの接触を防ぐ面実
装ハイブリッドICを提供するものである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and a circuit pattern on one printed wiring board is formed by shielding the circuit pattern on the bottom surface of the surface mount hybrid IC with an insulating film. The present invention provides a surface mount hybrid IC that prevents contact with the surface mount hybrid IC.

【0004】[0004]

【課題を解決するための手段】本発明は上述の課題を解
決するため、本願第1の発明は、基板両面に回路パター
ンと側面に電極を形成して表面にチップ部品を搭載し、
前記基板の表面をシェルにて被ってなる面実装ハイブリ
ッドICにおいて、前記基板裏面に絶縁膜を形成し、該
絶縁膜にて前記基板裏面の回路パターンと、一方のプリ
ント配線基板の回路パターンとを絶縁してなるなること
を特徴とする。本願第2の発明は、本願第1の発明に係
わり、前記基板裏面に、導電性ペーストを塗着焼成して
なることを特徴とする。本願第3の発明は、本願第1の
発明に係わり、前記基板裏面に、絶縁性シートを貼接し
てしてなることを特徴とする請求項1記載の面実装ハイ
ブリッドIC。本願第4の発明は、本願第1の発明に係
わり、前記基板裏面に、エポキシ樹脂を塗布してなるこ
とを特徴とする。
In order to solve the above-mentioned problems, the first invention of the present application is to form a circuit pattern on both surfaces of a substrate and electrodes on the side surfaces and mount a chip component on the front surface.
In a surface mount hybrid IC in which the front surface of the substrate is covered with a shell, an insulating film is formed on the back surface of the substrate, and the insulating film forms a circuit pattern on the back surface of the substrate and a circuit pattern on one printed wiring board. It is characterized by being insulated. A second invention of the present application relates to the first invention of the present application, characterized in that a conductive paste is applied and baked on the back surface of the substrate. A third invention of the present application relates to the first invention of the present application, wherein the surface mounting hybrid IC according to claim 1, wherein an insulating sheet is attached to the back surface of the substrate. A fourth invention of the present application relates to the first invention of the present application, characterized in that an epoxy resin is applied to the back surface of the substrate.

【0005】[0005]

【作用】以上のように構成したので、本発明による面実
装ハイブリッドICによれば、セラミック基板の裏面の
回路パターン面に、絶縁性を有する絶縁膜が形成され、
この面実装ハイブリッドICを装着する一方のプリント
配線基板上に、この面実装ハイブリッドICの底面を密
接しても、前記セラミック基板の前記回路パターン面と
前記プリント配線基板の回路パターン面との間に、前記
絶縁膜による絶縁層が密接して介在しているので異物が
混入せず、また、前記回路パターンに突起等があって
も、前記絶縁膜により遮られているのでショートするこ
とはない。
With the above-described structure, according to the surface mount hybrid IC of the present invention, an insulating film having an insulating property is formed on the circuit pattern surface on the back surface of the ceramic substrate.
Even if the bottom surface of the surface-mount hybrid IC is brought into close contact with one of the printed wiring boards on which the surface-mount hybrid IC is mounted, the circuit pattern surface of the ceramic substrate and the circuit pattern surface of the printed wiring board are separated from each other. Since the insulating layer formed by the insulating film is closely intervened, no foreign matter is mixed in, and even if there is a protrusion or the like on the circuit pattern, it is blocked by the insulating film and therefore no short circuit occurs.

【0006】[0006]

【実施例】以下、図面に基づいて本発明によるの実施例
を詳細に説明する。図1は面実装ハイブリッドICを示
す底面図で、図2は図1の面実装ハイブリッドICを示
す側断面図である。図において、1はセラミック基板
で、この表面に回路パターン2にて回路とチップ素子等
を接合する接合面を形成し、裏面に回路パターン3にて
前記回路に係合する回路を形成し、側面に前記回路から
延出して外部のプリント配線基板の回路パターンに接続
する電極4が備えられている。5はシェルで、素材を樹
脂材にて底面を開放した箱状に形成し、前記セラミック
基板1の表面に、前記シェル5を被せて底面の開口縁と
前記セラミック基板1の表面とをエポキシ系の樹脂にて
接着することにより、前記セラミック基板1の表面の前
記回路パターン2とチップ素子等の装着部品が封止され
て完成体としている。6は絶縁膜で、前記回路パターン
3の外周の前記電極4の近傍を除いた全面積に、例え
ば、本願第2の特徴とする部分においては、素材を樹脂
系にて構成したマーキングペーストを所要の厚さに印刷
し、焼成(焼成温度約150℃)工程を経て前記回路パ
ターン3面上に膜厚を形成している。
Embodiments of the present invention will be described in detail below with reference to the drawings. 1 is a bottom view showing the surface mount hybrid IC, and FIG. 2 is a side sectional view showing the surface mount hybrid IC of FIG. In the figure, reference numeral 1 is a ceramic substrate, on the surface of which a bonding surface for bonding a circuit and a chip element or the like is formed by a circuit pattern 2, and on the back surface, a circuit for engaging the circuit is formed by a circuit pattern 3 And an electrode 4 extending from the circuit and connected to a circuit pattern of an external printed wiring board. Reference numeral 5 denotes a shell, which is made of a resin material and formed into a box shape having an open bottom surface. The shell 5 is covered on the surface of the ceramic substrate 1 so that the opening edge of the bottom surface and the surface of the ceramic substrate 1 are made of epoxy. The circuit pattern 2 on the surface of the ceramic substrate 1 and the mounting components such as chip elements are sealed by adhering with the resin of FIG. Reference numeral 6 denotes an insulating film, and the entire area of the outer periphery of the circuit pattern 3 excluding the vicinity of the electrode 4 requires, for example, a marking paste composed of a resin material as a material in the second feature of the present application. And the thickness is formed on the surface of the circuit pattern 3 through a firing (firing temperature of about 150 ° C.) step.

【0007】従って、製造工程において、前記プリント
配線基板1の前記回路パターン3上に載置された面実装
ハイブリッドICの底面は、前記絶縁膜6により絶縁さ
れているので、この半田リフロー時等の工程にて金属粉
等の異物が混入しても、この絶縁膜6が遮蔽して前記回
路パターン3に接触することはない。また、この回路パ
ターン3に突起等があっても、前記絶縁膜6に遮られて
双方の基板のパターンの接触は防止される。なお、前記
絶縁膜6の焼成温度を150℃程度に抑えることによ
り、既に前工程にて用いられている物質、即ち、クリー
ム半田(約225℃)およびガラスペースト(約515
℃)の溶融温度に対して影響を与えることはない。本願
第3の特徴とする部分においては、前記セラミック基板
1の裏面の前記回路パターン3面に、例えば、ポリエス
テルを基材としたシートをシリコンゴム系の一定の粘度
を有する接着剤を用いて接着し、このシートに絶縁され
て前述同様の絶縁膜が形成される。本願第4の特徴とす
る部分においては、前記セラミック基板1の裏面の前記
回路パターン3面に、常温にて硬化するエポキシ系樹脂
材を塗布して絶縁膜を形成してもよい。
Therefore, in the manufacturing process, since the bottom surface of the surface mount hybrid IC mounted on the circuit pattern 3 of the printed wiring board 1 is insulated by the insulating film 6, the solder reflow or the like may occur. Even if foreign matter such as metal powder is mixed in the process, the insulating film 6 does not shield and contact the circuit pattern 3. Moreover, even if the circuit pattern 3 has a protrusion or the like, the circuit pattern 3 is blocked by the insulating film 6 to prevent the patterns of both substrates from contacting each other. By controlling the firing temperature of the insulating film 6 to about 150 ° C., the substances already used in the previous step, that is, cream solder (about 225 ° C.) and glass paste (about 515 ° C.) are used.
(.Degree. C.) melting temperature is not affected. In the third characteristic part of the present application, for example, a polyester-based sheet is bonded to the surface of the circuit pattern 3 on the back surface of the ceramic substrate 1 by using a silicone rubber-based adhesive having a constant viscosity. Then, the sheet is insulated and an insulating film similar to the above is formed. In the fourth feature of the present application, an epoxy resin material that cures at room temperature may be applied to the surface of the circuit pattern 3 on the back surface of the ceramic substrate 1 to form an insulating film.

【0008】[0008]

【発明の効果】以上に説明したように、本発明による面
実装ハイブリッドICにおいては、面実装ハイブリッド
ICの底面の回路パターンを絶縁膜にて絶縁することに
より、プリント配線基板の回路パターンとの間の接触が
防止できるもので、よって、プリント配線基板の回路パ
ターン上に微細な突起、若しくは、半田接合時等に金属
粉等の異物が混入しても双方のパターンをショートする
ことはなく、その効果は大である。
As described above, in the surface mount hybrid IC according to the present invention, the circuit pattern on the bottom surface of the surface mount hybrid IC is insulated by the insulating film so that the circuit pattern of the surface mount hybrid IC is separated from the circuit pattern of the printed wiring board. Therefore, even if a fine protrusion on the circuit pattern of the printed wiring board or a foreign substance such as metal powder is mixed in at the time of soldering, both patterns are not short-circuited. The effect is great.

【図面の簡単な説明】[Brief description of drawings]

【図1】図1は本発明に適用した面実装ハイブリッドI
Cを示した底面図である。
FIG. 1 is a surface mount hybrid I applied to the present invention.
It is a bottom view showing C.

【図2】図2は本発明に適用した面実装ハイブリッドI
Cを示した側断面図である。
FIG. 2 is a surface mount hybrid I applied to the present invention.
It is a side sectional view showing C.

【図3】図3は従来の面実装ハイブリッドICを示した
側断面図である。
FIG. 3 is a side sectional view showing a conventional surface mount hybrid IC.

【符号の説明】[Explanation of symbols]

1 セラミック基板 2 回路パターン 3 回路パターン 4 電極 5 シェル 6 絶縁膜 1 Ceramic substrate 2 Circuit pattern 3 Circuit pattern 4 Electrode 5 Shell 6 Insulating film

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 基板両面に回路パターンと側面に電極を
形成して表面にチップ部品を搭載し、前記基板の表面を
シェルにて被ってなる面実装ハイブリッドICにおい
て、前記基板裏面に絶縁膜を形成し、該絶縁膜にて前記
基板裏面の回路パターンと、一方のプリント配線基板の
回路パターンとを絶縁してなるなることを特徴とする面
実装ハイブリッドIC。
1. A surface mount hybrid IC comprising a circuit pattern formed on both sides of a substrate and electrodes formed on the sides thereof, chip components mounted on the front side, and a shell covering the front side of the substrate to form an insulating film on the back side of the substrate. A surface mount hybrid IC, which is formed by insulating the circuit pattern on the back surface of the substrate from the circuit pattern on one printed wiring board by the insulating film.
【請求項2】 前記基板裏面に、導電性ペーストを塗着
焼成してなることを特徴とする請求項1記載の面実装ハ
イブリッドIC。
2. The surface mount hybrid IC according to claim 1, wherein a conductive paste is applied and baked on the back surface of the substrate.
【請求項3】 前記基板裏面に、絶縁性シートを貼接し
てしてなることを特徴とする請求項1記載の面実装ハイ
ブリッドIC。
3. The surface mount hybrid IC according to claim 1, wherein an insulating sheet is attached to the back surface of the substrate.
【請求項4】 前記基板裏面に、エポキシ樹脂を塗布し
てなることを特徴とする請求項1記載の面実装ハイブリ
ッドIC。
4. The surface mount hybrid IC according to claim 1, wherein an epoxy resin is applied to the back surface of the substrate.
JP189394A 1994-01-13 1994-01-13 Surface-mounting hybrid ic Pending JPH07211994A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP189394A JPH07211994A (en) 1994-01-13 1994-01-13 Surface-mounting hybrid ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP189394A JPH07211994A (en) 1994-01-13 1994-01-13 Surface-mounting hybrid ic

Publications (1)

Publication Number Publication Date
JPH07211994A true JPH07211994A (en) 1995-08-11

Family

ID=11514269

Family Applications (1)

Application Number Title Priority Date Filing Date
JP189394A Pending JPH07211994A (en) 1994-01-13 1994-01-13 Surface-mounting hybrid ic

Country Status (1)

Country Link
JP (1) JPH07211994A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009000978A (en) * 2007-06-25 2009-01-08 Brother Ind Ltd Droplet discharge device
CN103442516A (en) * 2013-08-16 2013-12-11 沪士电子股份有限公司 Method for achieving insulation protection between printed circuit board plug-in holes

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009000978A (en) * 2007-06-25 2009-01-08 Brother Ind Ltd Droplet discharge device
CN103442516A (en) * 2013-08-16 2013-12-11 沪士电子股份有限公司 Method for achieving insulation protection between printed circuit board plug-in holes

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