JPH07211809A - Semiconductor nonvolatile storage device and its manufacture - Google Patents

Abstract

PURPOSE:To realize a semiconductor nonvolatile storage device and its manufacturing method wherein the increase of a voltage necessary for writing and the irregularity of data writing characteristics can be restrained, the influence upon data writing characteristics which is caused by the deterioration of a gate insulating film as the result of repeated operation is little, and reliability can be improved. CONSTITUTION:In a DINOR type semiconductor nonvolatile storage device, the structure of a drain diffusion layer 3a is constituted as an so-called asymmetric memory cell wherein the overlap part with a floating gate 5 is larger than the structure of a source diffusion layer 2, and the diffusion concentration of the part is set high. Thereby the stretch of the diffusion layer from the source side can be restrained, and the enlargement of short channel phenomenon can be restricted only in the drain side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile memory, for example, a semiconductor nonvolatile memory device such as a flash EEPROM and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a NOR type flash EEPROM, a bit line is divided into a main bit line and a sub bit line,
A DIN having a structure in which one selection transistor is arranged between them
OR (DIvided bit line NOR) type flash EEPROM
Is proposed. This DINOR type flash EEP
In case of ROM, both write / erase operations are performed by FN (Fowler-
Since it is performed by the Nordheim) tunneling, the current consumption is lower than that of the operation of the NOR flash EEPROM of the channel hot electron (CHE) / FN system, and thus it is suitable for lowering the voltage.

FIG. 15 shows a DINOR type flash EEP of, for example, one bit line and one sub bit line portion when eight bits are divided into sub bit lines in units of the bit line direction.
It is a figure which shows the memory array of ROM. In addition, FIG.
15 is a diagram showing a memory array pattern. The memory array of FIG. 15 is the memory transistor 8 surrounded by a broken line in FIG.
And one selection transistor. 15 and 16, SWL is a selected word line, WL1 to W
L8 is a word line, MBL is a main bit line, SBL is a sub bit line, SRL is a source line, ST is a selection transistor, MT1 to MT8 are memory transistors, and CNT _MBL.
Indicates a main bit line contact, CNT _SBL indicates a sub bit line contact, and LCS indicates an element isolation region.

This memory cell, as shown in FIG.
The sub-bit line SBL is branched from the main bit line MBL, and a plurality of memory transistors are arranged in parallel on each of the branched sub-bit lines SBL via the select transistor ST.

FIG. 17 shows a DINOR type flash EEP.
It is sectional drawing which shows the cell structure example of ROM. In FIG. 17, 1 is a substrate, 2 is a source diffusion layer, 3 is a drain diffusion layer, 4 is a gate insulating film, 5 is a floating gate, and 6
Is a poly-poly interlayer insulating film, and 7 is a control gate. Generally, in the DINOR type memory cell, as shown in FIG. 17, the source diffusion layer 2 and the drain diffusion layer 3 have a symmetrical structure including the diffusion concentration and are substantially equal to the floating gate 5. It is configured to overlap.

In the DINOR type flash EEPROM having such a structure, erase, write and read operations by FN tunneling are performed as follows.

First, at the time of erasing, the selected word line SWL is set to 0 V to turn off the selection transistor ST,
The drain connected to the bit line BL is set to the floating state. Then, set the word line WL to 10V to 20V.
Electrons are injected into the floating gate 5 by biasing the common source line SRL and the substrate to about −5V to 6V. as a result,
The threshold voltage V _TH of the memory transistor MT is 5V to
The voltage becomes 6 V or more, and the device is turned off.

At the time of writing, the selected word line SWL is set to 1
The selection transistor ST is turned on by setting it to 0V to 15V, and the common source line SRL is set to a floating state. Subsequently, the word line WL is set to -10V
When biased to about 15 V and writing "1" data, about 5 V to 6 V is applied to the bit line BL (drain),
When writing “0” data, 0 V is applied to the bit line BL (drain). As a result, the electrons in the floating gate 5 are extracted from the drain only when "1" data is written, and the threshold voltage V _TH of the memory transistor MT drops to about 1V to 2V.

At the time of reading, the selected word line SWL is set to 3
When the selection transistor ST is turned on by setting V to 5V, then the word line WL is applied to about 3V to 5V and the bit line (drain) is applied to about 1 to 2V, and sufficient current flows in the bit line. Is determined to be "1" data, and if no flow is determined to be "0" data.

Incidentally, FIG. 18 shows the set voltage in each of the erase, write and read operations of the DINOR type flash EEPROM described above.

[0011]

However, in the above-mentioned conventional symmetrical memory cell, from the viewpoint of prevention of the short channel phenomenon, the overlap portion between the source / drain and the floating gate is large and the diffusion concentration is large. It is extremely difficult to set it high. Therefore, at the time of data writing, not only the required voltage at the time of data writing becomes high due to the influence of the depletion layer of the drain diffusion layer, but also the characteristic variation becomes large, and further, as shown in FIG. While repeating, the electron trap ET and the interface resistance IV are generated, and thus, there is a problem that the gate insulating film is easily affected and deterioration in reliability occurs.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to suppress an increase in voltage required for writing and variations in characteristics of data writing, and to write data due to deterioration of a gate insulating film due to repeated operation. It is an object of the present invention to provide a semiconductor non-volatile memory device which has a small influence on characteristics and can improve reliability and a manufacturing method thereof.

[0013]

In order to achieve the above object, in a DINOR type semiconductor nonvolatile memory device for writing and erasing data by FN tunneling of the present invention, source and drain diffusion structures are asymmetrically configured. There is.

In the semiconductor nonvolatile device of the present invention, the diffusion structure of one of the source and the drain has a larger overlap with the floating gate than the other diffusion structure, and the diffusion concentration at that portion is large. It is set high.

The semiconductor nonvolatile device of the present invention has means for switching the source and drain between the write / erase operation and the read operation.

In the method of manufacturing a DINOR type semiconductor nonvolatile memory device of the present invention, when the source diffusion layer and the drain diffusion layer are formed, the source diffusion layer and the drain diffusion layer are formed by ion implantation and then the source diffusion layer is formed. Additional ion implantation is performed to either one of the diffusion layer and the drain diffusion layer to set one diffusion concentration higher than the other diffusion concentration.

Further, in the method for manufacturing a DINOR type semiconductor nonvolatile memory device of the present invention, when forming the source diffusion layer and the drain diffusion layer, the source diffusion is made so that the diffusion concentration of one becomes higher than the diffusion concentration of the other. Ion implantation is performed in separate steps for the layer and the drain diffusion layer.

[0018]

According to the semiconductor nonvolatile memory device of the present invention, the extension of the diffusion layer from the source side or the drain side can be suppressed, and the increase of the short channel phenomenon can be limited to only the drain side or the source side.

According to the method of manufacturing the semiconductor nonvolatile memory device of the present invention, when forming the source diffusion layer and the drain diffusion layer, first, in the same step, the source diffusion layer and the drain diffusion layer are formed by ion implantation. It Then, additional ion implantation to either one of the source diffusion layer and the drain diffusion layer, for example, the drain diffusion layer, is performed by high concentration or oblique ion implantation, and the diffusion concentration of the drain is set higher than the diffusion concentration of the source.

Further, according to the method for manufacturing a semiconductor nonvolatile memory device of the present invention, when forming the source diffusion layer and the drain diffusion layer, ion implantation is performed in separate steps. Then, for example, the ion implantation on the drain side is performed by high-concentration or oblique ion implantation rather than the ion implantation on the source side, and the diffusion concentration of the drain is set higher than the diffusion concentration of the source.

[0021]

1 is a sectional view of a cell showing an embodiment of a DINOR type flash EEPROM according to the present invention.
The same components as those in FIG. 17 showing the conventional example are represented by the same reference numerals. That is, 1 is a silicon substrate, 2 is a source diffusion layer, 3a is a drain diffusion layer, 4 is a gate insulating film, 5 is a floating gate, 6 is a Poly-Poly interlayer insulating film, and 7 is a control gate.

In this memory cell, the structure of the drain diffusion layer 3a has a larger overlapping portion with the floating gate 5 than the structure of the source diffusion layer 2, and the diffusion concentration in that portion is set to be high, that is, so-called. It is configured as an asymmetric memory cell.

In the DINOR type memory cell having the above-mentioned structure, the extension of the diffusion layer from the source side is suppressed,
The increase of the short channel phenomenon can be limited to only the drain side.
As a result, the increase in the voltage required for data writing due to the spread of the drain depletion layer is prevented, the variation in the data writing characteristic is reduced, and further, the reliability is deteriorated due to the deterioration of the gate insulating film 4 which occurs during the repeated data writing operation. It becomes possible to prevent it.

Next, referring to FIG. 2 to FIG.
A method of manufacturing the DINOR type flash EEPROM will be described. 2 to 13 correspond to cross-sectional views taken along the line AA in the layout pattern diagram of FIG. 15, respectively.

First, as shown in FIG. 2, a silicon substrate 1
After forming the gate insulating film 4 having a thickness of 10 to 11 nm on the
A first polysilicon layer 51 to be a floating gate having a thickness of about 100 to 200 nm is formed by the CVD method.

Next, as shown in FIG. 3, after the first polysilicon layer 51 to be the selection transistor ST portion is selectively removed, a portion between the floating gate and the control gate is removed.
An ONO laminated oxide film 61 for a Poly-Poly interlayer insulating film is formed. This ONO laminated oxide film 61 is formed as follows, for example. First, a thermal oxide film of about 14 nm is formed by thermal oxidation of the first polysilicon. Next, 11n
A Si ₃ N ₄ film of about m is formed by the CVD method. Finally, a thermal oxide film of about 2 nm is formed on the Si ₃ N ₄ film by thermal oxidation. The film thickness of the ONO laminated oxide film 61 thus formed is about 22 nm in terms of SiO ₂ .

Next, as shown in FIG. 4, the ONO laminated oxide film 61 in the selection transistor portion is selectively removed. Next, as shown in FIG. 5, the gate insulating film 41 of the select transistor portion is formed by thermal oxidation. This gate insulating film 4
Since No. 1 has a high breakdown voltage specification, it is formed to have a film thickness of, for example, about 30 nm.

Next, as shown in FIG. 6, a second control gate 7 having a thickness of about 200 nm is formed by the CVD method.
A polysilicon layer 71 is formed. Next, as shown in FIG. 7, the first polysilicon layer 51 and the second polysilicon layer 7
1. The ONO laminated oxide film 61 is processed and etched to select transistors ST and memory transistors MT1 to MT8.
To form. This processing is carried out by self-alignment like a general EPROM.

Next, as shown in FIG. 8, an asymmetric type source diffusion layer 2 and drain diffusion layer 3a are formed. Specific methods for forming the asymmetrical source / drain diffusion layers 2 and 3a include, for example, two methods shown in FIGS. 9 and 10.

In the method shown in FIG. 9, first, as shown in (A)
Thus, common ion implantation is performed on the source / drain.
This implanter is an overlay with the floating gate.
So that the pop-up part does not become large, for example Phos⁺I
ON, 40keV, 1E14cm^-2, With injection angle 7 °
U Next, as shown in FIG. 9B, at least the source
With only the drain part covered with the resist PR,
Perform on injection. This implant is a floating game
Has a large overlap and a large diffusion concentration.
So, for example Phos⁺Ion 40 keV, 5
E15 cm ^-2, Large injection angle 30 °.

In the method of FIG. 10, the source / drain
Ion implantation is performed separately. First, shown in FIG.
As shown in FIG.
Ions are implanted into the source while being covered with. This inn
The plastic has a large overlap with the floating gate.
Be careful not to become strict, for example Phos⁺40 ions
keV, 1E14cm^-2, The implantation angle is 7 °. Next, the figure
As shown in FIG. 9 (B), only the drain portion is ion-implanted.
To do. This implanter is used with floating gates.
So that the burlap is large and the diffusion density is large,
For example Phos⁺Ion at 40 keV, 5E15c
m ^-2, Large injection angle 30 °.

Next, as shown in FIG. 11, after forming the first interlayer insulating film 8 to a thickness of 200 nm to 300 nm, a contact hole CNH _SBL for connecting the sub bit line and the diffusion layer is formed. Next, as shown in FIG. 12, the third polysilicon layer 9 as a sub bit line is formed to a thickness of 200 nm by the CVD method.
After forming approximately, patterning is performed. Next, as shown in FIG. 13, the second interlayer insulating film 10 is formed to a thickness of 200 nm to 300 n.
After m is formed, a contact hole CNH _MBL for connecting the main bit line and the sub bit is formed. Then, after forming the aluminum (Al) wiring 11 for the main bit line by the sputtering method, patterning processing is performed.

As described above, according to this embodiment,
In the DINOR type flash EEPROM, the source / drain diffusion structure is made asymmetric, the overlap portion with the floating gate is made larger on the drain side than on the source side, and the diffusion concentration thereof is set higher, so that at the time of data writing. The spread of the depletion layer of the drain diffusion layer can be suppressed, and the increase in the voltage required for writing can be suppressed. Further, it is possible to suppress variations in characteristics of writing data. Further, the deterioration of the gate insulating film due to the repeated operation has little influence on the data writing characteristics, and the reliability can be improved.

In the above-described embodiment, FIG.
In the cell structure based on the DINOR type flash EEPROM shown in FIG. 3, the drain diffusion layer 3a has an overlapping portion with the floating gate 5 and a diffusion concentration set to be larger and higher than the source diffusion layer 2 and the drain diffusion at the time of data writing. Although the expansion of the depletion layer of the layer 3a is suppressed, for example, as shown in FIG. 14, a selection transistor ST2 is provided between the main bit line MBL and the source line SRL to perform write / erase operation and read operation. It is also possible to switch the source and drain. In this configuration, the overlap portion of the source diffusion layer with the floating gate 5 and the diffusion concentration are set to be larger and higher than those of the drain diffusion layer. Also in this case, the same effect as that of the above-described configuration of FIG. 1 can be obtained.

[0035]

As described above, according to the present invention,
At the time of data writing, it is possible to suppress the expansion of the depletion layer of the drain diffusion layer and suppress an increase in the voltage required for writing. It is possible to suppress variations in data writing characteristics. The deterioration of the gate insulating film due to the repeated operation has little influence on the data writing characteristics, and the reliability can be improved.

[Brief description of drawings]

FIG. 1 is a DINOR type flash EEPR according to the present invention.
It is a memory cell sectional view showing one example of OM.

FIG. 2 is a DINOR type flash EEPR according to the present invention.
FIG. 9 is a diagram for explaining the manufacturing method of the OM, and is a diagram for explaining the step of forming the gate insulating film and the first polysilicon layer.

FIG. 3 is a DINOR type flash EEPR according to the present invention.
6A and 6B are diagrams for explaining the method of manufacturing the OM, which are diagrams for explaining a selective removal step of the first polysilicon layer to be the selection transistor section and a step of forming an ONO laminated oxide film for the Poly-Poly interlayer insulating film. Is.

FIG. 4 is a DINOR type flash EEPR according to the present invention.
FIG. 9 is a diagram for explaining the manufacturing method of the OM, and is a diagram for explaining a step of selectively removing the ONO laminated oxide film in the selection transistor portion.

FIG. 5 is a DINOR type flash EEPR according to the present invention.
FIG. 6A is a diagram for explaining the manufacturing method of the OM and also a diagram for explaining the step of forming the gate insulating film of the select transistor portion.

FIG. 6 is a DINOR type flash EEPR according to the present invention.
It is a figure for demonstrating the manufacturing method of OM, and is a figure for demonstrating the formation process of a 2nd polysilicon layer.

FIG. 7 is a DINOR type flash EEPR according to the present invention.
FIG. 9 is a diagram for explaining the manufacturing method of the OM, and is a diagram for explaining the process etching step of the first polysilicon layer, the second polysilicon layer, and the ONO laminated oxide film for forming the select transistor and the memory transistor. .

FIG. 8 is a DINOR type flash EEPR according to the present invention.
FIG. 9 is a diagram for explaining the manufacturing method of the OM and also a diagram for explaining a step of forming an asymmetrical source / drain diffusion layer.

FIG. 9 is a diagram for explaining a first method of forming an asymmetric type source / drain diffusion layer, in which (A) is a source / drain diffusion layer;
The figure for demonstrating a drain ion implantation process, (B)
FIG. 7 is a diagram for explaining an additional ion implantation process for the drain.

10A and 10B are diagrams for explaining a second method of forming an asymmetric type source / drain diffusion layer, wherein FIG. 10A is a diagram for explaining a source / ion implantation step, and FIG. It is a figure for demonstrating an ion implantation process.

FIG. 11 is a DINOR type flash EEP according to the present invention.
FIG. 9 is a diagram for explaining the method for manufacturing the ROM, which is a diagram for explaining a step of forming a contact hole for connection between the first interlayer insulating film and the sub bit line and the diffusion layer.

FIG. 12 is a DINOR type flash EEP according to the present invention.
FIG. 9 is a diagram for illustrating the method for manufacturing the ROM, which is a diagram for describing the step of forming the third polysilicon layer and the step of patterning.

FIG. 13 is a DINOR flash EEP according to the present invention.
FIG. 6 is a diagram for explaining the method of manufacturing the ROM, including a step of forming a second interlayer insulating film, a step of forming a contact hole for connecting the main bit line and the sub bit, and a step of forming and processing an aluminum wiring for the main bit line. It is a figure for explaining a process.

FIG. 14 is a diagram showing another memory array configuration of the DINOR type flash EEPROM.

FIG. 15 is a diagram showing a memory array configuration of a DINOR type flash EEPROM of one bit line and one sub bit line portion when sub-bit lines are divided into units of 8 bits in the bit line direction.

FIG. 16 is a diagram showing a memory array pattern of a DINOR type flash EEPROM.

FIG. 17 is a conventional DINOR type flash EEPROM.
3 is a cross-sectional view showing an example of the cell structure of FIG.

FIG. 18 is a diagram showing set voltages at each operation of erasing, writing, and reading of the DINOR type flash EEPROM.

FIG. 19 is a diagram for explaining a deterioration phenomenon in the vicinity of a drain end due to a data write operation in a conventional memory cell.

[Explanation of symbols]

 1 ... Silicon substrate 2 ... Source diffusion layer 3a ... Drain diffusion layer 4 ... Gate insulating film 5 ... Floating gate 6 ... Poly-Poly interlayer insulating film 7 ... Control gate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/115

Claims (5)

[Claims] 1. A DINOR type semiconductor nonvolatile memory device for writing and erasing data by FN tunneling, wherein the source and drain diffusion structures are asymmetrical. 2. The diffusion structure of one of the source and the drain has a larger overlapping portion with the floating gate than the other diffusion structure, and the diffusion concentration in that portion is set to be higher. 1. The semiconductor nonvolatile memory device according to 1. 3. The semiconductor non-volatile memory device according to claim 1, further comprising means for switching a source and a drain between a write / erase operation and a read operation. 4. A method of manufacturing a DINOR type semiconductor non-volatile memory device, comprising: forming a source diffusion layer and a drain diffusion layer,
After forming the source diffusion layer and the drain diffusion layer by ion implantation, additional ion implantation is performed to either one of the source diffusion layer and the drain diffusion layer, and one diffusion concentration is made higher than the other diffusion concentration. Method of manufacturing a semiconductor nonvolatile memory device to be set. 5. A method of manufacturing a DINOR type semiconductor nonvolatile memory device, comprising: forming a source diffusion layer and a drain diffusion layer,
So that the diffusion concentration of one is higher than the diffusion concentration of the other,
A method for manufacturing a semiconductor nonvolatile memory device, wherein ion implantation is performed in separate steps in a source diffusion layer and a drain diffusion layer.