JP2001308209A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly integrated NAND cell type EEPROM, substantially eliminating a space for a selective transistor. SOLUTION: In the NAND cell type EEPROM which consists of multiple NAND cells, each NAND cell has multiple memory cells stacked on a p-wall 2 which is formed on an n-type Si substrate 1. A memory cell consists of a floating gate 4 and a control gate 6, and allows writing and erasing by exchanging electric charges between them. Each NAND cell is connected to a bit wire 13 through a selective transistor. A selective transistor is made with TFT, making a thin film Si layer 9 formed on a NAND cell a channel section.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device in which a plurality of memory cells having a MOS transistor structure are connected to form a memory cell unit.

[0002]

2. Description of the Related Art In recent years, as a nonvolatile semiconductor memory (EEPROM) which is electrically rewritable and can be highly integrated, a plurality of memory cells are formed as one unit, and a data line is connected to the memory cell. An EEPROM having a structure that achieves high integration by reducing the number of contacts is known. For example, a NAND circuit connected in series with a plurality of memory cells
What constitutes a cell is known. FIG. 12 is a plan view showing one NAND cell of this type of EEPROM, and FIGS. 13 (a) and 13 (b) are arrows AA 'and BB'.
It is sectional drawing.

In a p-type silicon substrate (or a wafer in which a p-type well is formed in an n-type silicon substrate) 81, eight memory cells M1 to M8 and two select transistors S1 are provided in a region surrounded by an isolation insulating film 82. , S2 are arrayed. As a memory cell constituting a NAND cell, a floating gate 84 (8) of a first-layer polycrystalline silicon film is formed on a substrate 81 via a first gate insulating film 83.
4 _1, 84 _2, ...) are formed, and further the second layer polycrystalline silicon film by the control gate 86 via a second gate insulating film 85 (86 _1, 86 _2, ...) are formed.

[0004] The gate insulating film of the select transistors S1, S2 are formed simultaneously with the second gate insulating film 85, their gate electrodes 88 _1, 88 ₂ are formed simultaneously with the control gate 86. The control gate 86 of each memory cell is formed continuously in the row direction to form a word line. An n-type diffusion layer 87 serving as a source / drain is formed between the memory cells, and the source / drain is connected in series so that adjacent ones share the source / drain to form a NAND cell.

The writing and erasing operations of this NAND cell type EEPROM are performed by transferring charges by a tunnel current between the substrate 21 and the floating gate 84. And
Such a NAND cell type EEPROM uses a conventional NO
Compared with the R type, there is an advantage that the number of contacts is greatly reduced and high integration is possible.

However, if this type of EEPROM is to be further integrated, there are the following problems to be solved. That is, the area occupied by portions other than the memory cells, particularly, the area occupied by the select transistors S1 and S2 must be reduced. In the case of a NAND cell, the selection transistor S
1 and S2 are indispensable for securing the selectivity with the adjacent NAND cell.

[0007]

As described above, in the conventional nonvolatile semiconductor memory device, the area occupied by the select transistor cannot be reduced, which is a factor that hinders further high integration. Was.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to substantially eliminate an area occupied by a select transistor and to realize a non-volatile memory capable of higher integration. Another object of the present invention is to provide a nonvolatile semiconductor memory device.

[0009]

(Structure) The gist of the present invention is that a selection transistor connected to a memory cell unit is formed as a thin film transistor (TFT) on the memory cell unit.

That is, the present invention provides a memory cell comprising a plurality of memory cells in which a charge storage layer and a control gate are stacked on a semiconductor substrate and writing and erasing are performed by transferring charges between the charge storage layer and the substrate. Multiple units are arranged,
In a nonvolatile semiconductor memory device in which each memory cell unit is connected to a data line via a selection transistor, the selection transistor is formed by a thin film transistor having a thin film semiconductor layer formed on the memory cell unit as a channel portion. It is characterized by becoming.

Here, preferred embodiments of the present invention include the following.

(1) The memory cell unit is a NAND cell in which a plurality of memory cells are connected in series.

(2) A contact portion for connecting a drain-side select transistor of a memory cell unit to a data line (bit line) is shifted by an adjacent bit line.

(3) Adjacent memory cell units are connected to the same data line via different selection transistors, and one of the selection transistors connected to the data line is turned on to turn on one of the adjacent memory cell units. Select and operate.

(4) The drain side of the memory cell unit is connected to a data line via a selection transistor, and the source side is connected to an adjacent data line via another selection transistor. More specifically, a plurality of memory cell units are connected in series, each connection point is connected to a data line via a selection transistor, and each memory cell unit has one of the data lines as a bit line and the other as a source line. Be driven as

(Operation) According to the present invention, since the select transistor composed of the TFT is formed above the memory cell unit, the area occupied by the select transistor portion can be substantially eliminated, and the integration degree is correspondingly reduced. Is improved. Further, when forming a memory cell unit, it is not necessary to form two types of a gate insulating film, that is, a selection transistor portion and a memory cell portion, and only one type of a memory cell portion is required. In addition, since the select transistor is provided on the memory cell unit, the degree of freedom in array connection is increased, and for example, advantages such as elimination of a source line and substitution of an adjacent bit line are generated, and high performance can be achieved. Become.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments.

(First Embodiment) FIG. 1 is a plan view showing a schematic configuration of a NAND cell type EEPROM according to a first embodiment of the present invention, and FIG. 2 is a sectional view taken along the line AA 'of FIG. is there.

A p-well 2 is formed on an n-type Si substrate 1, and element regions 15 and element isolation regions 16 are alternately arranged in a stripe pattern on the p-well 2. On the p-well 2, a floating gate (charge storage layer) 4 is formed via a first gate insulating film 3 so as to be orthogonal to the device region 15 and the device isolation region 16. A control gate 6 is formed through the gate.

Then, by forming an n ⁺ layer 7 in the p well 2 by impurity diffusion using the control gate 6 as a mask,
A memory cell having a MOS transistor structure is formed. The memory cells are connected in series to form a NAND cell.

On the substrate on which the NAND cell is formed, the first
Is deposited, for example, the control gate 5
Contact holes 8a are formed in every eight element regions. An amorphous or polycrystalline silicon film 9 is deposited on the insulating film 8, the silicon film 9 is processed into a predetermined shape, and a part thereof is connected to the n ⁺ diffusion layer 7. A gate electrode (selection gate) 11 is formed on a part of the silicon film 9 with a gate insulating film 10 interposed therebetween. For example, As is ion-implanted into the silicon film 9 using the gate electrode 11 as a mask. Thus, a selection transistor including a TFT (Thin Film Transistor) having 9a as a channel and 9b and 9c as a source / drain is configured.

A second interlayer insulating film 12 is deposited on the substrate on which the select transistor is formed, and a contact hole 12a for connecting the drain 9c of the select transistor and the bit line is formed in the second interlayer insulating film 12. Then, the bit line 13 is deposited on the insulating film 12. This gives T
The drain 9c of the selection transistor made of FT is connected to the bit line 13, and the source 9b is connected to the drain side of the NAND cell.

In the selection transistor connected to the source side, 9b2 is connected to 7 via 8a, and 9c2 is connected to an adjacent 9c2 to become a source line.

FIG. 3 shows an equivalent circuit of the cell array shown in FIGS. 1 and 2, and FIG. 4 shows an example of the cell array arrangement. For two NAND cells, there is one drain-side selection transistor (connected to the selection gate SGD) and one source-side selection transistor (connected to the selection gate SGS), and each selection transistor is used in common by the two NAND cells. Can be Specifically, a plurality of NAND cells are connected in series, and a selection transistor is provided at the connection point. The element region (n ⁺ layer) on the substrate is electrically connected in one block by a plurality of NAND cells, and the block is separated by separating the element region.

The following (Table 1) shows the operation of this embodiment.
Note that writing and erasing operations of the NAND cell type EEPROM are performed by transferring charges by a tunnel current between the substrate 1 and the floating gate 3.

[0026]

[Table 1]

For erasing, as in the normal NAND cell operation, a high potential Vpp is applied to a p-well or the like, the control gate CG is set to 0 V, and charges in the floating gate are released to the substrate. The control gate CG of the cell not to be erased is set to Vpp.
Prevent charge release. At the time of erasing, the selection gate SG is set to 0 V, the bit line BL is set to about 0 V to VM, or the selection gate SG is set to Vpp.
Although the bit line BL may be set at about Vpp, the selection gate SG is set to 0 V, and the bit line BL is set to 0 V or VM.
In this case, since Vpp is not applied to the transistor of the bit line decoder (column decoder), a transistor with a high breakdown voltage is not required. For this reason, the bit line decoder can be composed of only low-voltage transistors, resulting in a significant area reduction.

As a method of batch erasing, the control gate CG and the selection gate SG of all the memory cells are set to 0 V, and the bit lines BL,
High potential Vpp is applied to the common source line of the NAND cell and the substrate. As a result, electrons are emitted from the floating gate to the substrate in all the memory cells, and a state “0” in which the threshold value moves in the negative direction is obtained.

Writing is performed in the same manner as in the operation of a normal NAND cell. Writing is performed sequentially from the memory cell M8 on the source side. First, the common source and the source side select gate SGS are grounded, and the control gate CG of the memory cell M8 is turned on.
And the intermediate potential VM is applied to the remaining control gate CG and the drain side select gate SGD. This allows
The potential (0 V) of the bit line BL is transmitted to the drain of the memory cell M8. In this memory cell M8, electrons are injected from the drain diffusion layer into the floating gate, and the threshold value moves in the positive direction. That is, "1" is written. Hereinafter, data writing is performed in the order of the memory cells M7, M6,.

However, VM is applied to the control gate CG of the non-selected NAND in the selected block. This is because the voltage applied to the bit line BL is applied to the n ⁺ layer in the same block. In addition, non-selection N in the selected block
Although the SGD of AND is set to 0 V, the voltage of VM may be applied to surely determine the diffusion layer voltage (the same potential as the selected NAND).

Reading is performed in the same manner as a normal NAND cell. That is, the control is performed by grounding the control gate CG and the common source line of the selected memory cell, applying a power supply potential to the remaining control gates and the select gates, and detecting the presence or absence of a current.

As described above, according to the present embodiment, the NAND
Since the selection transistor for connecting the cell to the bit line and the source line is formed as a TFT on the NAND cell, the following effects can be obtained.

(1) The area occupied by the select transistor section is substantially eliminated, and the memory cell array can be reduced.

(2) The gate insulating film in the memory cell array becomes only the tunnel oxide film of the memory cell, and it is not necessary to separately form the gate insulating film from the select transistor. Therefore, the number of steps can be reduced.

(3) When the selection transistor is formed of two layers of polysilicon, a step for making contact with the first layer of polysilicon is required, but this step can be omitted.

(4) The area of the column decoder can be greatly reduced.

(5) Since the selection transistor is a TFT, the substrate bias effect is eliminated, the drive capability is increased, the VM voltage is reduced, and the reading speed is increased.

As a modification of the present embodiment, a configuration as shown in FIG. 5 may be used. This is because, as a conventional selection transistor on the source side of the NAND cell, M
An OS transistor is used, and only a TFT on the drain side uses a TFT. In this case, although the effect of reducing the area of the memory cell array is reduced by half, the diffusion layers can be separated even in the same block.

(Second Embodiment) FIG. 6 is a plan view showing a schematic configuration of a NAND cell type EEPROM according to a second embodiment of the present invention, and FIG. 7 is an equivalent circuit diagram thereof. In addition,
The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, the basic configuration is the same as that of the first embodiment, but the position of the bit line contact of the selection transistor is shifted between adjacent bit lines. That is, the silicon films on the bit line contact side are alternately formed above and below the substrate contact.

The operation of this embodiment can be performed in the same manner as in the first embodiment. However, by shifting the position of the bit line contact as described above, the margin for forming the Si film, the margin for the bit line contact portion, etc. are reduced. There are advantages that can be done.

As shown in Table 2 below, SGD1 and SGD2 can be set to VH and 0V, respectively, at the time of writing. In the cell connected to the source side of SGD2, the diffusion layer floats and is not written. By doing so, only half the cells connected to one word line can be written, and the page size and block size can be reduced.

[0043]

[Table 2]

Also in the present embodiment, as shown in FIG. 5, it is possible to use a MOS transistor on the substrate as a conventional selection transistor on the source side and use a TFT only for the selection transistor on the drain side.

(Third Embodiment) FIG. 8 is a plan view showing a schematic configuration of a NAND cell type EEPROM according to a third embodiment of the present invention, and FIG. 9 is an equivalent circuit diagram thereof. In addition,
The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The selection transistor on the source side is the same as in the first embodiment. The drain-side select transistor is the same as that of the second embodiment, but the bit line connection method is different. In other words, the bit line connects two adjacent NAND cells in common, and by selecting one of the selection gates SGD1 and SGD2, one of the NAND cells can be selected. The operation of this embodiment is as shown in (Table 3) below.

[0047]

[Table 3]

In this embodiment, not only the same effects as in the first embodiment can be obtained, but also by improving the connection method of the bit lines, the design margin of the bit lines is increased, and the capacitance between the bit lines is also increased. There is an advantage of being reduced.

(Embodiment 4) FIG. 10 is an equivalent circuit diagram showing a schematic configuration of a NAND cell type EEPROM according to a fourth embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, the source line is eliminated and a bit line is used instead. That is, the drain side and the source side of the NAND cell are all connected to the bit line via the selection transistor. Then, select transistors (eg, SGa2, SGb2) adjacent to each other are simultaneously turned on.
For example, when reading out a cell indicated by a circle in FIG. 10, when SGb2 is ON, SGa2 is OFF and at the same time, SGa3 is ON and the current is changed from BL2 to BL2.
1, or flows from BL4 to BL3. in this way,
Adjacent BLs serve as BLs and source lines.

The operation of this embodiment is as shown in the following (Table 4). Sector erasure and partial erasure can be performed using CG21-C
This is a case where the cell connected to G28 is erased.

[0052]

[Table 4]

In this case, the case where erasing is performed by applying Vpp to the well has been described, but a method of applying Vpp to the drain may be used. Alternatively, a method of writing by hot electrons may be used.

(Embodiment 5) FIG. 11 is an equivalent circuit diagram showing a schematic configuration of a NAND cell type EEPROM according to a fifth embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

This embodiment differs from the fourth embodiment in that adjacent BLs are connected in a complementary manner. That is, the selection transistors connected to SG22 and SG32 are turned on at the same time, and the cell marked with ○ is read, the selection transistors connected to SG21 and SG31 are turned on, and the cell marked with △ can be read. The bit lines play the role of source lines.

The present invention is not limited to the embodiments described above. In the embodiment, the NAND cell type E
Although an EPROM has been described as an example, the present invention is not limited to this, and can be applied to various EEPROMs having a selection gate. More specifically, the present invention is not limited to the control gate type EEPROM, but is a NAND cell type EEPROM using MNOS type memory cells.
It is also applicable to EPROM. In addition, EEPR
Instead of the OM, a so-called mask ROM in which a MOS transistor in which information is fixedly written by channel ion implantation or the like is used as a memory cell can be applied when a NAND cell configuration is used.

The present invention can be applied to a ground array type, a FACE type, and an AND type cell having a diffusion layer bit line. Further, the present invention can be applied to a DINOR type having a sub-bit line. In addition, various modifications can be made without departing from the scope of the present invention.

[0058]

As described in detail above, according to the present invention, the area occupied by the select transistor is substantially reduced by forming the select transistor connected to the memory cell unit as a TFT above the memory cell unit. It is possible to realize a nonvolatile semiconductor memory device which can be eliminated and which can achieve higher integration.

[Brief description of the drawings]

FIG. 1 is a NAND cell type EEP according to a first embodiment.
FIG. 2 is a plan view showing a schematic configuration of a ROM.

FIG. 2 is a sectional view taken along line AA ′ of FIG.

FIG. 3 is an equivalent circuit diagram of the cell array shown in FIGS.

FIG. 4 is a diagram showing an example of a cell array arrangement according to the first embodiment.

FIG. 5 is an equivalent circuit diagram showing a modification of the first embodiment.

FIG. 6 shows a NAND cell type EEP according to a second embodiment.
FIG. 2 is a plan view showing a schematic configuration of a ROM.

FIG. 7 is an equivalent circuit diagram of the cell array shown in FIG.

FIG. 8 shows a NAND cell type EEP according to a third embodiment.
FIG. 2 is a plan view showing a schematic configuration of a ROM.

FIG. 9 is an equivalent circuit diagram of the cell array of FIG. 7;

FIG. 10 shows a NAND cell type EE according to a fourth embodiment.
FIG. 3 is an equivalent circuit diagram of a PROM.

FIG. 11 shows a NAND cell type EE according to a fifth embodiment.
FIG. 3 is an equivalent circuit diagram of a PROM.

FIG. 12 is a plan view showing one NAND cell of a conventional EEPROM.

FIG. 13 is a sectional view taken along line AA ′ and BB ′ in FIG. 11;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... n-type substrate 2 ... p well 3 ... 1st gate insulating film 4 ... floating gate 5 ... 2nd gate insulating film 6 ... control gate 7 ... n ⁺ layer 8 ... 1st interlayer insulating film 8a ... contact hole 9 ... silicon Film 9a channel region 9a, 9b source / drain region 10 gate insulating film for TFT 11 selection gate electrode 12 second interlayer insulating film 12a contact hole 13 bit line 15 element region 16 element isolation region

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/786

Claims (3)

[Claims] A plurality of memory cell units each having a charge storage layer and a control gate stacked on a semiconductor substrate and connecting a plurality of memory cells for writing and erasing by transferring charges between the charge storage layer and the substrate. In a nonvolatile semiconductor memory device, wherein each memory cell unit is connected to a data line via a selection transistor, the selection transistor is defined as a thin film semiconductor layer formed on the memory cell unit as a channel portion. A non-volatile semiconductor memory device comprising a thin film transistor. 2. An adjacent memory cell unit is connected to the same data line via a different selection transistor, one of the selection transistors connected to the data line is made conductive, and one of the adjacent memory cell units is connected to the other memory cell unit. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is selectively operated. 3. The memory cell unit according to claim 1, wherein a drain side is connected to a data line via a selection transistor, and a source side is connected to another data line via another selection transistor. Item 3. The nonvolatile semiconductor memory device according to Item 1.