JPH06325582A - Non-volatile storage device - Google Patents

Abstract

PURPOSE:To reduce probability of being subject to the effect of a depletion cell at the time of the read of information in a non-volatile storage device. CONSTITUTION:The sources of memory transistors sharing word lines WL1-WL4 are connected in common by source lines SL1-SL3. The drains of the memory transistors arrayed along the direction crossing with the word lines WL1-WL4 are connected in common by bit lines BL1, BL2. The word lines WL1-WL4 are bonded with the gates of each select transistor in a source open circuit 30, the source lines SL1-SL3 are connected to drains, and a source common line S/CL is connected in common with sources. When information is read, only select transistors sharing the word lines with the select memory transistors are turned on, and currents are made to flow through the source common line S/CL from the source lines connected to the select memory transistors. The select transistors sharing the word lines with non-selective memory transistors are turned off, and currents are not made to flow through the source common line S/CL from the source lines bonded with the non-selective memory transistors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an EEPROM (Electrically
The present invention relates to a non-volatile storage device such as Erasable Programmable Read On Memory) that semi-permanently stores information.

[0002]

2. Description of the Related Art FIG. 13 is a plan view showing the structure of a nonvolatile memory device. This figure shows a state in which the passivation film is peeled off. Referring to FIG. 1, a conventional nonvolatile memory device has a plurality of memory cells 2A, 2B, 2C, and 2D arranged in a matrix on a P-type silicon substrate 1 along a row direction and a column direction. There is.

Each of the memory cells 2A to 2D has a stack type memory transistor 4 having a floating gate 3.
It is composed of A, 4B, 4C and 4D. That is, it has a so-called 1 cell / 1 transistor structure. The control gates of the memory transistors 4A and 4B arranged in the column direction are extended in the column direction to form the word line WL1. Similarly, the control gates of the memory transistors 4C and 4D arranged in the column direction are
The word line WL2 is extended along the column direction.

The N ⁺ type source regions 5a of the memory transistors 4A and 4B sharing the word line WL1 extend in parallel with the word line WL1. Similarly, the memory transistors 4C and 4D sharing the word line WL2 are shared.
The N ⁺ type source region 5b extends in parallel with the word line WL2. A source line SL (see FIG. 14) is in contact with each of the source regions 5a and 5b through source contact holes 6a and 6b at the ends in the extension direction.

Memory transistors 4A and 4C adjacent to each other along the row direction, that is, the direction intersecting the word line WL1.
Share the N ⁺ -type drain region 7a, and the drain region 7a is in contact with the bit line BL1 (see FIG. 14) through the drain contact hole 8a. Similarly, the memory transistors 4B and 4D adjacent to each other along the direction intersecting the word line WL2 share the N ⁺ type drain region 7b, and the drain region 7b is shared.
Is in contact with the bit line BL2 (see FIG. 14) through the drain contact hole 8b.

FIG. 14 is an equivalent circuit diagram showing an electrical configuration of the nonvolatile memory device. Referring to the figure, word line WL1 is shared by memory transistors 4A and 4B arranged in the column direction, and word line WL2
Are memory transistors 4C and 4D arranged in the column direction.
Shared in. The source line SL is commonly connected to the sources of all the memory transistors 4A to 4D.

The bit lines BL1 and BL2 intersect the word lines WL1 and WL2. Bit line BL
1 denotes memory transistors 4A, 4 arranged in the row direction.
The bit line BL2 is shared by C, and the bit line BL2 is shared by the memory transistors 4B and 4D arranged in the row direction. Here, with reference to FIG. 14, an information reading operation in the nonvolatile memory device will be described. For example, assume that the information stored in the memory cell 2A is read. First,
While applying 0V to the source line SL, 5V is applied to the word line WL1 to which the memory cell 2A for reading information is connected. Then, in order to select the memory cell 2A, 1V is applied to the bit line BL1 to which the selected memory cell 2A is connected, and 0V is applied to the other word line WL2 and bit line BL2.

Then, in the selected memory cell 2A, if charges are accumulated in the floating gate FG of the memory transistor 4A, a channel is not formed between the source S and the drain D, and as a result, the memory transistor 4A does not conduct. That is, no cell current flows through the selected memory cell 2A. On the other hand, if no charge is stored in the floating gate FG of the memory transistor 4A, a channel is formed between the source S and the drain D, and as a result, the memory transistor 4A becomes conductive. That is, a cell current flows through the selected memory cell 2A as indicated by the solid line arrow in the figure. By sensing this state, reading of the information stored in the selected memory cell 2A is achieved.

In the following description, the memory transistors 4A to 4D are collectively referred to as "memory transistor 4".

[0010]

In the above non-volatile memory device, the operating characteristics of each memory transistor, that is, the operating speed varies, so that when erasing or writing information according to the driving method, the A so-called over-erased or over-written state may occur and the memory transistor may be in a depletion state.

That is, when the state in which electrons are accumulated in the floating gate FG of the memory transistor 4 is set as the writing state, for example, as shown in FIG. 15A, the control gate CG is set to -9V and the source is set. S
To the source S side by applying 0V to the substrate 1 while applying 5V to each of them, opening the drain D, and applying 0V to the substrate 1.
Information is erased by a so-called source extraction method in which N (Fowler-Nordheim) tunneling is performed and extraction is performed. Alternatively, as shown in FIG. 15B, -20V is applied to the control gate CG and the source S,
By applying 0V to the drain D and the substrate 1 respectively, an FN tunnel current is generated between the control gate CG and the substrate 1, and the electrons accumulated in the floating gate FG are extracted to the substrate 1 side by this FN tunnel current. Information may be erased by the substrate extraction method. At this time, if electrons are excessively extracted and become in an excessively erased state, holes are accumulated in the floating gate FG as shown in FIG. When holes are accumulated in the floating gate FG, the surface of the substrate 1 directly below the floating gate FG is affected by the holes and is inverted. As a result, a channel is formed between the source S and the drain D of the memory transistor 4, and the depletion state is set.

On the other hand, when the state in which the electrons are accumulated in the floating gate FG of the memory transistor 4 is to be the erased state, for example, as shown in FIG. 16A, the control gate CG is set to -7V and the drain D is set.
5V is applied to each of the source S and the substrate 1
0V is applied to the floating gate FG
Information is written by a so-called drain extraction method, in which the electrons accumulated in 1 are tunneled to the drain D side by FN and extracted. At this time, if the electrons are excessively extracted and the state becomes the excessive write state, FIG.
As shown in (b), holes are accumulated in the floating gate FG of the memory transistor 4,
Depression state is entered.

Referring again to FIG. 14, memory cell 2 sharing bit line BL1 with memory cell 2A, for example.
It is assumed that the information stored in the memory cell 2A is read when the memory transistor 4C of C is in the overerased or overwritten state. Unselected memory cell 2
In C, 0V is applied to the control gate CG and the source S of the memory transistor 4C, and 1V is applied to the drain D. At this time, since the memory transistor 4C is in the depletion state, even if no voltage is applied to the control gate, a cell current will flow in the unselected memory cell 2C as indicated by the dotted arrow in the figure. Therefore, the information stored in the non-selected memory cell 2C is erroneously read.

Therefore, in order to prevent the above-mentioned erroneous reading, a technique of performing verification in bit units to prevent the generation of depletion cells is described in "IE ² JOURNAL OF SOLID.
STATE CIRCUITS, VOL.24, NO.3, OCTOBER 1989 ". The verifying technique proposed in this document draws out the electrons accumulated in the floating gate while detecting the threshold distributions of all memory transistors, detects the cells in the depletion state, and determines the threshold distributions. By controlling so as to fall within a desired range, the probability of being affected by the depletion cell at the time of reading information is reduced.

However, if the above verification technique is adopted, a predetermined verification control circuit is required and the chip area becomes large. In addition, if the verification is performed every time the information is rewritten, the program time becomes rather long. In view of the above, the present invention provides a non-volatile memory device capable of reducing the probability that a selected cell is affected by a depletion cell at the time of reading information without increasing the chip area and lengthening the program time. With the goal.

[0016]

Means for solving the problems according to the present invention are arranged in a matrix on a semiconductor substrate,
A plurality of memory transistors each having a source, a drain, a gate, and a charge storage layer capable of storing charge, and storing information by injecting charge into the charge storage layer or extracting charge from the charge storage layer, A word line commonly connected to the gates of memory transistors arranged in a predetermined direction, a source line commonly connected to the sources of memory transistors sharing the word line, and a drain of memory transistors arranged in a direction intersecting the word line. A plurality of select transistors that are provided corresponding to the bit lines, the word lines and the source lines that are commonly connected to each other, and open the corresponding source lines. Each select transistor has a source, a drain and a gate. The corresponding word line is connected to the gate and the source Is a source open circuit in which the corresponding source line is connected to one of the drains and the source common line is commonly connected to the other of the source and the drain, and the information stored in the desired memory transistor is read out. Therefore, the means for selecting the memory transistor, the means for detecting a change in the potential of the bit line to which the selected memory transistor is connected at the time of reading the information, the means for selecting the memory transistor at the time of reading the information are connected. Means for applying a read voltage capable of generating a current between the source and drain of the memory transistor to the bit line, and a charge to the word line to which the selected memory transistor is connected at the time of reading information. Depending on the state of the storage layer, the source-drain of the memory transistor A sense voltage that can be turned on or off is applied, the select transistor connected to the selected word line is made conductive, and the source line connected to the selected transistor and the source common line are connected. At the same time, the ground potential is applied to the word line to which the unselected memory transistor is connected, and the select transistor connected to the unselected word line is connected to the select transistor without conducting. It includes means for disconnecting each source line from the source common line, and means for applying a predetermined voltage different from the read voltage to the source common line when reading information.

[0017]

In the above-mentioned means for solving the problems, at the time of reading information, the sense voltage is applied to the word line to which the selected memory transistor is connected, the read voltage is applied to the bit line, and the source common line is applied. And a predetermined voltage different from the read voltage is applied. At this time, if the charge is accumulated in the charge storage layer of the selected memory transistor, the influence of the sense voltage is blocked by the charge accumulated in the charge storage layer and does not reach the substrate. As a result, the source-drain of the memory transistor does not conduct and a channel is not formed, so that no current flows. On the other hand, if no charge is stored in the charge storage layer of the selected memory transistor, the influence of the sense voltage extends to the surface of the substrate, and the source-drain of the memory transistor becomes conductive.
A channel is formed and a current flows. By detecting the change in the potential of the bit line at this time, reading of the information stored in the selected memory transistor is achieved.

In the source open circuit, the select transistors sharing the selected word line become conductive, so that the source line connected to the select transistor and the source common line are connected. Therefore, the current generated in the selected memory transistor flows to the source common line via the source line connected to the selected memory transistor. on the other hand,
The select transistors sharing the unselected word line do not conduct, and the source line and the source common line connected to the select transistor are cut off. Therefore, even if the non-selected memory transistor sharing the bit line with the selected memory transistor is in the depletion state, the current of the depletion transistor is source common through each source line connected to the non-selected memory transistor. It doesn't flow on the line.

As described above, at the time of reading information, the source line connected to the selected memory transistor and the source common line are connected to each other, and only the current generated in the selected memory transistor flows in the source common line.
The source line to which the non-selected memory transistor is connected is opened, and the current generated in the non-selected memory transistor can be prevented from flowing to the source common line. The probability of being affected by the cell can be reduced.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a first embodiment of the present invention will be described with reference to FIGS.
It will be described in detail based on 0. FIG. 1 shows the configuration of a non-volatile memory device according to the first embodiment of the present invention.
Is a plan view showing a state in which the passivation film is peeled off, FIG. 7B is a sectional view taken along line II-II of FIG.
FIG. 4B is a sectional view taken along line IV-IV of FIG. Referring to FIG. 1A, the nonvolatile memory device of this embodiment includes a memory cell array 20 and a source open circuit 30 on a P-type silicon substrate 10.

The memory cell array 20 includes a plurality of memory cells 21A, 21B, 21C, 21D, 21E, 21F, 2 arranged in a matrix along the row and column directions.
1G, 21H, and each memory cell 21A-21
H is a stack type memory transistor 22A, 22B,
22C, 22D, 22E, 22F, 22G, 22H. That is, it has a 1-cell / 1-transistor structure.

The source open circuit 30 includes memory transistors 22A, 22B, 22C and 22D arranged in the column direction.
, 22E, 22F, and 22G, 22H, respectively, are provided with a plurality of MOS type select transistors 31A, 31B, 31C, 31D arranged in the row direction. The memory transistor and the select transistor which are adjacent in the column direction are shown in FIG.
Only G, 22H and select transistor 31D appear. ), Element isolation is performed by a plurality of field oxide films 40 which are formed thickly on the surface layer of the silicon substrate 10 at predetermined intervals.

Each of the memory transistors 22A to 22H is
FIG. 1B (memory transistors 22A, 22C, 22
Only E and 22G appear. ), The source region 23 and the drain region 24 are formed on the surface layer of the silicon substrate 10 with a predetermined space, and each source region 23.
And the tunnel oxide film 26 formed on the channel region 25 sandwiched between the drain regions 24 and the floating gate 2 formed on each tunnel oxide film 26.
7 and ON formed on each floating gate 27
An O (oxide-nitride-oxide) film 28 and a control gate 29 formed on the ONO film 28 are provided.

As shown in FIG. 1B, each source region 23 has a so-called single source structure composed of an N ⁺ layer, and is shared by memory transistors adjacent in the row direction. Each drain region 24 is shown in FIG.
As shown in FIG. 5, the so-called LDD (l) is composed of an N ⁺ layer 24a and P ⁺ layers 24b joined to both ends of the N ⁺ layer 24a.
ight doped drain) structure, which is shared by memory transistors adjacent to each other in the row direction.

The tunnel oxide film 26 is formed in each channel region 2.
The charge generated in 5 is tunneled. Therefore, the tunnel oxide film 26 is made of SiO ₂ , and its film thickness is extremely thin so that the charges can be tunneled. Each floating gate 27 is for accumulating charges tunneling through the tunnel oxide film 26, and is made of, for example, polysilicon in which As, P, etc. are highly doped to reduce the resistance. This floating gate 2
7 are arranged in an island shape as shown in FIG.

Each ONO film 28 is for confining charges in the floating gate 27 for a long time, and has a structure in which a Si ₃ N ₄ film is sandwiched between upper and lower SiO ₂ films. Each control gate 29 has
A predetermined control voltage is applied at the time of writing, erasing, and reading of information, and is made of, for example, polysilicon in which As, P, etc. are highly doped to reduce the resistance.

Select transistors 31A to 31D
Is a silicon substrate 10 as shown in FIGS.
Formed on the surface layer of the N ⁺ type source region 32 and the N ⁺ type drain region 33 at a predetermined interval, and a gate formed on the channel region sandwiched between the source region 32 and the drain region 33. An oxide film 34 and a gate 35 formed on the gate oxide film 34 are provided. The gate oxide film 34 is provided relatively thicker than the tunnel oxide film 26.

Memory transistors 2 arranged along the column direction
The control gates 29 of 2A and 22B correspond to the select transistor 3 of the source open circuit 30 along the column direction.
The word line WL1 is extended to above 1A. The end of the word line WL1 in the extending direction is the gate 35 of the select transistor 31A.
Similarly, the memory transistors 22 arranged in the column direction are arranged.
C, 22D, and 22E, 22F, and 22G, 22
The H control gate 29 is also extended along the column direction onto the select transistor 31A of the source open circuit 30, and the word lines WL2, WL3, and W, respectively.
It is L4. Also, the word lines WL2, WL
The ends of the WLs 3 and 4 in the extending direction also serve as the gates 35 of the select transistors 31B to 31D.

The source regions 23 of the memory transistors arranged in the column direction extend in parallel with the word lines WL1 to WL4, and select transistors 31A to 31A, respectively.
Source line SL connected to the drain region 33 of 31D
1, SL2, SL3. The whole surface is shown in Fig. 1 (b).
As shown in FIG. 5, it is covered with the interlayer insulating film 50. Therefore, each floating gate 27 is surrounded by an insulating film,
Not connected to the outside. The interlayer insulating film 50 is made of P-doped SiO ₂ PSG (phosho-silicate-glass).
BPSG (bron-phosho-silicate-glas) with B mixed in
s) etc. On the interlayer insulating film 50, FIG.
As shown in FIG.
Drain contact holes 61 and 6 are provided at the locations corresponding to
2, 63 and 64 are opened, and source contact holes 71 and 72 are opened at locations corresponding to the source regions 33 of the select transistors.

As shown in FIG. 1B, the bit line BL1 passes through the drain contact hole 61 shared by the memory transistors 22A and 22C and the drain contact hole 63 shared by the memory transistors 22E and 22G. Transistors 22A, 22
The drain regions 24 shared by C, 22E, and 22G are in contact with each other. Similarly, the drain contact hole 62 shared by the memory transistors 22B and 22D, and the memory transistors 22F and 2D.
The bit line BL2 (see FIG. 2) is in contact with the drain regions 24 shared by the memory transistors 22B and 22D and 22F and 22H, respectively, through the drain contact hole 64 shared by 2H. As shown in FIG. 1B, the bit lines BL1 and BL2 intersect the word lines WL1 to WL4 and extend in the row direction.

The source common line S / CL is provided through the source contact hole 71 shared by the select transistors 31A and 31B and the source contact hole 72 shared by the select transistors 31C and 31D.
(See FIG. 2) are select transistors 31A, 31
The source regions 32 shared by B, 31C, and 31D are in contact with each other.

FIG. 2 is an equivalent circuit diagram showing the electrical configuration of the nonvolatile memory device. Referring to the figure, the word line WL1 has memory transistors 22 arranged in the column direction.
It is shared by A, 22B and select transistor 31A. Similarly, for the other word lines WL2 to WL4, the memory transistors 22C and 22D, the select transistor 31B, and the memory transistor 22 arranged in the column direction are arranged.
E, 22F, select transistor 31C, and memory transistors 22G, 22H, select transistor 31
It is shared by D respectively.

In the figure, the source line SL1 at the left end is
Memory transistors 22A, 22 arranged along the column direction
B, shared by Select Transistor 31A. The source line SL2 is shared by the memory transistors 22C and 22D, the select transistor 31B, and the memory transistors 22E and 22F and the select transistor 31C that are arranged in the column direction. Right source line SL3
Are memory transistors 22A, 2 arranged in the column direction.
2B, shared by select transistor 31A.

The bit lines BL1 and BL2 intersect the word lines WL1 to WL4. The bit line BL1 has memory transistors 22 arranged in the row direction.
It is shared by A, 22C, 22E and 22G. Similarly, the bit line BL2 is shared by the memory transistors 22B, 22D, 22F, 22H arranged in the row direction.

The source common line S / CL is shared by the select transistors 31A to 31D arranged in the row direction. A common substrate line SUB is provided on the substrates. A row decoder 81 is connected to the word lines WL1 to WL4. The row decoder 81 uses word lines WL1 to WL1 when writing, erasing and reading information.
4 is for applying a predetermined voltage.

A column decoder 82 is connected to the bit lines BL1 and BL2. The column decoder 82 uses the bit lines BL1 and BL1 when writing, erasing and reading information.
It is for applying a predetermined voltage to 2. A sense amplifier (SA) 83 is connected to the column decoder 82. The sense amplifier 83 is for detecting a change in the potential of the bit line to which the selected memory transistor is connected when reading information.

A source control circuit 84 is connected to the source common line S / CL. The source control circuit 84, when writing, erasing and reading information,
This is for applying a predetermined voltage to the source lines SL1 to SL3. A substrate control circuit 85 is connected to the substrate line SUB. The substrate control circuit 85 is for applying a predetermined voltage to the substrate line SUB when writing, erasing and reading information.

The row decoder 81, the column decoder 82, the sense amplifier 83, the source control circuit 84, and the substrate control circuit 85 are supplied with control signals from a control circuit (not shown) and are controlled by these control signals. Here, FIG.
9 to 9 and Tables 1 to 3, the operations of writing, erasing, and reading information in the nonvolatile memory device will be described. Note that Tables 1 to 3 show different driving methods.

First, it is assumed that the driving method shown in Table 1 is adopted.
Table 1 shows a driving method in which hot electrons are injected into the floating gate at the time of writing information and electrons accumulated in the floating gate are pulled out to the source side at the time of erasing information.

[0040]

[Table 1]

<Write (WRITE)> For example, in FIG. 2, it is assumed that information is written in the memory cell 21A. First, the source control circuit 84 and the substrate control circuit 85 apply 0V to the source common line S / CL and the substrate line SUB, respectively. The memory cell 21 in which information is written by the row decoder 81.
12V to word line WL1 to which A is connected
Is applied. Then, in order to select the memory cell 21A, the row decoder 81 and the column decoder 82 apply 5V to the bit line BL1 to which the memory cell 21A is connected, and at the same time, other word lines WL2 to W2.
0V is applied to L4 and bit line BL2, respectively.

Then, in the selected memory cell 21A,
As shown in FIG. 3, a high electric field is applied between the control gate 29 and the drain region 24 of the memory transistor 22A, and a saturated channel current flows between the source region 23 and the drain region 24. In the pinch-off region of the drain region 24, the electrons accelerated by the high electric field are ionized (i
So-called hot electrons with high energy are generated. The hot electrons FN tunnel the tunnel oxide film 26,
It is injected into the floating gate 27 near the drain region 24. The electrons injected into the floating gate 27 are confined in the floating gate 27 for a long time by the ONO film 28. As a result, the selected memory cell 21A is in the state of writing the information "1".

The gate voltage required for conducting between the source and drain differs between the state where electrons are accumulated in the floating gate and the state where electrons are not accumulated. That is, the threshold voltage V _TH for conducting between the source and the drain is higher than the threshold voltage V 1 (for example, 7) when the electrons of the floating gate are injected.
V), and a low threshold V2 (for example, 1.5 V) is taken in a state where electrons have not been injected. Thus, by setting the threshold voltage V _TH to two types, binary data of “1” or “0” can be stored in the memory cell. <Erase> Information is erased collectively for each word line. For example, in FIG. 2, it is assumed that the information stored in the memory cells 21A and 21B arranged along the word line WL1 is erased. Column decoder 8
2, all the bit lines BL1 and BL2 are opened, the source control circuit 84 applies 5V to the source common line S / CL, and the substrate control circuit 85 applies 0V to the substrate line SUB. . In order to select the memory cells 21A and 21B,
With respect to the word line WL1 by the row decoder 81,
9V is applied and other word lines WL2 to WL
0V is applied to 4.

Then, the selected memory cells 21A, 21
In B, as shown in FIG.
The electrons accumulated in the
It is pulled out after N tunneling. As a result, the information stored in the selected memory cells 21A and 21B is erased. <Read (READ)> For example, in FIG. 2, it is assumed that the information stored in the memory cell 21A is read. First, the source control circuit 84 and the substrate control circuit 85 apply 0V to the source common line S / CL and the substrate line SUB, respectively. The row decoder 81 applies a sense voltage of 5V to the word line WL1 to which the memory cell 21A is connected. Then, the memory cell 21A is selected by the row decoder 81 and the column decoder 82 in order to select the memory cell 21A.
1V is applied to the bit line BL1 to which the bit lines are connected, and 0V is applied to the other word lines WL2 to WL4 and the bit line BL2.

Then, in the selected memory cell 21A,
As shown in FIG. 5A, when electrons are accumulated in the floating gate 27 of the memory transistor 21A, the influence of the positive charge of the control gate 29 is blocked by the electrons in the floating gate 27, and Substrate 10 immediately below 27
Does not reach Therefore, the memory transistor 21A
The source region 23-drain region 24 are not conductive, and a channel is not formed. That is, no cell current flows in the selected memory cell 21A. On the other hand, as shown in FIG. 5B, when electrons are not accumulated in the floating gate 27 of the memory transistor 21A,
The influence of positive charges on the control gate 29 extends to the substrate 10 directly below the floating gate 27, and the surface of the substrate 10 is inverted. Therefore, the source region 23 and the drain region 24 of the memory transistor 22A become conductive, and a channel is formed. That is, a cell current flows in the selected memory cell 21A. By sensing this state with the decoders 81 and 82 and the sense amplifier 83, the memory cell 2
Reading of the information stored in 1A is accomplished.

Here, the sense voltage is an intermediate voltage between two types of threshold voltages V _TH , V1 and V2. Therefore, when this sense voltage is applied, conduction / non-conduction between the source and drain is determined by whether or not electrons are accumulated in the floating gate. next,
It is assumed that the driving method shown in Table 2 is adopted. Table 2 shows that electrons are injected into the floating gates of the memory transistors in all the memory cells in advance, all the memory cells are set in the erased state, and the electrons accumulated in the floating gates at the time of writing information are transferred to the drain side. The drive method of pulling out is shown.

[0047]

[Table 2]

<Write (WRITE)> For example, in FIG. 2, it is assumed that information is written in the memory cell 21A. First, when writing information, all memory cells 21A ...
Electrons are collectively injected into the floating gates of the memory transistors 22A to 20D in 21D to put all the memory cells 21A to 21D in an erased state. Then, the source control circuit 84 causes the source common line S
/ CL is opened and 0V is applied to the substrate line SUB by the substrate control circuit 85. The row decoder 81 applies -7V to the word line WL1 to which the memory cell 21A for writing information is connected. In order to select the memory cell 21A,
By the row decoder 81 and the column decoder 82, 5 is applied to the bit line BL1 to which the memory cell 21A is connected.
V is applied and other word lines WL2 to WL4
To the bit line BL2 and 1 V to the bit line BL2.

Then, in the selected memory cell 21A,
As shown in FIG. 6, the electrons accumulated in the floating gate 27 of the memory transistor 22A are
It is extracted to the drain region 24 side by FN tunneling. As a result, the selected memory cell 21A has information "0".
Will be in the write state. <Erase> Information is erased collectively for each word line. For example, it is assumed that the information stored in the memory cells 21A and 21B arranged along the word line WL1 is erased. First, the column decoder 82
The source control circuit 84 and the substrate control circuit 85 apply −5V to all the bit lines BL1 and BL2, the source common line S / CL, and the substrate line SUB. Then, the memory cell 21A,
In order to select 21B, the row decoder 81 applies 20V to the word line WL1 to which the memory cells 21A and 21B for erasing information are connected, and
0V is applied to the other word lines WL2 to WL4.

Then, the selected memory cells 21A, 21A
In B, as shown in FIG.
F between the control gates 29 of A and 22B and the substrate 10
An N tunnel current is generated, and electrons are injected into the floating gate 27 by this FN tunnel current. As a result, the selected memory cells 21A and 21B are in the erased state of information.

The read operation is similar to that of the hot electron injection method, and therefore its explanation is omitted.
Then, it is assumed that the driving method shown in Table 3 is adopted. Table 3 shows a driving method in which an FN tunnel current is generated between the control gate and the substrate and electrons are injected into the floating gate by the FN tunnel current.

[0052]

[Table 3]

<Write (WRITE)> For example, in FIG. 2, it is assumed that information is written in the memory cell 21A. First, the source control circuit 84 and the substrate control circuit 85 apply 0V to the source common line S / CL and the substrate line SUB. The row decoder 81 applies 20V to the word line WL1 to which the memory cell 21A for writing information is connected. Then, the memory cell 21A is selected by the row decoder 81 and the column decoder 82 in order to select the memory cell 21A.
0V is applied to the bit line BL1 connected to the same, 0V is applied to the other word lines WL2 to WL4, and 7V is applied to the bit line BL2.

Then, in the selected memory cell 21A,
As shown in FIG. 8, memory transistors 22A and 22B
An FN tunnel current is generated between the control gate 29 and the substrate 10, and electrons are injected into the floating gate 27 by this FN tunnel current. As a result, the selected memory cells 21A and 21B are in the state of writing the information "1". <Erase> Information is erased collectively for each word line. For example, in FIG. 2, the memory cells 21A and 2A arranged along the word line WL1.
It is assumed that the information stored in 1B is erased. First,
By the column decoder 82, the source control circuit 84, and the substrate control circuit 85, all bit lines BL
0V is applied to 1, BL2, the source common line S / CL, and the substrate line SUB. Then, in order to select the memory cells 21A and 21B, the row decoder 81 applies −20 V to the word line WL1 to which the memory cells 21A and 21B for erasing information are connected, and the other word lines WL2. 0V is applied to WL4.

Then, the selected memory cells 21A, 21
In B, as shown in FIG.
A bias reverse to that at the time of writing is applied between the control gates 29 of A and 22B and the substrate 10, and F at the opposite direction to that at the time of writing
An N tunnel current is generated, and the electrons accumulated in the floating gate 27 escape to the substrate 10 side by the FN tunnel current. As a result, the selected memory cell 2
1A and 21B are in the erased state of information.

The read operation is similar to that of the hot electron injection method, and therefore its explanation is omitted.
FIG. 10 is a diagram showing a cell current flow at the time of reading. Referring to the figure, for example, when reading information, memory cell 21A
Is selected, as described above, the source common line S
0V is applied to / CL and the substrate line SUB and 5V is applied to the selected word line WL1.
However, 1V is applied to the selected bit line BL1. In addition, unselected word lines WL2 to
0V is applied to the WL4 and the bit line BL2, respectively.

At this time, the selected word line WL1
5V is applied to the gate of the select transistor 31A that shares the same, and when the select transistor 31A is turned on, the source line SL1 connected to the selected memory cell 21A and the source common line S / CL are connected. . That is, the source line SL1 is grounded. Therefore, the cell current generated in the selected memory cell 21A flows to the source common line S / CL via the source line SL1 and drops to the ground, as shown by the arrow in the figure.

On the other hand, unselected word lines WL2 to WL
Select transistors 31B to 31D sharing 4
Since 0V is applied to the gate of each of the source transistors and the select transistors 31B to 31D remain off, the source lines SL2 and SL connected to the non-selected memory cells are connected.
3 and the source common line S / CL are cut off.
That is, the source lines SL2 and SL3 are opened.
Therefore, even if a cell that does not share the source line SL1 among the unselected memory cells that share the selected bit line BL1 is in the depletion state, the cell current of the depletion cell is from the source line to the source. Does not flow to the common line S / CL. That is, the probability that the information stored in the non-selected memory cell to which the source line SL1 is not connected is erroneously read is reduced.

As described above, in the above nonvolatile memory device,
At the time of reading information, only the select transistor sharing the word line with the selected memory cell is turned on, the source line connected to the selected memory cell is grounded so that a current flows, and the unselected memory cell and the word line are connected. It is possible to turn off the select transistor sharing the memory cell and open the source line to which the non-selected memory cell is connected so that no current flows. The probability of receiving it can be reduced. Therefore, it is not necessary to perform verification on a bit-by-bit basis to prevent erroneous reading, the chip area does not increase, and the programming time is short.

Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 11 is an equivalent circuit diagram of the nonvolatile memory device according to the second embodiment of the present invention. Referring to the figure, in the nonvolatile memory device of the present embodiment, the memory cells arranged along the word lines WL1 to WL4 without sharing the source lines SL1 to SL4 with the memory transistors arranged along the bit lines BL1 and BL2. It is different from the first embodiment in that it is shared only by the transistors, and the other configurations are the same.

FIG. 12 is a diagram showing the flow of cell current during reading. Referring to the figure, for example, when the memory cell 21A is selected at the time of reading information, the source control circuit 84 and the substrate control circuit 85 cause 0 to the source lines SL1 to SL3 and the substrate line SUB.
V is applied. Further, the row decoder 81 and the column decoder 82 apply 5V to the word line WL1 and 1V to the bit line BL1, respectively, and apply 0V to the other word lines WL2 to WL4 and the bit line BL2. Will be applied respectively.

At this time, the selected word line WL1
By turning on the select transistor 31A sharing the same, the source line SL1 connected to the selected memory cell 21A is grounded. for that reason,
If electrons are accumulated in the floating gate of the memory transistor 22A in the selected memory cell 21A, the cell current flows through the source line SL along the path indicated by the arrow in the figure.
1 and the source common line S / CL to ground.

On the other hand, unselected word lines WL2 to WL
Select transistors 31B to 31D sharing 4
Remains off, the source lines SL2 to SL4 connected to the non-selected memory cells are opened. Thereby, even if any of the unselected memory cells sharing the selected bit line BL1 is in the depletion state, the cell current of the depletion cell does not flow to the source common line S / CL. In particular, even if the non-selected memory cell sharing the source line SL1 with the selected memory cell 21A is a depletion cell, the information stored in this depletion cell is not erroneously read.

As described above, in the above nonvolatile memory device,
Since the source line is not shared by the memory transistors arranged along the bit lines, but is shared only by the memory transistors arranged along the word lines, the word line is shared with the selected memory cell when reading information. The selected select transistor is turned on, the source line connected to the selected memory cell is grounded, and the select transistor sharing the word line with the unselected memory cell is turned off to connect the unselected memory cell. By setting the open source line to the open state, the selected memory cell is not affected by the non-selected depletion cell during reading.

The present invention is not limited to the above embodiments, and it goes without saying that many modifications and changes can be made within the scope of the present invention. For example, in the above-described embodiment, an example in which a memory transistor that stores electric charge in the floating gate is used has been described, but the same effect can be obtained even if the floating gate is eliminated and the electric charge is stored in the ONO film or the NO film. To get

[0066]

As is apparent from the above description, according to the present invention, at the time of reading information, the source line connected to the selected memory transistor and the source common line are connected to each other, which is generated in the selected memory transistor. Only the current flows in the source common line, the source line connected to the non-selected memory transistor is opened, and the current generated in the non-selected memory transistor can be prevented from flowing in the source common line. Therefore, it is possible to reduce the probability that the selected memory cell is affected by the non-selected depletion cell during reading.

Therefore, it is not necessary to perform verification on a bit-by-bit basis to prevent erroneous reading, and as a result, the chip area does not increase, and the programming time can be shortened.

[Brief description of drawings]

FIG. 1 shows a configuration of a nonvolatile memory device according to a first embodiment of the present invention, FIG. 1 (a) is a plan view showing a state in which a passivation film is removed, and FIG. 1 (b) is the same. Figure (a)
II-II line sectional view of the same, (c) is a IV-IV of the same (a)
It is a line sectional view.

FIG. 2 is an equivalent circuit diagram showing an electrical configuration of a nonvolatile memory device.

FIG. 3 is a diagram showing an information writing operation of a memory transistor by a hot electron injection method.

FIG. 4 is a diagram showing an information erasing operation of a memory transistor.

FIG. 5 is a diagram showing an operation of reading information from a memory transistor.

FIG. 6 is a diagram showing an information writing operation of a memory transistor by a drain extraction method.

FIG. 7 is a diagram showing an information erasing operation of a memory transistor.

FIG. 8 is a diagram showing an information writing operation of a memory transistor by an FN tunnel method.

FIG. 9 is a diagram showing an information erasing operation of a memory transistor.

FIG. 10 is a diagram showing the flow of cell current during reading.

FIG. 11 is an equivalent circuit diagram showing an electrical configuration of a nonvolatile memory device according to Example 2 of the present invention.

FIG. 12 is a diagram showing the flow of cell current during reading.

FIG. 13 is a plan view showing a configuration of a conventional nonvolatile memory device.

FIG. 14 is an equivalent circuit diagram showing an electrical configuration of a nonvolatile memory device.

FIG. 15 is a diagram showing an erasing operation of information in a memory transistor when a state in which charges are accumulated is set to a writing state.

FIG. 16 is a diagram showing an information writing operation of a memory transistor in the case where an electric charge is stored in an erased state.

[Explanation of symbols]

 10 silicon substrate 20 memory cell array 21A to 21D memory cell 22A to 22D memory transistor 30 source open circuit 31A to 31D select transistor WL1 to WL4 word line SL1 to SL4 source line BL1, BL2 bit line S / CL source common line 81 row decoder 82 column decoder 83 sense amplifier 84 source control circuit 85 board control circuit

Claims (1)

[Claims] 1. A semiconductor substrate is provided with a source, a drain, a gate, and a charge storage layer capable of storing charges, which are arranged in a matrix on a semiconductor substrate, and charge is injected into or from the charge storage layer. Multiple memory transistors that store information by extracting charges, word lines that are commonly connected to the gates of memory transistors that line up in a predetermined direction, and sources of memory transistors that share word lines are commonly connected A source line, a bit line commonly connecting the drains of the memory transistors arranged in a direction intersecting the word line, and provided corresponding to each word line and source line,
The select transistor includes a plurality of select transistors for opening the corresponding source line. Each select transistor has a source, a drain and a gate, and the corresponding word line is connected to the gate, and either the source or the drain is connected. A source open circuit in which a corresponding source line is connected to one of the sources and a source common line is commonly connected to the other of the source and the drain, and in order to read the information stored in a desired memory transistor, Means for selecting memory transistor, Means for detecting potential change of bit line to which selected memory transistor is connected at the time of reading information, Bit line to which selected memory transistor is connected at reading of information In contrast, between the source and drain of the memory transistor Means for applying a read voltage capable of generating a current flow, and when reading information, a word line connected to a selected memory transistor is electrically connected between the source and drain of the memory transistor according to the state of the charge storage layer. A sense voltage that can be turned on or off is applied, the select transistor connected to the selected word line is made conductive, and the source line connected to the select transistor and the source common line are connected. And apply a ground potential to the word line to which the non-selected memory transistor is connected,
Means for disconnecting each source line and source common line connected to the select transistor without turning on each select transistor to which the non-selected word line is connected, and a source common when reading information. A non-volatile memory device including means for applying a predetermined voltage different from a read voltage to a line.